|
Extracted the display state machine, moving it into a separate library module. |
|
|
Introduced a display configuration structure to be included in an application, |
|
|
Introduced framebuffer usage and replaced the DMA interrupt with a Timer2 event, |
|
|
Introduced a parameter for FPB in uart_init, eliminating this dependency on the |
|
|
Introduced dual pixel transfer channels to the timer-based VGA example, also |
|
|
Introduced various definitions for transfer and display-related properties. |
|
|
Experiment with interleaved DMA channels. |
|
|
Replaced usage of the DMA interrupt with the Timer3 event for the zero channel. |
|
|
Replaced usage of the DMA interrupt with the Timer2 event for the zero channel. |
|
|
Added support for a framebuffer, also providing a common library function to |
|
|
Moved .data into flash. Otherwise, it appears that certain pointer arithmetic |
|
|
Added a function to update the source of a DMA channel. |
|
|
Organised header and common payload files into include and lib directories. |
|
|
Added a VGA example variant employing timer-scheduled single-pixel transfers. |
|
|
Updated the documentation to be more specific to this example. |
|
|
Added a parallel mode variant of the VGA example. |
|
|
Introduced device configuration files for individual programs together with |
|
|
Fixed parallel mode write strobe configuration. |
|
|
Added support for parallel mode. |
|
|
Added the documentation from the VGAPIC32 project. |
|
|
Removed superfluous variable declaration. |
|
|
Added support for external interrupt configuration. |
|
|
Corrected the description of the frequency generation mechanism, changing the |
|
|
Fixed the description of the interrupt configuration of OC1. |
|
|
The timer and OC interrupts do not need to be enabled to initiate DMA transfers. |
|
|
Removed debugging output showing line data. |
|
|
Introduced separate example directories containing the demonstration program and |
|
|
Added more DMA channel configuration functions. |
|
|
Introduced proper allocation of the IRQ stack. |
|
|
Reformatted using spaces. |
|
|
Fixed comments, indicating that it is the UART interrupt being handled that |
|
|
Introduced some UART convenience functions. |
|
|
Handle the channel completion interrupt correctly, allowing it to occur again. |
|
|
It appears unnecessary to re-enable the first DMA channel. Thus, handling a DMA |
|
|
Moved application-specific pin configuration into the main program. |
|
|
Added copyright and licensing information. |
|
|
Added output compare support, demonstrating its use with DMA cell transfers. |
|
|
Demonstrated DMA channel chaining with cell transfers initiated using timer |
|
|
Added a debugging function for writing strings. |
|
|
Restored the DMA transfer upon UART receive interrupt condition functionality. |
|
|
Introduced separate configuration functions for DMA auto-enable and chaining. |
|
|
Fixed the DCHxDSIZ offset and added some more definitions. |
|
|
Test with higher-priority interrupt, disabling DMA, due to instability. |
|
|
Added timer initialisation functions. |
|
|
Extended the use and scope of the UART interrupt flags function. |
|
|
Renamed various files to be less specific to a particular application. |
|
|
Added a note about the peripheral clock frequency. |
|
|
Introduced parameterised initialisation of DMA and UART peripherals. |
|
|
Added address translation macros. |
|
|
Added read-only data positioning. |
|
|
Some tidied-up configuration and initialisation routines and a simple UART test. |
|
