# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1539964259 -7200
# Node ID 0f9eb8bc112d20aea4fe6d07ed1772b7876ec433
# Parent  ffb0fa616eaf80857df9ff9b3b70bb9bec813847
Handle the channel completion interrupt correctly, allowing it to occur again.

diff -r ffb0fa616eaf -r 0f9eb8bc112d main.c
--- a/main.c	Fri Oct 19 17:13:56 2018 +0200
+++ b/main.c	Fri Oct 19 17:50:59 2018 +0200
@@ -85,6 +85,7 @@
     dma_set_transfer(1, PHYSICAL((uint32_t) message2), sizeof(message2) - 1,
                         HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
                         1);
+    dma_init_interrupt(1, 0b00001000, 7, 3);
 
     /* Configure a timer for the first DMA channel whose interrupt condition
        drives the transfer but is not handled (having a lower priority than the
@@ -157,6 +158,18 @@
                 dma_on(0);
         }
     }
+
+    /* Check for a DMA interrupt condition (CHBCIF). */
+
+    ifs = REG(DMAIFS) & DMA_INT_FLAGS(1, 1);
+
+    if (ifs)
+    {
+        uart_write_string("CHBCIF\r\n");
+        INV_REG(PORTA, 1 << 2);
+        CLR_REG(DMA_REG(1, DCHxINT), 0b11111111);
+        CLR_REG(DMAIFS, ifs);
+    }
 }