# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1540064918 -7200
# Node ID 3e6c6b06ca0b23c5d9554f0ece0a0ca299a9720f
# Parent  d1ce7d9d76aa198534b249e23f45bd2cf515c89e
The timer and OC interrupts do not need to be enabled to initiate DMA transfers.

diff -r d1ce7d9d76aa -r 3e6c6b06ca0b examples/demo/main.c
--- a/examples/demo/main.c	Sat Oct 20 19:26:44 2018 +0200
+++ b/examples/demo/main.c	Sat Oct 20 21:48:38 2018 +0200
@@ -69,6 +69,14 @@
 
     init_dma();
 
+    /* Peripheral relationships:
+
+       Timer2 -> DMA0: message1 -> U1TXREG
+                    \___
+                        \
+       Timer3 -> OC1 -> DMA1: message2 -> U1TXREG
+    */
+
     /* Initiate DMA on the Timer2 interrupt. Since the channel is not
        auto-enabled, it must be explicitly enabled elsewhere (when a UART
        interrupt is handled). */
@@ -91,11 +99,9 @@
     dma_init_interrupt(1, 0b00001000, 7, 3);
 
     /* Configure a timer for the first DMA channel whose interrupt condition
-       drives the transfer but is not handled (having a lower priority than the
-       CPU. */
+       drives the transfer. The interrupt itself does not need to be enabled. */
 
     timer_init(2, 0b111, 60000);
-    timer_init_interrupt(2, 1, 3);
     timer_on(2);
 
     /* Configure a timer for the output compare unit below. */
@@ -105,12 +111,11 @@
 
     /* Configure output compare in dual compare (continuous output) mode using
        Timer3 as time base. The interrupt condition drives the second DMA
-       channel but is not handled (having a lower priority than the CPU). */
+       channel but does not need to be enabled. */
 
     oc_init(1, 0b101, 3);
     oc_set_pulse(1, 10000);
     oc_set_pulse_end(1, 20000);
-    oc_init_interrupt(1, 1, 3);
     oc_on(1);
 
     /* Set UART interrupt priority above CPU priority to process events and to