# HG changeset patch # User Paul Boddie # Date 1557003258 -7200 # Node ID d112c32b7417dd805f91e3e00ffcc6ea49cace24 # Parent 751c61390702984445e6bb1609b7c0aae3d0d54c Moved VGA example documentation into the wiki documentation. diff -r 751c61390702 -r d112c32b7417 docs/wiki/Examples--vga --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/wiki/Examples--vga Sat May 04 22:54:18 2019 +0200 @@ -0,0 +1,100 @@ += VGA Output Example = + +This example demonstrates the generation of an analogue VGA signal from a +PIC32 microcontroller using general output pins. It follows on from the work +done in the VGAPIC32 project. The result is not entirely satisfactory: + + * Every fourth pixel is wider than the others, this apparently being an + artefact of the DMA transfer mechanism. + +It might be possible to introduce some kind of delay and even out the pixel +widths, but this has not been investigated with hardware. However, unlike the +[[../vga-pmp|vga-pmp]] example, there is no accompanying signal to potentially +orchestrate the staging of individual pixels at a slightly delayed rate. + +Attempts to introduce other remedies to the wide pixel problem have been made +with the [[../vga-dual|vga-dual]] and [[../vga-timer|vga-timer]] examples. + +== Hardware Details == + +The pin usage of this solution is documented below. + +=== PIC32MX270F256B-50I/SP Pin Assignments === + +{{{ +MCLR# 1 \/ 28 +HSYNC/OC1/RA0 2 27 +VSYNC/OC2/RA1 3 26 RB15/U1TX + D0/RB0 4 25 RB14 + D1/RB1 5 24 RB13/U1RX + D2/RB2 6 23 + D3/RB3 7 22 RB11/PGEC2 + 8 21 RB10/PGEC3 + RA2 9 20 + RA3 10 19 + D4/RB4 11 18 RB9 + 12 17 RB8 + 13 16 RB7/D7 + D5/RB5 14 15 +}}} + +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS +unlike the MX170 variant). + +=== UART Connections === + +UART1 is exposed by the RB13 and RB15 pins. + +=== Data Signal Routing === + +For one bit of intensity, two bits per colour channel: + +{{{ +D7 -> 2200R -> I + +I -> diode -> R +I -> diode -> G +I -> diode -> B + +D6 (not connected) + +D5 -> 470R -> R +D4 -> 1000R -> R +D3 -> 470R -> G +D2 -> 1000R -> G +D1 -> 470R -> B +D0 -> 1000R -> B + +HSYNC -> HS +VSYNC -> VS +}}} + +=== Output Socket Pinout === + +{{{ +5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) + + 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) + +15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) +}}} + +=== Output Cable Pinout === + +{{{ + 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) + +6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) + + 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) +}}} + +== References == + +https://en.wikipedia.org/wiki/VGA_connector + +http://papilio.cc/index.php?n=Papilio.VGAWing + +http://lucidscience.com/pro-vga%20video%20generator-2.aspx + +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 docs/wiki/Examples--vga-cpu --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/wiki/Examples--vga-cpu Sat May 04 22:54:18 2019 +0200 @@ -0,0 +1,120 @@ += VGA Output Example (CPU-Driven Transfers) = + +This example demonstrates the generation of an analogue VGA signal from a +PIC32 microcontroller using general output pins. Instead of using DMA, which +was the focus of the VGAPIC32 project and is a central feature of the +approaches demonstrated by other examples ([[../vga|vga]], +[[../vga-dual|vga-dual]], [[../vga-pmp|vga-pmp]], [[../vga-timer|vga-timer]]), +here the CPU is given the task of transferring pixel data to the output pins. + +Instead of a timer interrupt condition initiating DMA transfers, the interrupt +is handled and a routine invoked to issue the necessary load and store +instructions in a loop. Otherwise, the use of the timer to generate sync +pulses is as in the other examples and the general display state machine is +largely the same. + +The resulting picture is more pleasing than that produced by most of the DMA +examples in that the display pixels have consistent widths. Moreover, the +pixels are also narrower than those produced by the [[../vga-timer|vga-timer]] +example. It is possible to generate a display with something approaching 200 +pixels horizontally, with 160 pixels being demonstrated. + +However, the CPU now spends a lot of time occupied in an interrupt request +handler generating pixels. This seems less elegant than using DMA, but in +practice, the CPU may be effectively stalled where DMA transfers dominate +access to the RAM. Even if, in such situations, the CPU may be able to access +flash memory to load instructions, programs typically end up accessing RAM at +some point, and this would effectively limit the concurrency within the +system. Certainly, this approach seems to result in slower programs than the +plain DMA-based approach. + +One potential advantage of this approach is in the flexibility that might be +achieved by manipulating the pixel data. With DMA, data is transferred as it +is found and is generally not transformed (although there are some features in +the PIC32 DMA controller for certain kinds of data), whereas we might envisage +supporting display modes employing fewer bits for the output signal, reducing +the number of colours but also the size of the framebuffer. + +== Hardware Details == + +The pin usage of this solution is documented below. + +=== PIC32MX270F256B-50I/SP Pin Assignments === + +{{{ +MCLR# 1 \/ 28 +HSYNC/OC1/RA0 2 27 +VSYNC/OC2/RA1 3 26 RB15/U1TX + D0/RB0 4 25 RB14 + D1/RB1 5 24 RB13/U1RX + D2/RB2 6 23 + D3/RB3 7 22 RB11/PGEC2 + 8 21 RB10/PGEC3 + RA2 9 20 + RA3 10 19 + D4/RB4 11 18 RB9 + 12 17 RB8 + 13 16 RB7/D7 + D5/RB5 14 15 +}}} + +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS +unlike the MX170 variant). + +=== UART Connections === + +UART1 is exposed by the RB13 and RB15 pins. + +=== Data Signal Routing === + +For one bit of intensity, two bits per colour channel: + +{{{ +D7 -> 2200R -> I + +I -> diode -> R +I -> diode -> G +I -> diode -> B + +D6 (not connected) + +D5 -> 470R -> R +D4 -> 1000R -> R +D3 -> 470R -> G +D2 -> 1000R -> G +D1 -> 470R -> B +D0 -> 1000R -> B + +HSYNC -> HS +VSYNC -> VS +}}} + +=== Output Socket Pinout === + +{{{ +5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) + + 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) + +15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) +}}} + +=== Output Cable Pinout === + +{{{ + 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) + +6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) + + 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) +}}} + +== References == + +https://en.wikipedia.org/wiki/VGA_connector + +http://papilio.cc/index.php?n=Papilio.VGAWing + +http://lucidscience.com/pro-vga%20video%20generator-2.aspx + +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 docs/wiki/Examples--vga-dual --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/wiki/Examples--vga-dual Sat May 04 22:54:18 2019 +0200 @@ -0,0 +1,109 @@ += VGA Output Example (Dual-Channel DMA Transfers) = + +This example demonstrates the generation of an analogue VGA signal from a +PIC32 microcontroller using general output pins. It follows on from the work +done in the VGAPIC32 project. The result is not entirely satisfactory: + + * Every fourth pixel is wider than the others, this apparently being an + artefact of the DMA transfer mechanism. + +It might be possible to introduce some kind of delay and even out the pixel +widths, but this has not been investigated with hardware. However, unlike the +[[../vga-pmp|vga-pmp]] example, there is no accompanying signal to potentially +orchestrate the staging of individual pixels at a slightly delayed rate. +Potentially, the peripheral clock signal might be generated and processed to +make such a signal. + +Unlike the [[../vga|vga]] example, this example employs two DMA channels for +pixel data which are interleaved to investigate a potential remedy for the +wide pixel effect. Unfortunately, despite each channel contributing every +other word (or group of four pixels), the effect persists. However, the +picture is perhaps more stable than in the [[../vga|vga]] example. + +One significant problem with this example is that scrolling causes the DMA +channels to become ordered incorrectly. This does not affect the +[[../vga-timer|vga-timer]] example which also employs two DMA channels. + +== Hardware Details == + +The pin usage of this solution is documented below. + +=== PIC32MX270F256B-50I/SP Pin Assignments === + +{{{ +MCLR# 1 \/ 28 +HSYNC/OC1/RA0 2 27 +VSYNC/OC2/RA1 3 26 RB15/U1TX + D0/RB0 4 25 RB14 + D1/RB1 5 24 RB13/U1RX + D2/RB2 6 23 + D3/RB3 7 22 RB11/PGEC2 + 8 21 RB10/PGEC3 + RA2 9 20 + RA3 10 19 + D4/RB4 11 18 RB9 + 12 17 RB8 + 13 16 RB7/D7 + D5/RB5 14 15 +}}} + +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS +unlike the MX170 variant). + +=== UART Connections === + +UART1 is exposed by the RB13 and RB15 pins. + +=== Data Signal Routing === + +For one bit of intensity, two bits per colour channel: + +{{{ +D7 -> 2200R -> I + +I -> diode -> R +I -> diode -> G +I -> diode -> B + +D6 (not connected) + +D5 -> 470R -> R +D4 -> 1000R -> R +D3 -> 470R -> G +D2 -> 1000R -> G +D1 -> 470R -> B +D0 -> 1000R -> B + +HSYNC -> HS +VSYNC -> VS +}}} + +=== Output Socket Pinout === + +{{{ +5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) + + 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) + +15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) +}}} + +=== Output Cable Pinout === + +{{{ + 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) + +6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) + + 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) +}}} + +== References == + +https://en.wikipedia.org/wiki/VGA_connector + +http://papilio.cc/index.php?n=Papilio.VGAWing + +http://lucidscience.com/pro-vga%20video%20generator-2.aspx + +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 docs/wiki/Examples--vga-pmp --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/wiki/Examples--vga-pmp Sat May 04 22:54:18 2019 +0200 @@ -0,0 +1,113 @@ += VGA Output Example (Parallel Mode Transfers) = + +This example demonstrates the generation of an analogue VGA signal from a +PIC32 microcontroller using the parallel mode (parallel master port, PMP) +peripheral. The result is not entirely satisfactory: + + * Pixels are very narrow unless buffered using a flip-flop driven by the + peripheral, this being a characteristic of the way the peripheral works, it + normally being used to drive memory and display controllers. + + * Introducing a flip-flop means that the final pixel from the pixel data + remains asserted and must be reset using a second DMA channel. + + * Every fourth pixel is wider than the others, this apparently being an + artefact of the DMA transfer mechanism. + +It might be possible introduce some kind of delay to the write strobe (PMWR) +and even out the pixel widths, but this has not been investigated. + +It appears to be the case that the system and peripheral clock frequencies +need to be matched. In this example, a frequency of 48MHz has been chosen. + +== Hardware Details == + +The pin usage of this solution is documented below. + +=== PIC32MX270F256B-50I/SP Pin Assignments === + +{{{ +MCLR# 1 \/ 28 + D7/PMD7/RA0 2 27 + D6/PMD6/RA1 3 26 RB15/U1TX + D0/PMD0/RB0 4 25 RB14 + D1/PMD1/RB1 5 24 RB13/(PMRD)/U1RX + D2/PMD2/RB2 6 23 + PMWR/RB3 7 22 RB11/PGEC2 + 8 21 RB10/PGEC3 + RA2 9 20 + (PMA0)/RA3 10 19 +HSYNC/OC1/RB4 11 18 RB9/PMD3/D3 + 12 17 RB8/PMD4/D4 + 13 16 RB7/PMD5/D5 +VSYNC/OC2/RB5 14 15 +}}} + +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS +unlike the MX170 variant). + +=== UART Connections === + +UART1 is exposed by the RB13 and RB15 pins. + +=== Data Signal Routing === + +A flip-flop is used to buffer the outputs: + +{{{ +Dn -> 74HC273:Dn + 74HC273:Qn -> Qn +VCC -> 74HC273:MR# +PMWR -> 74HC273:CP +}}} + +For two bits of intensity, two bits per colour channel: + +{{{ +Q7 -> 2200R -> I +Q6 -> 4700R -> I + +I -> diode -> R +I -> diode -> G +I -> diode -> B + +Q5 -> 470R -> R +Q4 -> 1000R -> R +Q3 -> 470R -> G +Q2 -> 1000R -> G +Q1 -> 470R -> B +Q0 -> 1000R -> B + +HSYNC -> HS +VSYNC -> VS +}}} + +=== Output Socket Pinout === + +{{{ +5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) + + 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) + +15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) +}}} + +=== Output Cable Pinout === + +{{{ + 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) + +6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) + + 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) +}}} + +== References == + +https://en.wikipedia.org/wiki/VGA_connector + +http://papilio.cc/index.php?n=Papilio.VGAWing + +http://lucidscience.com/pro-vga%20video%20generator-2.aspx + +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 docs/wiki/Examples--vga-timer --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/wiki/Examples--vga-timer Sat May 04 22:54:18 2019 +0200 @@ -0,0 +1,147 @@ += VGA Output Example (Timed DMA Transfers) = + +This example demonstrates the generation of an analogue VGA signal from a +PIC32 microcontroller using general output pins. Unlike the [[../vga|vga]] and +[[../vga-pmp|vga-pmp]] examples, it employs a regular interrupt condition to +schedule single-byte (single-pixel) DMA transfers instead of a single +whole-line transfer. + +The principal advantage of this method over the whole-line transfer method is +its production of pixels with consistent widths. The principal disadvantage is +the significant loss of horizontal resolution due to the latencies involved in +propagating interrupt conditions to the DMA controller and thereby initiating +each transfer. + +Employing a peripheral clock that has half the frequency of the system clock +should ensure the stability of the picture, since the lower frequency may make +transfers easier to schedule. The peripheral clock should provide a more +forgiving deadline for each transfer, permitting late transfers to complete on +time. + +Meanwhile, matching the system and peripheral clock frequencies appears to +leave the scheduling of transfers open to uncertainty, with transfers being +more readily delayed by other activity in the system, and with instability of +the picture being the result. + +Unlike the [[../vga|vga]] example, but in common with the +[[../vga-dual|vga-dual]] example, this example employs two DMA channels for +pixel data which are interleaved to investigate a potential remedy for the +wide pixel effect. This seems to preserve consistent pixel widths only with a +transfer cell size of 1: other cell sizes suffer from the wide pixel problem. +Despite not offering the greater throughput of larger cell sizes, merely +employing dual channels increases throughput for a cell size of 1, making the +technique worth using. + +In contrast to the [[../vga|vga]] and [[../vga-pmp|vga-pmp]] examples, a +special DMA channel is employed to initiate the pixel transfer process without +actually transferring any pixel data itself. The channel arrangement is as +follows: + +|| Transfer Initiator || DMA Channel || Transfer Activity || +|| Timer2 || DMA1 || zerodata -> PORTB || +|| Timer3 || DMA0 || linedata -> PORTB || +|| Timer3 || DMA2 || linedata -> PORTB || +|| Timer3 || DMA3 || zerodata -> PORTB || + +The real purpose of this channel (DMA1) is to capture the Timer2 interrupt +condition and to enable the following channels (DMA0, DMA2) through channel +chaining. Having been enabled, DMA0 and DMA2 are then able to conduct +transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or +"zero" channel to ensure that the pixel level is set to black at the end of +each display line. + +In principle, other initiating conditions can be used instead of Timer3, which +is configured to produce such conditions as frequently as possible: + + * A persistent interrupt condition can be employed instead. For example, + configuring UART2 and setting the UART2 transfer interrupt, employing this + interrupt condition for DMA0 and DMA2, produces the same effect. + + * An external interrupt such as INT2 can be configured, and the peripheral + clock can be routed through the CLKO pin and back into the microcontroller + via an appropriate pin. With INT2 being employed as the interrupt + condition for DMA0 and DMA2, the same effect is produced. + +== Hardware Details == + +The pin usage of this solution is documented below. + +=== PIC32MX270F256B-50I/SP Pin Assignments === + +{{{ +MCLR# 1 \/ 28 +HSYNC/OC1/RA0 2 27 +VSYNC/OC2/RA1 3 26 RB15/U1TX + D0/RB0 4 25 RB14 + D1/RB1 5 24 RB13/U1RX + D2/RB2 6 23 + D3/RB3 7 22 RB11/PGEC2 + 8 21 RB10/PGEC3 + RA2 9 20 + RA3 10 19 + D4/RB4 11 18 RB9 + 12 17 RB8 + 13 16 RB7/D7 + D5/RB5 14 15 +}}} + +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS +unlike the MX170 variant). + +=== UART Connections === + +UART1 is exposed by the RB13 and RB15 pins. + +=== Data Signal Routing === + +For one bit of intensity, two bits per colour channel: + +{{{ +D7 -> 2200R -> I + +I -> diode -> R +I -> diode -> G +I -> diode -> B + +D6 (not connected) + +D5 -> 470R -> R +D4 -> 1000R -> R +D3 -> 470R -> G +D2 -> 1000R -> G +D1 -> 470R -> B +D0 -> 1000R -> B + +HSYNC -> HS +VSYNC -> VS +}}} + +=== Output Socket Pinout === + +{{{ +5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) + + 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) + +15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) +}}} + +=== Output Cable Pinout === + +{{{ + 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) + +6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) + + 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) +}}} + +== References == + +https://en.wikipedia.org/wiki/VGA_connector + +http://papilio.cc/index.php?n=Papilio.VGAWing + +http://lucidscience.com/pro-vga%20video%20generator-2.aspx + +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 docs/wiki/VGA_Output_Examples --- a/docs/wiki/VGA_Output_Examples Thu May 02 23:21:32 2019 +0200 +++ b/docs/wiki/VGA_Output_Examples Sat May 04 22:54:18 2019 +0200 @@ -1,4 +1,12 @@ -= VGA Output Example Comparison = += VGA Output Examples = + + * [[Examples/vga|vga]] + * [[Examples/vga-cpu|vga-cpu]] + * [[Examples/vga-dual|vga-dual]] + * [[Examples/vga-pmp|vga-pmp]] + * [[Examples/vga-timer|vga-timer]] + +== Comparison == In investigating different techniques, the following observations have been made about the behaviour of the different VGA examples: diff -r 751c61390702 -r d112c32b7417 examples/vga-cpu/README.txt --- a/examples/vga-cpu/README.txt Thu May 02 23:21:32 2019 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,119 +0,0 @@ -Introduction ------------- - -This example demonstrates the generation of an analogue VGA signal from a -PIC32 microcontroller using general output pins. Instead of using DMA, which -was the focus of the VGAPIC32 project and is a central feature of the -approaches demonstrated by other examples (vga, vga-dual, vga-pmp, vga-timer), -here the CPU is given the task of transferring pixel data to the output pins. - -Instead of a timer interrupt condition initiating DMA transfers, the interrupt -is handled and a routine invoked to issue the necessary load and store -instructions in a loop. Otherwise, the use of the timer to generate sync -pulses is as in the other examples and the general display state machine is -largely the same. - -The resulting picture is more pleasing than that produced by most of the DMA -examples in that the display pixels have consistent widths. Moreover, the -pixels are also narrower than those produced by the vga-timer example. It is -possible to generate a display with something approaching 200 pixels -horizontally, with 160 pixels being demonstrated. - -However, the CPU now spends a lot of time occupied in an interrupt request -handler generating pixels. This seems less elegant than using DMA, but in -practice, the CPU may be effectively stalled where DMA transfers dominate -access to the RAM. Even if, in such situations, the CPU may be able to access -flash memory to load instructions, programs typically end up accessing RAM at -some point, and this would effectively limit the concurrency within the -system. Certainly, this approach seems to result in slower programs than the -plain DMA-based approach. - -One potential advantage of this approach is in the flexibility that might be -achieved by manipulating the pixel data. With DMA, data is transferred as it -is found and is generally not transformed (although there are some features in -the PIC32 DMA controller for certain kinds of data), whereas we might envisage -supporting display modes employing fewer bits for the output signal, reducing -the number of colours but also the size of the framebuffer. - -Hardware Details -================ - -The pin usage of this solution is documented below. - -PIC32MX270F256B-50I/SP Pin Assignments --------------------------------------- - -MCLR# 1 \/ 28 -HSYNC/OC1/RA0 2 27 -VSYNC/OC2/RA1 3 26 RB15/U1TX - D0/RB0 4 25 RB14 - D1/RB1 5 24 RB13/U1RX - D2/RB2 6 23 - D3/RB3 7 22 RB11/PGEC2 - 8 21 RB10/PGEC3 - RA2 9 20 - RA3 10 19 - D4/RB4 11 18 RB9 - 12 17 RB8 - 13 16 RB7/D7 - D5/RB5 14 15 - -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS -unlike the MX170 variant). - -UART Connections ----------------- - -UART1 is exposed by the RB13 and RB15 pins. - -Data Signal Routing -------------------- - -For one bit of intensity, two bits per colour channel: - -D7 -> 2200R -> I - -I -> diode -> R -I -> diode -> G -I -> diode -> B - -D6 (not connected) - -D5 -> 470R -> R -D4 -> 1000R -> R -D3 -> 470R -> G -D2 -> 1000R -> G -D1 -> 470R -> B -D0 -> 1000R -> B - -HSYNC -> HS -VSYNC -> VS - -Output Socket Pinout --------------------- - - 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) - - 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) - - 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) - -Output Cable Pinout -------------------- - - 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) - - 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) - - 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) - -References ----------- - -https://en.wikipedia.org/wiki/VGA_connector - -http://papilio.cc/index.php?n=Papilio.VGAWing - -http://lucidscience.com/pro-vga%20video%20generator-2.aspx - -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 examples/vga-dual/README.txt --- a/examples/vga-dual/README.txt Thu May 02 23:21:32 2019 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,109 +0,0 @@ -Introduction ------------- - -This example demonstrates the generation of an analogue VGA signal from a -PIC32 microcontroller using general output pins. It follows on from the work -done in the VGAPIC32 project. The result is not entirely satisfactory: - - * Every fourth pixel is wider than the others, this apparently being an - artefact of the DMA transfer mechanism. - -It might be possible to introduce some kind of delay and even out the pixel -widths, but this has not been investigated with hardware. However, unlike the -vga-pmp example, there is no accompanying signal to potentially orchestrate -the staging of individual pixels at a slightly delayed rate. Potentially, the -peripheral clock signal might be generated and processed to make such a -signal. - -Unlike the vga example, this example employs two DMA channels for pixel data -which are interleaved to investigate a potential remedy for the wide pixel -effect. Unfortunately, despite each channel contributing every other word (or -group of four pixels), the effect persists. However, the picture is perhaps -more stable than in the vga example. - -One significant problem with this example is that scrolling causes the DMA -channels to become ordered incorrectly. This does not affect the vga-timer -example which also employs two DMA channels. - -Hardware Details -================ - -The pin usage of this solution is documented below. - -PIC32MX270F256B-50I/SP Pin Assignments --------------------------------------- - -MCLR# 1 \/ 28 -HSYNC/OC1/RA0 2 27 -VSYNC/OC2/RA1 3 26 RB15/U1TX - D0/RB0 4 25 RB14 - D1/RB1 5 24 RB13/U1RX - D2/RB2 6 23 - D3/RB3 7 22 RB11/PGEC2 - 8 21 RB10/PGEC3 - RA2 9 20 - RA3 10 19 - D4/RB4 11 18 RB9 - 12 17 RB8 - 13 16 RB7/D7 - D5/RB5 14 15 - -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS -unlike the MX170 variant). - -UART Connections ----------------- - -UART1 is exposed by the RB13 and RB15 pins. - -Data Signal Routing -------------------- - -For one bit of intensity, two bits per colour channel: - -D7 -> 2200R -> I - -I -> diode -> R -I -> diode -> G -I -> diode -> B - -D6 (not connected) - -D5 -> 470R -> R -D4 -> 1000R -> R -D3 -> 470R -> G -D2 -> 1000R -> G -D1 -> 470R -> B -D0 -> 1000R -> B - -HSYNC -> HS -VSYNC -> VS - -Output Socket Pinout --------------------- - - 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) - - 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) - - 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) - -Output Cable Pinout -------------------- - - 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) - - 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) - - 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) - -References ----------- - -https://en.wikipedia.org/wiki/VGA_connector - -http://papilio.cc/index.php?n=Papilio.VGAWing - -http://lucidscience.com/pro-vga%20video%20generator-2.aspx - -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 examples/vga-pmp/README.txt --- a/examples/vga-pmp/README.txt Thu May 02 23:21:32 2019 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,111 +0,0 @@ -Introduction ------------- - -This example demonstrates the generation of an analogue VGA signal from a -PIC32 microcontroller using the parallel mode (parallel master port, PMP) -peripheral. The result is not entirely satisfactory: - - * Pixels are very narrow unless buffered using a flip-flop driven by the - peripheral, this being a characteristic of the way the peripheral works, it - normally being used to drive memory and display controllers. - - * Introducing a flip-flop means that the final pixel from the pixel data - remains asserted and must be reset using a second DMA channel. - - * Every fourth pixel is wider than the others, this apparently being an - artefact of the DMA transfer mechanism. - -It might be possible introduce some kind of delay to the write strobe (PMWR) -and even out the pixel widths, but this has not been investigated. - -It appears to be the case that the system and peripheral clock frequencies -need to be matched. In this example, a frequency of 48MHz has been chosen. - -Hardware Details -================ - -The pin usage of this solution is documented below. - -PIC32MX270F256B-50I/SP Pin Assignments --------------------------------------- - -MCLR# 1 \/ 28 - D7/PMD7/RA0 2 27 - D6/PMD6/RA1 3 26 RB15/U1TX - D0/PMD0/RB0 4 25 RB14 - D1/PMD1/RB1 5 24 RB13/(PMRD)/U1RX - D2/PMD2/RB2 6 23 - PMWR/RB3 7 22 RB11/PGEC2 - 8 21 RB10/PGEC3 - RA2 9 20 - (PMA0)/RA3 10 19 -HSYNC/OC1/RB4 11 18 RB9/PMD3/D3 - 12 17 RB8/PMD4/D4 - 13 16 RB7/PMD5/D5 -VSYNC/OC2/RB5 14 15 - -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS -unlike the MX170 variant). - -UART Connections ----------------- - -UART1 is exposed by the RB13 and RB15 pins. - -Data Signal Routing -------------------- - -A flip-flop is used to buffer the outputs: - -Dn -> 74HC273:Dn - 74HC273:Qn -> Qn -VCC -> 74HC273:MR# -PMWR -> 74HC273:CP - -For two bits of intensity, two bits per colour channel: - -Q7 -> 2200R -> I -Q6 -> 4700R -> I - -I -> diode -> R -I -> diode -> G -I -> diode -> B - -Q5 -> 470R -> R -Q4 -> 1000R -> R -Q3 -> 470R -> G -Q2 -> 1000R -> G -Q1 -> 470R -> B -Q0 -> 1000R -> B - -HSYNC -> HS -VSYNC -> VS - -Output Socket Pinout --------------------- - - 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) - - 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) - - 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) - -Output Cable Pinout -------------------- - - 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) - - 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) - - 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) - -References ----------- - -https://en.wikipedia.org/wiki/VGA_connector - -http://papilio.cc/index.php?n=Papilio.VGAWing - -http://lucidscience.com/pro-vga%20video%20generator-2.aspx - -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 examples/vga-timer/README.txt --- a/examples/vga-timer/README.txt Thu May 02 23:21:32 2019 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,145 +0,0 @@ -Introduction ------------- - -This example demonstrates the generation of an analogue VGA signal from a -PIC32 microcontroller using general output pins. Unlike the vga and vga-pmp -examples, it employs a regular interrupt condition to schedule single-byte -(single-pixel) DMA transfers instead of a single whole-line transfer. - -The principal advantage of this method over the whole-line transfer method is -its production of pixels with consistent widths. The principal disadvantage is -the significant loss of horizontal resolution due to the latencies involved in -propagating interrupt conditions to the DMA controller and thereby initiating -each transfer. - -Employing a peripheral clock that has half the frequency of the system clock -should ensure the stability of the picture, since the lower frequency may make -transfers easier to schedule. The peripheral clock should provide a more -forgiving deadline for each transfer, permitting late transfers to complete on -time. - -Meanwhile, matching the system and peripheral clock frequencies appears to -leave the scheduling of transfers open to uncertainty, with transfers being -more readily delayed by other activity in the system, and with instability of -the picture being the result. - -Unlike the vga example, but in common with the vga-dual example, this example -employs two DMA channels for pixel data which are interleaved to investigate a -potential remedy for the wide pixel effect. This seems to preserve consistent -pixel widths only with a transfer cell size of 1: other cell sizes suffer from -the wide pixel problem. Despite not offering the greater throughput of larger -cell sizes, merely employing dual channels increases throughput for a cell -size of 1, making the technique worth using. - -In contrast to the vga and vga-pmp examples, a special DMA channel is employed -to initiate the pixel transfer process without actually transferring any pixel -data itself. The channel arrangement is as follows: - - Transfer Initiator DMA Channel Transfer Activity - ------------------ ----------- ----------------- - Timer2 DMA1 zerodata -> PORTB - Timer3 DMA0 linedata -> PORTB - Timer3 DMA2 linedata -> PORTB - Timer3 DMA3 zerodata -> PORTB - -The real purpose of this channel (DMA1) is to capture the Timer2 interrupt -condition and to enable the following channels (DMA0, DMA2) through channel -chaining. Having been enabled, DMA0 and DMA2 are then able to conduct -transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or -"zero" channel to ensure that the pixel level is set to black at the end of -each display line. - -In principle, other initiating conditions can be used instead of Timer3, which -is configured to produce such conditions as frequently as possible: - - * A persistent interrupt condition can be employed instead. For example, - configuring UART2 and setting the UART2 transfer interrupt, employing this - interrupt condition for DMA0 and DMA2, produces the same effect. - - * An external interrupt such as INT2 can be configured, and the peripheral - clock can be routed through the CLKO pin and back into the microcontroller - via an appropriate pin. With INT2 being employed as the interrupt - condition for DMA0 and DMA2, the same effect is produced. - -Hardware Details -================ - -The pin usage of this solution is documented below. - -PIC32MX270F256B-50I/SP Pin Assignments --------------------------------------- - -MCLR# 1 \/ 28 -HSYNC/OC1/RA0 2 27 -VSYNC/OC2/RA1 3 26 RB15/U1TX - D0/RB0 4 25 RB14 - D1/RB1 5 24 RB13/U1RX - D2/RB2 6 23 - D3/RB3 7 22 RB11/PGEC2 - 8 21 RB10/PGEC3 - RA2 9 20 - RA3 10 19 - D4/RB4 11 18 RB9 - 12 17 RB8 - 13 16 RB7/D7 - D5/RB5 14 15 - -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS -unlike the MX170 variant). - -UART Connections ----------------- - -UART1 is exposed by the RB13 and RB15 pins. - -Data Signal Routing -------------------- - -For one bit of intensity, two bits per colour channel: - -D7 -> 2200R -> I - -I -> diode -> R -I -> diode -> G -I -> diode -> B - -D6 (not connected) - -D5 -> 470R -> R -D4 -> 1000R -> R -D3 -> 470R -> G -D2 -> 1000R -> G -D1 -> 470R -> B -D0 -> 1000R -> B - -HSYNC -> HS -VSYNC -> VS - -Output Socket Pinout --------------------- - - 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) - - 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) - - 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) - -Output Cable Pinout -------------------- - - 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) - - 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) - - 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) - -References ----------- - -https://en.wikipedia.org/wiki/VGA_connector - -http://papilio.cc/index.php?n=Papilio.VGAWing - -http://lucidscience.com/pro-vga%20video%20generator-2.aspx - -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga diff -r 751c61390702 -r d112c32b7417 examples/vga/README.txt --- a/examples/vga/README.txt Thu May 02 23:21:32 2019 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,100 +0,0 @@ -Introduction ------------- - -This example demonstrates the generation of an analogue VGA signal from a -PIC32 microcontroller using general output pins. It follows on from the work -done in the VGAPIC32 project. The result is not entirely satisfactory: - - * Every fourth pixel is wider than the others, this apparently being an - artefact of the DMA transfer mechanism. - -It might be possible to introduce some kind of delay and even out the pixel -widths, but this has not been investigated with hardware. However, unlike the -vga-pmp example, there is no accompanying signal to potentially orchestrate -the staging of individual pixels at a slightly delayed rate. - -Attempts to introduce other remedies to the wide pixel problem have been made -with the vga-dual and vga-timer examples. - -Hardware Details -================ - -The pin usage of this solution is documented below. - -PIC32MX270F256B-50I/SP Pin Assignments --------------------------------------- - -MCLR# 1 \/ 28 -HSYNC/OC1/RA0 2 27 -VSYNC/OC2/RA1 3 26 RB15/U1TX - D0/RB0 4 25 RB14 - D1/RB1 5 24 RB13/U1RX - D2/RB2 6 23 - D3/RB3 7 22 RB11/PGEC2 - 8 21 RB10/PGEC3 - RA2 9 20 - RA3 10 19 - D4/RB4 11 18 RB9 - 12 17 RB8 - 13 16 RB7/D7 - D5/RB5 14 15 - -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS -unlike the MX170 variant). - -UART Connections ----------------- - -UART1 is exposed by the RB13 and RB15 pins. - -Data Signal Routing -------------------- - -For one bit of intensity, two bits per colour channel: - -D7 -> 2200R -> I - -I -> diode -> R -I -> diode -> G -I -> diode -> B - -D6 (not connected) - -D5 -> 470R -> R -D4 -> 1000R -> R -D3 -> 470R -> G -D2 -> 1000R -> G -D1 -> 470R -> B -D0 -> 1000R -> B - -HSYNC -> HS -VSYNC -> VS - -Output Socket Pinout --------------------- - - 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) - - 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) - - 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) - -Output Cable Pinout -------------------- - - 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) - - 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) - - 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) - -References ----------- - -https://en.wikipedia.org/wiki/VGA_connector - -http://papilio.cc/index.php?n=Papilio.VGAWing - -http://lucidscience.com/pro-vga%20video%20generator-2.aspx - -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga