# HG changeset patch # User Paul Boddie # Date 1539791775 -7200 # Node ID d878ce48d7d4346b015bedd64e859772095e7696 # Parent c1b168829e0b84e71754552fdcc23ddd2fd48359 Renamed various files to be less specific to a particular application. diff -r c1b168829e0b -r d878ce48d7d4 Makefile --- a/Makefile Wed Oct 17 17:53:08 2018 +0200 +++ b/Makefile Wed Oct 17 17:56:15 2018 +0200 @@ -1,4 +1,4 @@ -# Makefile - Build the IntCondTest payload +# Makefile - Build the PIC32 deployment payload # # Copyright (C) 2015, 2017, 2018 Paul Boddie # Copyright (C) Xiangfu Liu @@ -33,7 +33,7 @@ -march=mips32 LDFLAGS = -nostdlib -EL -TARGET = intcond.elf +TARGET = payload.elf DUMP = $(TARGET:.elf=.dump) MAP = $(TARGET:.elf=.map) SCRIPT = $(TARGET:.elf=.ld) @@ -43,8 +43,8 @@ # Ordering of objects is important and cannot be left to replacement rules. -SRC = intcond.S main.c init.c cpu.S -OBJ = intcond.o main.o init.o cpu.o +SRC = start.S main.c init.c cpu.S +OBJ = start.o main.o init.o cpu.o .PHONY: all clean distclean diff -r c1b168829e0b -r d878ce48d7d4 intcond.S --- a/intcond.S Wed Oct 17 17:53:08 2018 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,98 +0,0 @@ -/* - * PIC32 microcontroller initialisation code. - * - * Copyright (C) 2017, 2018 Paul Boddie - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "mips.h" -#include "pic32.h" - -/* Disable JTAG functionality on pins. */ - -.section .devcfg0, "a" -.word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ - -/* -Set the oscillator to be the FRC oscillator with PLL, with peripheral clock -divided by 2, and FRCDIV+PLL selected. - -The watchdog timer (FWDTEN) is also disabled. - -The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with -RPB4. -*/ - -.section .devcfg1, "a" -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1; - DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ - -/* -Set the FRC oscillator PLL function with an input division of 4, an output -division of 2, a multiplication of 24, yielding a multiplication of 3. - -The FRC is apparently at 16MHz and this produces a system clock of 48MHz. - -The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 -settings. -*/ - -.section .devcfg2, "a" -.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; - DEVCFG2<6:4> = FPLLMUL<2:0> = 111; - DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ - -/* The start routine is placed at the boot location. */ - -.section .boot, "a" - -.globl _start -.extern main - -_start: - /* Enable caching. */ - - mfc0 $v1, CP0_CONFIG - li $t8, ~CONFIG_K0 - and $v1, $v1, $t8 - ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT - mtc0 $v1, CP0_CONFIG - nop - - /* Get the RAM size. */ - - la $v1, BMXDRMSZ - lw $t0, 0($v1) - - /* Initialise the stack pointer. */ - - li $v1, KSEG0_BASE - addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */ - - /* Initialise the globals pointer. */ - - lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) - ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) - - /* - Jump to the main program. Since the boot code is separate from the - other code, the address cannot be obtained via the GOT. - ("relocation truncated to fit: R_MIPS_PC16 against `main'") - */ - - lui $t9, %hi(main) - ori $t9, $t9, %lo(main) - jr $t9 - nop diff -r c1b168829e0b -r d878ce48d7d4 intcond.ld --- a/intcond.ld Wed Oct 17 17:53:08 2018 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(_start) - -/* See... - * FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX170/270 DEVICES (64 KB RAM, 256 KB FLASH) - * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet - */ - -MEMORY -{ - kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x10000 - kseg0_boot_mem (rx) : ORIGIN = 0x9FC00000, LENGTH = 0xBF0 - kseg0_program_mem (rx) : ORIGIN = 0x9D000000, LENGTH = 0x40000 - physical_boot_mem (rx) : ORIGIN = 0x1FC00000, LENGTH = 0xBF0 - physical_program_mem (rx) : ORIGIN = 0x1D000000, LENGTH = 0x40000 - sfrs : ORIGIN = 0xBF800000, LENGTH = 0x100000 - configsfrs : ORIGIN = 0xBFC00BF0, LENGTH = 0x10 - config3 : ORIGIN = 0xBFC00BF0, LENGTH = 0x4 - config2 : ORIGIN = 0xBFC00BF4, LENGTH = 0x4 - config1 : ORIGIN = 0xBFC00BF8, LENGTH = 0x4 - config0 : ORIGIN = 0xBFC00BFC, LENGTH = 0x4 - physical_config3 : ORIGIN = 0x3FC00BF0, LENGTH = 0x4 - physical_config2 : ORIGIN = 0x3FC00BF4, LENGTH = 0x4 - physical_config1 : ORIGIN = 0x3FC00BF8, LENGTH = 0x4 - physical_config0 : ORIGIN = 0x3FC00BFC, LENGTH = 0x4 -} - -SECTIONS -{ - .boot : { *(.boot*) } > kseg0_boot_mem AT > physical_boot_mem - .vectors : { *(.vectors*) } > kseg0_program_mem AT > physical_program_mem - .text : { *(.text*) } > kseg0_program_mem AT > physical_program_mem - .bss : { *(.bss*) } > kseg1_data_mem - .rodata : { *(.rodata*) } > kseg0_program_mem AT > physical_program_mem - .got : { - _gp = ALIGN(16); - *(.got*) - } > kseg0_program_mem AT > physical_program_mem - .devcfg0 : { *(.devcfg0) } > config0 AT > physical_config0 - .devcfg1 : { *(.devcfg1) } > config1 AT > physical_config1 - .devcfg2 : { *(.devcfg2) } > config2 AT > physical_config2 - /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } -} diff -r c1b168829e0b -r d878ce48d7d4 payload.ld --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/payload.ld Wed Oct 17 17:56:15 2018 +0200 @@ -0,0 +1,43 @@ +OUTPUT_ARCH(mips) +ENTRY(_start) + +/* See... + * FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX170/270 DEVICES (64 KB RAM, 256 KB FLASH) + * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet + */ + +MEMORY +{ + kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x10000 + kseg0_boot_mem (rx) : ORIGIN = 0x9FC00000, LENGTH = 0xBF0 + kseg0_program_mem (rx) : ORIGIN = 0x9D000000, LENGTH = 0x40000 + physical_boot_mem (rx) : ORIGIN = 0x1FC00000, LENGTH = 0xBF0 + physical_program_mem (rx) : ORIGIN = 0x1D000000, LENGTH = 0x40000 + sfrs : ORIGIN = 0xBF800000, LENGTH = 0x100000 + configsfrs : ORIGIN = 0xBFC00BF0, LENGTH = 0x10 + config3 : ORIGIN = 0xBFC00BF0, LENGTH = 0x4 + config2 : ORIGIN = 0xBFC00BF4, LENGTH = 0x4 + config1 : ORIGIN = 0xBFC00BF8, LENGTH = 0x4 + config0 : ORIGIN = 0xBFC00BFC, LENGTH = 0x4 + physical_config3 : ORIGIN = 0x3FC00BF0, LENGTH = 0x4 + physical_config2 : ORIGIN = 0x3FC00BF4, LENGTH = 0x4 + physical_config1 : ORIGIN = 0x3FC00BF8, LENGTH = 0x4 + physical_config0 : ORIGIN = 0x3FC00BFC, LENGTH = 0x4 +} + +SECTIONS +{ + .boot : { *(.boot*) } > kseg0_boot_mem AT > physical_boot_mem + .vectors : { *(.vectors*) } > kseg0_program_mem AT > physical_program_mem + .text : { *(.text*) } > kseg0_program_mem AT > physical_program_mem + .bss : { *(.bss*) } > kseg1_data_mem + .rodata : { *(.rodata*) } > kseg0_program_mem AT > physical_program_mem + .got : { + _gp = ALIGN(16); + *(.got*) + } > kseg0_program_mem AT > physical_program_mem + .devcfg0 : { *(.devcfg0) } > config0 AT > physical_config0 + .devcfg1 : { *(.devcfg1) } > config1 AT > physical_config1 + .devcfg2 : { *(.devcfg2) } > config2 AT > physical_config2 + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } +} diff -r c1b168829e0b -r d878ce48d7d4 start.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/start.S Wed Oct 17 17:56:15 2018 +0200 @@ -0,0 +1,98 @@ +/* + * PIC32 microcontroller initialisation code. + * + * Copyright (C) 2017, 2018 Paul Boddie + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "mips.h" +#include "pic32.h" + +/* Disable JTAG functionality on pins. */ + +.section .devcfg0, "a" +.word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ + +/* +Set the oscillator to be the FRC oscillator with PLL, with peripheral clock +divided by 2, and FRCDIV+PLL selected. + +The watchdog timer (FWDTEN) is also disabled. + +The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with +RPB4. +*/ + +.section .devcfg1, "a" +.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1; + DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ + +/* +Set the FRC oscillator PLL function with an input division of 4, an output +division of 2, a multiplication of 24, yielding a multiplication of 3. + +The FRC is apparently at 16MHz and this produces a system clock of 48MHz. + +The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 +settings. +*/ + +.section .devcfg2, "a" +.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; + DEVCFG2<6:4> = FPLLMUL<2:0> = 111; + DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ + +/* The start routine is placed at the boot location. */ + +.section .boot, "a" + +.globl _start +.extern main + +_start: + /* Enable caching. */ + + mfc0 $v1, CP0_CONFIG + li $t8, ~CONFIG_K0 + and $v1, $v1, $t8 + ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT + mtc0 $v1, CP0_CONFIG + nop + + /* Get the RAM size. */ + + la $v1, BMXDRMSZ + lw $t0, 0($v1) + + /* Initialise the stack pointer. */ + + li $v1, KSEG0_BASE + addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */ + + /* Initialise the globals pointer. */ + + lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) + ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) + + /* + Jump to the main program. Since the boot code is separate from the + other code, the address cannot be obtained via the GOT. + ("relocation truncated to fit: R_MIPS_PC16 against `main'") + */ + + lui $t9, %hi(main) + ori $t9, $t9, %lo(main) + jr $t9 + nop