# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1540055970 -7200
# Node ID ec8c42b2c07b2af60f0d1db4eb95cbfc40049d59
# Parent  602a5cff7946716d4657ac582c09fcd2c5225f6b
Added more DMA channel configuration functions.

diff -r 602a5cff7946 -r ec8c42b2c07b init.c
--- a/init.c	Sat Oct 20 19:17:46 2018 +0200
+++ b/init.c	Sat Oct 20 19:19:30 2018 +0200
@@ -139,11 +139,12 @@
     REG(DMA_REG(channel, DCHxINT)) = 0;
 }
 
-/* Set the channel auto-enable mode. */
+/* Set the channel repeated enable mode, enabling it again when a block transfer
+   completes. The documentation describes this as auto-enable. */
 
-void dma_set_auto_enable(int channel, int auto_enable)
+void dma_set_auto_enable(int channel, int enable)
 {
-    (auto_enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4);
+    (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4);
 }
 
 /* Set the channel chaining mode. */
@@ -170,6 +171,25 @@
                                       ((enable ? 1 : 0) << 4);
 }
 
+/* Configure only the channel's initiation interrupt status. */
+
+void dma_set_interrupt_enable(int channel, int enable)
+{
+    if ((channel < DCHMIN) || (channel > DCHMAX))
+        return;
+
+    (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxECON), 1 << 4);
+}
+
+/* Permit the channel to register events while disabled or suspended. A
+   suspended channel is one that is enabled but where the DMA peripheral
+   has been suspended. */
+
+void dma_set_receive_events(int channel, int enable)
+{
+    (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 6);
+}
+
 /* Set a channel's transfer parameters. */
 
 void dma_set_transfer(int channel,
@@ -215,16 +235,28 @@
     SET_REG(DMAIEC, DMA_INT_FLAGS(channel, 1));
 }
 
+/* Enable or disable the channel. */
+
+void dma_set_enable(int channel, int enable)
+{
+    if ((channel < DCHMIN) || (channel > DCHMAX))
+        return;
+
+    (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 7);
+}
+
+/* Disable a DMA channel. */
+
+void dma_off(int channel)
+{
+    dma_set_enable(channel, 0);
+}
+
 /* Enable a DMA channel. */
 
 void dma_on(int channel)
 {
-    if ((channel < DCHMIN) || (channel > DCHMAX))
-        return;
-
-    /* Enable channel. */
-
-    SET_REG(DMA_REG(channel, DCHxCON), 1 << 7);
+    dma_set_enable(channel, 1);
 }
 
 
diff -r 602a5cff7946 -r ec8c42b2c07b init.h
--- a/init.h	Sat Oct 20 19:17:46 2018 +0200
+++ b/init.h	Sat Oct 20 19:19:30 2018 +0200
@@ -51,17 +51,25 @@
 
 void dma_init(int channel, uint8_t pri);
 
-void dma_set_auto_enable(int channel, int auto_enable);
+void dma_init_interrupt(int channel, uint8_t conditions,
+                        uint8_t pri, uint8_t sub);
+
+void dma_off(int channel);
+
+void dma_on(int channel);
+
+void dma_set_auto_enable(int channel, int enable);
 
 void dma_set_chaining(int channel, enum dma_chain chain);
 
-void dma_init_interrupt(int channel, uint8_t conditions,
-                        uint8_t pri, uint8_t sub);
-
-void dma_on(int channel);
+void dma_set_enable(int channel, int enable);
 
 void dma_set_interrupt(int channel, uint8_t int_num, int enable);
 
+void dma_set_interrupt_enable(int channel, int enable);
+
+void dma_set_receive_events(int channel, int enable);
+
 void dma_set_transfer(int channel,
                   uint32_t source_start_address, uint16_t source_size,
                   uint32_t destination_start_address, uint16_t destination_size,
@@ -77,14 +85,14 @@
 
 void oc_init(int unit, uint8_t mode, int timer);
 
+void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub);
+
+void oc_on(int unit);
+
 void oc_set_pulse(int unit, uint32_t start);
 
 void oc_set_pulse_end(int unit, uint32_t end);
 
-void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub);
-
-void oc_on(int unit);
-
 int OC_INT_FLAGS(int unit, uint8_t flags);
 
 uint32_t OC_IPC_PRI(int unit, uint8_t pri, uint8_t sub);