# HG changeset patch # User Paul Boddie # Date 1540055763 -7200 # Node ID fa0334bc8f8374e0ca7a5ea56e29060a644085cc # Parent 56f7040e64c6e6956ef0c55161f1f94104571e05 Reformatted using spaces. diff -r 56f7040e64c6 -r fa0334bc8f83 pic32.h --- a/pic32.h Fri Oct 19 18:55:36 2018 +0200 +++ b/pic32.h Sat Oct 20 19:16:03 2018 +0200 @@ -27,208 +27,214 @@ * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet */ -#define PMCON 0xBF807000 -#define PMMODE 0xBF807010 -#define PMADDR 0xBF807020 -#define PMDOUT 0xBF807030 -#define PMDIN 0xBF807040 -#define PMAEN 0xBF807050 -#define PMSTAT 0xBF807060 +#define PMCON 0xBF807000 +#define PMMODE 0xBF807010 +#define PMADDR 0xBF807020 +#define PMDOUT 0xBF807030 +#define PMDIN 0xBF807040 +#define PMAEN 0xBF807050 +#define PMSTAT 0xBF807060 -#define OSCCON 0xBF80F000 -#define REFOCON 0xBF80F020 -#define REFOTRIM 0xBF80F030 -#define CFGCON 0xBF80F200 -#define SYSKEY 0xBF80F230 +#define OSCCON 0xBF80F000 +#define REFOCON 0xBF80F020 +#define REFOTRIM 0xBF80F030 +#define CFGCON 0xBF80F200 +#define SYSKEY 0xBF80F230 -#define U1RXR 0xBF80FA50 +#define U1RXR 0xBF80FA50 -#define RPA0R 0xBF80FB00 -#define RPA1R 0xBF80FB04 -#define RPA2R 0xBF80FB08 -#define RPA3R 0xBF80FB0C -#define RPA4R 0xBF80FB10 -#define RPB0R 0xBF80FB2C -#define RPB1R 0xBF80FB30 -#define RPB2R 0xBF80FB34 -#define RPB3R 0xBF80FB38 -#define RPB4R 0xBF80FB3C -#define RPB5R 0xBF80FB40 -#define RPB10R 0xBF80FB54 -#define RPB15R 0xBF80FB68 +#define RPA0R 0xBF80FB00 +#define RPA1R 0xBF80FB04 +#define RPA2R 0xBF80FB08 +#define RPA3R 0xBF80FB0C +#define RPA4R 0xBF80FB10 +#define RPB0R 0xBF80FB2C +#define RPB1R 0xBF80FB30 +#define RPB2R 0xBF80FB34 +#define RPB3R 0xBF80FB38 +#define RPB4R 0xBF80FB3C +#define RPB5R 0xBF80FB40 +#define RPB10R 0xBF80FB54 +#define RPB15R 0xBF80FB68 -#define INTCON 0xBF881000 -#define IFS0 0xBF881030 -#define IFS1 0xBF881040 -#define IEC0 0xBF881060 -#define IEC1 0xBF881070 -#define IPC1 0xBF8810A0 -#define IPC2 0xBF8810B0 -#define IPC3 0xBF8810C0 -#define IPC4 0xBF8810D0 -#define IPC5 0xBF8810E0 -#define IPC6 0xBF8810F0 -#define IPC7 0xBF881100 -#define IPC8 0xBF881110 -#define IPC9 0xBF881120 -#define IPC10 0xBF881130 +#define INTCON 0xBF881000 +#define IFS0 0xBF881030 +#define IFS1 0xBF881040 +#define IEC0 0xBF881060 +#define IEC1 0xBF881070 +#define IPC1 0xBF8810A0 +#define IPC2 0xBF8810B0 +#define IPC3 0xBF8810C0 +#define IPC4 0xBF8810D0 +#define IPC5 0xBF8810E0 +#define IPC6 0xBF8810F0 +#define IPC7 0xBF881100 +#define IPC8 0xBF881110 +#define IPC9 0xBF881120 +#define IPC10 0xBF881130 -#define BMXCON 0xBF882000 -#define BMXDKPBA 0xBF882010 -#define BMXDUDBA 0xBF882020 -#define BMXDUPBA 0xBF882030 -#define BMXDRMSZ 0xBF882040 +#define BMXCON 0xBF882000 +#define BMXDKPBA 0xBF882010 +#define BMXDUDBA 0xBF882020 +#define BMXDUPBA 0xBF882030 +#define BMXDRMSZ 0xBF882040 -#define ANSELA 0xBF886000 -#define TRISA 0xBF886010 -#define PORTA 0xBF886020 -#define LATA 0xBF886030 -#define ODCA 0xBF886040 -#define ANSELB 0xBF886100 -#define TRISB 0xBF886110 -#define PORTB 0xBF886120 -#define LATB 0xBF886130 -#define ODCB 0xBF886140 +#define ANSELA 0xBF886000 +#define TRISA 0xBF886010 +#define PORTA 0xBF886020 +#define LATA 0xBF886030 +#define ODCA 0xBF886040 +#define ANSELB 0xBF886100 +#define TRISB 0xBF886110 +#define PORTB 0xBF886120 +#define LATB 0xBF886130 +#define ODCB 0xBF886140 /* DMA conveniences. */ -#define DMACON 0xBF883000 -#define DCH0CON 0xBF883060 -#define DCH1CON 0xBF883120 -#define DCH2CON 0xBF8831E0 -#define DCH3CON 0xBF8832A0 +#define DMACON 0xBF883000 +#define DCH0CON 0xBF883060 +#define DCH1CON 0xBF883120 +#define DCH2CON 0xBF8831E0 +#define DCH3CON 0xBF8832A0 -#define DCHMIN 0 -#define DCHMAX 3 -#define DCHBASE DCH0CON -#define DCHSTEP (DCH1CON - DCH0CON) +#define DCHMIN 0 +#define DCHMAX 3 +#define DCHBASE DCH0CON +#define DCHSTEP (DCH1CON - DCH0CON) -#define DCHxCON 0x00 -#define DCHxECON 0x10 -#define DCHxINT 0x20 -#define DCHxSSA 0x30 -#define DCHxDSA 0x40 -#define DCHxSSIZ 0x50 -#define DCHxDSIZ 0x60 -#define DCHxSPTR 0x70 -#define DCHxDPTR 0x80 -#define DCHxCSIZ 0x90 -#define DCHxCPTR 0xA0 -#define DCHxDAT 0xB0 +#define DCHxCON 0x00 +#define DCHxECON 0x10 +#define DCHxINT 0x20 +#define DCHxSSA 0x30 +#define DCHxDSA 0x40 +#define DCHxSSIZ 0x50 +#define DCHxDSIZ 0x60 +#define DCHxSPTR 0x70 +#define DCHxDPTR 0x80 +#define DCHxCSIZ 0x90 +#define DCHxCPTR 0xA0 +#define DCHxDAT 0xB0 -#define DMAIEC IEC1 -#define DMAIFS IFS1 -#define DMAINTBASE 28 +#define DMAIEC IEC1 + +#define DCHxIE 1 + +#define DMAIFS IFS1 -#define DMAIPC IPC10 -#define DCHIPCBASE 0 -#define DCHIPCSTEP 8 +#define DCHxIF 1 + +#define DMAINTBASE 28 + +#define DMAIPC IPC10 +#define DCHIPCBASE 0 +#define DCHIPCSTEP 8 /* Output compare conveniences. */ -#define OC1CON 0xBF803000 -#define OC2CON 0xBF803200 -#define OC3CON 0xBF803400 -#define OC4CON 0xBF803600 -#define OC5CON 0xBF803800 +#define OC1CON 0xBF803000 +#define OC2CON 0xBF803200 +#define OC3CON 0xBF803400 +#define OC4CON 0xBF803600 +#define OC5CON 0xBF803800 -#define OCMIN 1 -#define OCMAX 5 -#define OCBASE OC1CON -#define OCSTEP (OC2CON - OC1CON) +#define OCMIN 1 +#define OCMAX 5 +#define OCBASE OC1CON +#define OCSTEP (OC2CON - OC1CON) -#define OCxCON 0x00 -#define OCxR 0x10 -#define OCxRS 0x20 +#define OCxCON 0x00 +#define OCxR 0x10 +#define OCxRS 0x20 -#define OCIEC IEC0 +#define OCIEC IEC0 -#define OCxIE 1 +#define OCxIE 1 -#define OCIFS IFS0 +#define OCIFS IFS0 -#define OCxIF 1 +#define OCxIF 1 -#define OCINTBASE 7 -#define OCINTSTEP 5 +#define OCINTBASE 7 +#define OCINTSTEP 5 -#define OC1IPC IPC1 -#define OC2IPC IPC2 -#define OC3IPC IPC3 -#define OC4IPC IPC4 -#define OC5IPC IPC5 -#define OCIPCBASE 16 +#define OC1IPC IPC1 +#define OC2IPC IPC2 +#define OC3IPC IPC3 +#define OC4IPC IPC4 +#define OC5IPC IPC5 +#define OCIPCBASE 16 /* Timer conveniences. */ -#define T1CON 0xBF800600 -#define T2CON 0xBF800800 -#define T3CON 0xBF800A00 -#define T4CON 0xBF800C00 -#define T5CON 0xBF800E00 +#define T1CON 0xBF800600 +#define T2CON 0xBF800800 +#define T3CON 0xBF800A00 +#define T4CON 0xBF800C00 +#define T5CON 0xBF800E00 -#define TIMERMIN 1 -#define TIMERMAX 5 -#define TIMERBASE T1CON -#define TIMERSTEP (T2CON - T1CON) +#define TIMERMIN 1 +#define TIMERMAX 5 +#define TIMERBASE T1CON +#define TIMERSTEP (T2CON - T1CON) -#define TxCON 0x00 -#define TMRx 0x10 -#define PRx 0x20 +#define TxCON 0x00 +#define TMRx 0x10 +#define PRx 0x20 -#define TIMERIEC IEC0 +#define TIMERIEC IEC0 -#define TxIE 1 +#define TxIE 1 -#define TIMERIFS IEC0 +#define TIMERIFS IEC0 -#define TxIF 1 +#define TxIF 1 -#define TIMERINTBASE 4 -#define TIMERINTSTEP 5 +#define TIMERINTBASE 4 +#define TIMERINTSTEP 5 -#define TIMER1IPC IPC1 -#define TIMER2IPC IPC2 -#define TIMER3IPC IPC3 -#define TIMER4IPC IPC4 -#define TIMER5IPC IPC5 -#define TIMERIPCBASE 0 +#define TIMER1IPC IPC1 +#define TIMER2IPC IPC2 +#define TIMER3IPC IPC3 +#define TIMER4IPC IPC4 +#define TIMER5IPC IPC5 +#define TIMERIPCBASE 0 /* UART conveniences. */ -#define U1MODE 0xBF806000 -#define U2MODE 0xBF806200 +#define U1MODE 0xBF806000 +#define U2MODE 0xBF806200 -#define UARTMIN 1 -#define UARTMAX 2 -#define UARTBASE U1MODE -#define UARTSTEP (U2MODE - U1MODE) +#define UARTMIN 1 +#define UARTMAX 2 +#define UARTBASE U1MODE +#define UARTSTEP (U2MODE - U1MODE) -#define UxMODE 0x00 -#define UxSTA 0x10 -#define UxTXREG 0x20 -#define UxRXREG 0x30 -#define UxBRG 0x40 +#define UxMODE 0x00 +#define UxSTA 0x10 +#define UxTXREG 0x20 +#define UxRXREG 0x30 +#define UxBRG 0x40 -#define UARTIEC IEC1 +#define UARTIEC IEC1 -#define UxEIE 1 -#define UxRIE 2 -#define UxTIE 4 +#define UxEIE 1 +#define UxRIE 2 +#define UxTIE 4 -#define UARTIFS IFS1 +#define UARTIFS IFS1 -#define UxEIF 1 -#define UxRIF 2 -#define UxTIF 4 +#define UxEIF 1 +#define UxRIF 2 +#define UxTIF 4 -#define UARTINTBASE 7 -#define UARTINTSTEP 14 +#define UARTINTBASE 7 +#define UARTINTSTEP 14 -#define UART1IPC IPC8 -#define UART1IPCBASE 0 -#define UART2IPC IPC9 -#define UART2IPCBASE 8 +#define UART1IPC IPC8 +#define UART1IPCBASE 0 +#define UART2IPC IPC9 +#define UART2IPCBASE 8 /* Interrupt numbers. * See... @@ -236,24 +242,24 @@ * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet */ -#define DMA0 60 -#define DMA1 61 -#define DMA2 62 -#define DMA3 63 -#define OC1 7 -#define OC2 12 -#define OC3 17 -#define OC4 22 -#define OC5 27 -#define T1 4 -#define T2 9 -#define T3 14 -#define T4 19 -#define T5 24 -#define U1RX 40 -#define U1TX 41 -#define U2RX 54 -#define U2TX 55 +#define DMA0 60 +#define DMA1 61 +#define DMA2 62 +#define DMA3 63 +#define OC1 7 +#define OC2 12 +#define OC3 17 +#define OC4 22 +#define OC5 27 +#define T1 4 +#define T2 9 +#define T3 14 +#define T4 19 +#define T5 24 +#define U1RX 40 +#define U1TX 41 +#define U2RX 54 +#define U2TX 55 /* Address modifiers. * See... @@ -261,8 +267,8 @@ * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet */ -#define CLR 0x4 -#define SET 0x8 -#define INV 0xC +#define CLR 0x4 +#define SET 0x8 +#define INV 0xC #endif /* __PIC32_H__ */