# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1539962036 -7200
# Node ID ffb0fa616eaf80857df9ff9b3b70bb9bec813847
# Parent  21bd14ed98724f9988e1048ecdb2543fca3d4058
It appears unnecessary to re-enable the first DMA channel. Thus, handling a DMA
completion condition on the second channel for such purposes is unnecessary.

diff -r 21bd14ed9872 -r ffb0fa616eaf main.c
--- a/main.c	Fri Oct 19 16:42:18 2018 +0200
+++ b/main.c	Fri Oct 19 17:13:56 2018 +0200
@@ -85,7 +85,6 @@
     dma_set_transfer(1, PHYSICAL((uint32_t) message2), sizeof(message2) - 1,
                         HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
                         1);
-    dma_init_interrupt(1, 0b00001000, 7, 3);
 
     /* Configure a timer for the first DMA channel whose interrupt condition
        drives the transfer but is not handled (having a lower priority than the
@@ -158,19 +157,6 @@
                 dma_on(0);
         }
     }
-
-    /* Check for a DMA interrupt condition (CHBCIF). */
-
-    ifs = REG(DMAIFS) & DMA_INT_FLAGS(1, 1);
-
-    if (ifs)
-    {
-        INV_REG(PORTA, 1 << 2);
-        CLR_REG(DMA_REG(0, DCHxINT), 0b11111111);
-        CLR_REG(DMAIFS, ifs);
-
-        dma_on(0);
-    }
 }