CommonPIC32

Changeset

148:d112c32b7417
2019-05-04 Paul Boddie raw files shortlog changelog graph Moved VGA example documentation into the wiki documentation.
docs/wiki/Examples--vga (file) docs/wiki/Examples--vga-cpu (file) docs/wiki/Examples--vga-dual (file) docs/wiki/Examples--vga-pmp (file) docs/wiki/Examples--vga-timer (file) docs/wiki/VGA_Output_Examples (file) examples/vga-cpu/README.txt examples/vga-dual/README.txt examples/vga-pmp/README.txt examples/vga-timer/README.txt examples/vga/README.txt
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/docs/wiki/Examples--vga	Sat May 04 22:54:18 2019 +0200
     1.3 @@ -0,0 +1,100 @@
     1.4 += VGA Output Example =
     1.5 +
     1.6 +This example demonstrates the generation of an analogue VGA signal from a
     1.7 +PIC32 microcontroller using general output pins. It follows on from the work
     1.8 +done in the VGAPIC32 project. The result is not entirely satisfactory:
     1.9 +
    1.10 + * Every fourth pixel is wider than the others, this apparently being an
    1.11 +   artefact of the DMA transfer mechanism.
    1.12 +
    1.13 +It might be possible to introduce some kind of delay and even out the pixel
    1.14 +widths, but this has not been investigated with hardware. However, unlike the
    1.15 +[[../vga-pmp|vga-pmp]] example, there is no accompanying signal to potentially
    1.16 +orchestrate the staging of individual pixels at a slightly delayed rate.
    1.17 +
    1.18 +Attempts to introduce other remedies to the wide pixel problem have been made
    1.19 +with the [[../vga-dual|vga-dual]] and [[../vga-timer|vga-timer]] examples.
    1.20 +
    1.21 +== Hardware Details ==
    1.22 +
    1.23 +The pin usage of this solution is documented below.
    1.24 +
    1.25 +=== PIC32MX270F256B-50I/SP Pin Assignments ===
    1.26 +
    1.27 +{{{
    1.28 +MCLR#          1  \/  28
    1.29 +HSYNC/OC1/RA0  2      27
    1.30 +VSYNC/OC2/RA1  3      26 RB15/U1TX
    1.31 +       D0/RB0  4      25 RB14
    1.32 +       D1/RB1  5      24 RB13/U1RX
    1.33 +       D2/RB2  6      23
    1.34 +       D3/RB3  7      22 RB11/PGEC2
    1.35 +               8      21 RB10/PGEC3
    1.36 +          RA2  9      20
    1.37 +          RA3 10      19
    1.38 +       D4/RB4 11      18 RB9
    1.39 +              12      17 RB8
    1.40 +              13      16 RB7/D7
    1.41 +       D5/RB5 14      15
    1.42 +}}}
    1.43 +
    1.44 +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
    1.45 +unlike the MX170 variant).
    1.46 +
    1.47 +=== UART Connections ===
    1.48 +
    1.49 +UART1 is exposed by the RB13 and RB15 pins.
    1.50 +
    1.51 +=== Data Signal Routing ===
    1.52 +
    1.53 +For one bit of intensity, two bits per colour channel:
    1.54 +
    1.55 +{{{
    1.56 +D7 -> 2200R -> I
    1.57 +
    1.58 +I -> diode -> R
    1.59 +I -> diode -> G
    1.60 +I -> diode -> B
    1.61 +
    1.62 +D6 (not connected)
    1.63 +
    1.64 +D5 -> 470R -> R
    1.65 +D4 -> 1000R -> R
    1.66 +D3 -> 470R -> G
    1.67 +D2 -> 1000R -> G
    1.68 +D1 -> 470R -> B
    1.69 +D0 -> 1000R -> B
    1.70 +
    1.71 +HSYNC -> HS
    1.72 +VSYNC -> VS
    1.73 +}}}
    1.74 +
    1.75 +=== Output Socket Pinout ===
    1.76 +
    1.77 +{{{
    1.78 +5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
    1.79 +
    1.80 +    10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
    1.81 +
    1.82 +15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
    1.83 +}}}
    1.84 +
    1.85 +=== Output Cable Pinout ===
    1.86 +
    1.87 +{{{
    1.88 +    1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
    1.89 +
    1.90 +6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
    1.91 +
    1.92 +    11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
    1.93 +}}}
    1.94 +
    1.95 +== References ==
    1.96 +
    1.97 +https://en.wikipedia.org/wiki/VGA_connector
    1.98 +
    1.99 +http://papilio.cc/index.php?n=Papilio.VGAWing
   1.100 +
   1.101 +http://lucidscience.com/pro-vga%20video%20generator-2.aspx
   1.102 +
   1.103 +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/docs/wiki/Examples--vga-cpu	Sat May 04 22:54:18 2019 +0200
     2.3 @@ -0,0 +1,120 @@
     2.4 += VGA Output Example (CPU-Driven Transfers) =
     2.5 +
     2.6 +This example demonstrates the generation of an analogue VGA signal from a
     2.7 +PIC32 microcontroller using general output pins. Instead of using DMA, which
     2.8 +was the focus of the VGAPIC32 project and is a central feature of the
     2.9 +approaches demonstrated by other examples ([[../vga|vga]],
    2.10 +[[../vga-dual|vga-dual]], [[../vga-pmp|vga-pmp]], [[../vga-timer|vga-timer]]),
    2.11 +here the CPU is given the task of transferring pixel data to the output pins.
    2.12 +
    2.13 +Instead of a timer interrupt condition initiating DMA transfers, the interrupt
    2.14 +is handled and a routine invoked to issue the necessary load and store
    2.15 +instructions in a loop. Otherwise, the use of the timer to generate sync
    2.16 +pulses is as in the other examples and the general display state machine is
    2.17 +largely the same.
    2.18 +
    2.19 +The resulting picture is more pleasing than that produced by most of the DMA
    2.20 +examples in that the display pixels have consistent widths. Moreover, the
    2.21 +pixels are also narrower than those produced by the [[../vga-timer|vga-timer]]
    2.22 +example. It is possible to generate a display with something approaching 200
    2.23 +pixels horizontally, with 160 pixels being demonstrated.
    2.24 +
    2.25 +However, the CPU now spends a lot of time occupied in an interrupt request
    2.26 +handler generating pixels. This seems less elegant than using DMA, but in
    2.27 +practice, the CPU may be effectively stalled where DMA transfers dominate
    2.28 +access to the RAM. Even if, in such situations, the CPU may be able to access
    2.29 +flash memory to load instructions, programs typically end up accessing RAM at
    2.30 +some point, and this would effectively limit the concurrency within the
    2.31 +system. Certainly, this approach seems to result in slower programs than the
    2.32 +plain DMA-based approach.
    2.33 +
    2.34 +One potential advantage of this approach is in the flexibility that might be
    2.35 +achieved by manipulating the pixel data. With DMA, data is transferred as it
    2.36 +is found and is generally not transformed (although there are some features in
    2.37 +the PIC32 DMA controller for certain kinds of data), whereas we might envisage
    2.38 +supporting display modes employing fewer bits for the output signal, reducing
    2.39 +the number of colours but also the size of the framebuffer.
    2.40 +
    2.41 +== Hardware Details ==
    2.42 +
    2.43 +The pin usage of this solution is documented below.
    2.44 +
    2.45 +=== PIC32MX270F256B-50I/SP Pin Assignments ===
    2.46 +
    2.47 +{{{
    2.48 +MCLR#          1  \/  28
    2.49 +HSYNC/OC1/RA0  2      27
    2.50 +VSYNC/OC2/RA1  3      26 RB15/U1TX
    2.51 +       D0/RB0  4      25 RB14
    2.52 +       D1/RB1  5      24 RB13/U1RX
    2.53 +       D2/RB2  6      23
    2.54 +       D3/RB3  7      22 RB11/PGEC2
    2.55 +               8      21 RB10/PGEC3
    2.56 +          RA2  9      20
    2.57 +          RA3 10      19
    2.58 +       D4/RB4 11      18 RB9
    2.59 +              12      17 RB8
    2.60 +              13      16 RB7/D7
    2.61 +       D5/RB5 14      15
    2.62 +}}}
    2.63 +
    2.64 +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
    2.65 +unlike the MX170 variant).
    2.66 +
    2.67 +=== UART Connections ===
    2.68 +
    2.69 +UART1 is exposed by the RB13 and RB15 pins.
    2.70 +
    2.71 +=== Data Signal Routing ===
    2.72 +
    2.73 +For one bit of intensity, two bits per colour channel:
    2.74 +
    2.75 +{{{
    2.76 +D7 -> 2200R -> I
    2.77 +
    2.78 +I -> diode -> R
    2.79 +I -> diode -> G
    2.80 +I -> diode -> B
    2.81 +
    2.82 +D6 (not connected)
    2.83 +
    2.84 +D5 -> 470R -> R
    2.85 +D4 -> 1000R -> R
    2.86 +D3 -> 470R -> G
    2.87 +D2 -> 1000R -> G
    2.88 +D1 -> 470R -> B
    2.89 +D0 -> 1000R -> B
    2.90 +
    2.91 +HSYNC -> HS
    2.92 +VSYNC -> VS
    2.93 +}}}
    2.94 +
    2.95 +=== Output Socket Pinout ===
    2.96 +
    2.97 +{{{
    2.98 +5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
    2.99 +
   2.100 +    10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
   2.101 +
   2.102 +15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
   2.103 +}}}
   2.104 +
   2.105 +=== Output Cable Pinout ===
   2.106 +
   2.107 +{{{
   2.108 +    1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
   2.109 +
   2.110 +6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
   2.111 +
   2.112 +    11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
   2.113 +}}}
   2.114 +
   2.115 +== References ==
   2.116 +
   2.117 +https://en.wikipedia.org/wiki/VGA_connector
   2.118 +
   2.119 +http://papilio.cc/index.php?n=Papilio.VGAWing
   2.120 +
   2.121 +http://lucidscience.com/pro-vga%20video%20generator-2.aspx
   2.122 +
   2.123 +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/docs/wiki/Examples--vga-dual	Sat May 04 22:54:18 2019 +0200
     3.3 @@ -0,0 +1,109 @@
     3.4 += VGA Output Example (Dual-Channel DMA Transfers) =
     3.5 +
     3.6 +This example demonstrates the generation of an analogue VGA signal from a
     3.7 +PIC32 microcontroller using general output pins. It follows on from the work
     3.8 +done in the VGAPIC32 project. The result is not entirely satisfactory:
     3.9 +
    3.10 + * Every fourth pixel is wider than the others, this apparently being an
    3.11 +   artefact of the DMA transfer mechanism.
    3.12 +
    3.13 +It might be possible to introduce some kind of delay and even out the pixel
    3.14 +widths, but this has not been investigated with hardware. However, unlike the
    3.15 +[[../vga-pmp|vga-pmp]] example, there is no accompanying signal to potentially
    3.16 +orchestrate the staging of individual pixels at a slightly delayed rate.
    3.17 +Potentially, the peripheral clock signal might be generated and processed to
    3.18 +make such a signal.
    3.19 +
    3.20 +Unlike the [[../vga|vga]] example, this example employs two DMA channels for
    3.21 +pixel data which are interleaved to investigate a potential remedy for the
    3.22 +wide pixel effect. Unfortunately, despite each channel contributing every
    3.23 +other word (or group of four pixels), the effect persists. However, the
    3.24 +picture is perhaps more stable than in the [[../vga|vga]] example.
    3.25 +
    3.26 +One significant problem with this example is that scrolling causes the DMA
    3.27 +channels to become ordered incorrectly. This does not affect the
    3.28 +[[../vga-timer|vga-timer]] example which also employs two DMA channels.
    3.29 +
    3.30 +== Hardware Details ==
    3.31 +
    3.32 +The pin usage of this solution is documented below.
    3.33 +
    3.34 +=== PIC32MX270F256B-50I/SP Pin Assignments ===
    3.35 +
    3.36 +{{{
    3.37 +MCLR#          1  \/  28
    3.38 +HSYNC/OC1/RA0  2      27
    3.39 +VSYNC/OC2/RA1  3      26 RB15/U1TX
    3.40 +       D0/RB0  4      25 RB14
    3.41 +       D1/RB1  5      24 RB13/U1RX
    3.42 +       D2/RB2  6      23
    3.43 +       D3/RB3  7      22 RB11/PGEC2
    3.44 +               8      21 RB10/PGEC3
    3.45 +          RA2  9      20
    3.46 +          RA3 10      19
    3.47 +       D4/RB4 11      18 RB9
    3.48 +              12      17 RB8
    3.49 +              13      16 RB7/D7
    3.50 +       D5/RB5 14      15
    3.51 +}}}
    3.52 +
    3.53 +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
    3.54 +unlike the MX170 variant).
    3.55 +
    3.56 +=== UART Connections ===
    3.57 +
    3.58 +UART1 is exposed by the RB13 and RB15 pins.
    3.59 +
    3.60 +=== Data Signal Routing ===
    3.61 +
    3.62 +For one bit of intensity, two bits per colour channel:
    3.63 +
    3.64 +{{{
    3.65 +D7 -> 2200R -> I
    3.66 +
    3.67 +I -> diode -> R
    3.68 +I -> diode -> G
    3.69 +I -> diode -> B
    3.70 +
    3.71 +D6 (not connected)
    3.72 +
    3.73 +D5 -> 470R -> R
    3.74 +D4 -> 1000R -> R
    3.75 +D3 -> 470R -> G
    3.76 +D2 -> 1000R -> G
    3.77 +D1 -> 470R -> B
    3.78 +D0 -> 1000R -> B
    3.79 +
    3.80 +HSYNC -> HS
    3.81 +VSYNC -> VS
    3.82 +}}}
    3.83 +
    3.84 +=== Output Socket Pinout ===
    3.85 +
    3.86 +{{{
    3.87 +5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
    3.88 +
    3.89 +    10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
    3.90 +
    3.91 +15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
    3.92 +}}}
    3.93 +
    3.94 +=== Output Cable Pinout ===
    3.95 +
    3.96 +{{{
    3.97 +    1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
    3.98 +
    3.99 +6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
   3.100 +
   3.101 +    11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
   3.102 +}}}
   3.103 +
   3.104 +== References ==
   3.105 +
   3.106 +https://en.wikipedia.org/wiki/VGA_connector
   3.107 +
   3.108 +http://papilio.cc/index.php?n=Papilio.VGAWing
   3.109 +
   3.110 +http://lucidscience.com/pro-vga%20video%20generator-2.aspx
   3.111 +
   3.112 +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/docs/wiki/Examples--vga-pmp	Sat May 04 22:54:18 2019 +0200
     4.3 @@ -0,0 +1,113 @@
     4.4 += VGA Output Example (Parallel Mode Transfers) =
     4.5 +
     4.6 +This example demonstrates the generation of an analogue VGA signal from a
     4.7 +PIC32 microcontroller using the parallel mode (parallel master port, PMP)
     4.8 +peripheral. The result is not entirely satisfactory:
     4.9 +
    4.10 + * Pixels are very narrow unless buffered using a flip-flop driven by the
    4.11 +   peripheral, this being a characteristic of the way the peripheral works, it
    4.12 +   normally being used to drive memory and display controllers.
    4.13 +
    4.14 + * Introducing a flip-flop means that the final pixel from the pixel data
    4.15 +   remains asserted and must be reset using a second DMA channel.
    4.16 +
    4.17 + * Every fourth pixel is wider than the others, this apparently being an
    4.18 +   artefact of the DMA transfer mechanism.
    4.19 +
    4.20 +It might be possible introduce some kind of delay to the write strobe (PMWR)
    4.21 +and even out the pixel widths, but this has not been investigated.
    4.22 +
    4.23 +It appears to be the case that the system and peripheral clock frequencies
    4.24 +need to be matched. In this example, a frequency of 48MHz has been chosen.
    4.25 +
    4.26 +== Hardware Details ==
    4.27 +
    4.28 +The pin usage of this solution is documented below.
    4.29 +
    4.30 +=== PIC32MX270F256B-50I/SP Pin Assignments ===
    4.31 +
    4.32 +{{{
    4.33 +MCLR#          1  \/  28
    4.34 +  D7/PMD7/RA0  2      27
    4.35 +  D6/PMD6/RA1  3      26 RB15/U1TX
    4.36 +  D0/PMD0/RB0  4      25 RB14
    4.37 +  D1/PMD1/RB1  5      24 RB13/(PMRD)/U1RX
    4.38 +  D2/PMD2/RB2  6      23
    4.39 +     PMWR/RB3  7      22 RB11/PGEC2
    4.40 +               8      21 RB10/PGEC3
    4.41 +          RA2  9      20
    4.42 +   (PMA0)/RA3 10      19
    4.43 +HSYNC/OC1/RB4 11      18 RB9/PMD3/D3
    4.44 +              12      17 RB8/PMD4/D4
    4.45 +              13      16 RB7/PMD5/D5
    4.46 +VSYNC/OC2/RB5 14      15
    4.47 +}}}
    4.48 +
    4.49 +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
    4.50 +unlike the MX170 variant).
    4.51 +
    4.52 +=== UART Connections ===
    4.53 +
    4.54 +UART1 is exposed by the RB13 and RB15 pins.
    4.55 +
    4.56 +=== Data Signal Routing ===
    4.57 +
    4.58 +A flip-flop is used to buffer the outputs:
    4.59 +
    4.60 +{{{
    4.61 +Dn   -> 74HC273:Dn
    4.62 +        74HC273:Qn -> Qn
    4.63 +VCC  -> 74HC273:MR#
    4.64 +PMWR -> 74HC273:CP
    4.65 +}}}
    4.66 +
    4.67 +For two bits of intensity, two bits per colour channel:
    4.68 +
    4.69 +{{{
    4.70 +Q7 -> 2200R -> I
    4.71 +Q6 -> 4700R -> I
    4.72 +
    4.73 +I -> diode -> R
    4.74 +I -> diode -> G
    4.75 +I -> diode -> B
    4.76 +
    4.77 +Q5 -> 470R -> R
    4.78 +Q4 -> 1000R -> R
    4.79 +Q3 -> 470R -> G
    4.80 +Q2 -> 1000R -> G
    4.81 +Q1 -> 470R -> B
    4.82 +Q0 -> 1000R -> B
    4.83 +
    4.84 +HSYNC -> HS
    4.85 +VSYNC -> VS
    4.86 +}}}
    4.87 +
    4.88 +=== Output Socket Pinout ===
    4.89 +
    4.90 +{{{
    4.91 +5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
    4.92 +
    4.93 +    10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
    4.94 +
    4.95 +15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
    4.96 +}}}
    4.97 +
    4.98 +=== Output Cable Pinout ===
    4.99 +
   4.100 +{{{
   4.101 +    1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
   4.102 +
   4.103 +6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
   4.104 +
   4.105 +    11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
   4.106 +}}}
   4.107 +
   4.108 +== References ==
   4.109 +
   4.110 +https://en.wikipedia.org/wiki/VGA_connector
   4.111 +
   4.112 +http://papilio.cc/index.php?n=Papilio.VGAWing
   4.113 +
   4.114 +http://lucidscience.com/pro-vga%20video%20generator-2.aspx
   4.115 +
   4.116 +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/docs/wiki/Examples--vga-timer	Sat May 04 22:54:18 2019 +0200
     5.3 @@ -0,0 +1,147 @@
     5.4 += VGA Output Example (Timed DMA Transfers) =
     5.5 +
     5.6 +This example demonstrates the generation of an analogue VGA signal from a
     5.7 +PIC32 microcontroller using general output pins. Unlike the [[../vga|vga]] and
     5.8 +[[../vga-pmp|vga-pmp]] examples, it employs a regular interrupt condition to
     5.9 +schedule single-byte (single-pixel) DMA transfers instead of a single
    5.10 +whole-line transfer.
    5.11 +
    5.12 +The principal advantage of this method over the whole-line transfer method is
    5.13 +its production of pixels with consistent widths. The principal disadvantage is
    5.14 +the significant loss of horizontal resolution due to the latencies involved in
    5.15 +propagating interrupt conditions to the DMA controller and thereby initiating
    5.16 +each transfer.
    5.17 +
    5.18 +Employing a peripheral clock that has half the frequency of the system clock
    5.19 +should ensure the stability of the picture, since the lower frequency may make
    5.20 +transfers easier to schedule. The peripheral clock should provide a more
    5.21 +forgiving deadline for each transfer, permitting late transfers to complete on
    5.22 +time.
    5.23 +
    5.24 +Meanwhile, matching the system and peripheral clock frequencies appears to
    5.25 +leave the scheduling of transfers open to uncertainty, with transfers being
    5.26 +more readily delayed by other activity in the system, and with instability of
    5.27 +the picture being the result.
    5.28 +
    5.29 +Unlike the [[../vga|vga]] example, but in common with the
    5.30 +[[../vga-dual|vga-dual]] example, this example employs two DMA channels for
    5.31 +pixel data which are interleaved to investigate a potential remedy for the
    5.32 +wide pixel effect. This seems to preserve consistent pixel widths only with a
    5.33 +transfer cell size of 1: other cell sizes suffer from the wide pixel problem.
    5.34 +Despite not offering the greater throughput of larger cell sizes, merely
    5.35 +employing dual channels increases throughput for a cell size of 1, making the
    5.36 +technique worth using.
    5.37 +
    5.38 +In contrast to the [[../vga|vga]] and [[../vga-pmp|vga-pmp]] examples, a
    5.39 +special DMA channel is employed to initiate the pixel transfer process without
    5.40 +actually transferring any pixel data itself. The channel arrangement is as
    5.41 +follows:
    5.42 +
    5.43 +|| Transfer Initiator || DMA Channel || Transfer Activity ||
    5.44 +|| Timer2             || DMA1        || zerodata -> PORTB ||
    5.45 +|| Timer3             || DMA0        || linedata -> PORTB ||
    5.46 +|| Timer3             || DMA2        || linedata -> PORTB ||
    5.47 +|| Timer3             || DMA3        || zerodata -> PORTB ||
    5.48 +
    5.49 +The real purpose of this channel (DMA1) is to capture the Timer2 interrupt
    5.50 +condition and to enable the following channels (DMA0, DMA2) through channel
    5.51 +chaining.  Having been enabled, DMA0 and DMA2 are then able to conduct
    5.52 +transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or
    5.53 +"zero" channel to ensure that the pixel level is set to black at the end of
    5.54 +each display line.
    5.55 +
    5.56 +In principle, other initiating conditions can be used instead of Timer3, which
    5.57 +is configured to produce such conditions as frequently as possible: 
    5.58 +
    5.59 +  * A persistent interrupt condition can be employed instead. For example,
    5.60 +    configuring UART2 and setting the UART2 transfer interrupt, employing this
    5.61 +    interrupt condition for DMA0 and DMA2, produces the same effect.
    5.62 +
    5.63 +  * An external interrupt such as INT2 can be configured, and the peripheral
    5.64 +    clock can be routed through the CLKO pin and back into the microcontroller
    5.65 +    via an appropriate pin. With INT2 being employed as the interrupt
    5.66 +    condition for DMA0 and DMA2, the same effect is produced.
    5.67 +
    5.68 +== Hardware Details ==
    5.69 +
    5.70 +The pin usage of this solution is documented below.
    5.71 +
    5.72 +=== PIC32MX270F256B-50I/SP Pin Assignments ===
    5.73 +
    5.74 +{{{
    5.75 +MCLR#          1  \/  28
    5.76 +HSYNC/OC1/RA0  2      27
    5.77 +VSYNC/OC2/RA1  3      26 RB15/U1TX
    5.78 +       D0/RB0  4      25 RB14
    5.79 +       D1/RB1  5      24 RB13/U1RX
    5.80 +       D2/RB2  6      23
    5.81 +       D3/RB3  7      22 RB11/PGEC2
    5.82 +               8      21 RB10/PGEC3
    5.83 +          RA2  9      20
    5.84 +          RA3 10      19
    5.85 +       D4/RB4 11      18 RB9
    5.86 +              12      17 RB8
    5.87 +              13      16 RB7/D7
    5.88 +       D5/RB5 14      15
    5.89 +}}}
    5.90 +
    5.91 +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
    5.92 +unlike the MX170 variant).
    5.93 +
    5.94 +=== UART Connections ===
    5.95 +
    5.96 +UART1 is exposed by the RB13 and RB15 pins.
    5.97 +
    5.98 +=== Data Signal Routing ===
    5.99 +
   5.100 +For one bit of intensity, two bits per colour channel:
   5.101 +
   5.102 +{{{
   5.103 +D7 -> 2200R -> I
   5.104 +
   5.105 +I -> diode -> R
   5.106 +I -> diode -> G
   5.107 +I -> diode -> B
   5.108 +
   5.109 +D6 (not connected)
   5.110 +
   5.111 +D5 -> 470R -> R
   5.112 +D4 -> 1000R -> R
   5.113 +D3 -> 470R -> G
   5.114 +D2 -> 1000R -> G
   5.115 +D1 -> 470R -> B
   5.116 +D0 -> 1000R -> B
   5.117 +
   5.118 +HSYNC -> HS
   5.119 +VSYNC -> VS
   5.120 +}}}
   5.121 +
   5.122 +=== Output Socket Pinout ===
   5.123 +
   5.124 +{{{
   5.125 +5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
   5.126 +
   5.127 +    10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
   5.128 +
   5.129 +15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
   5.130 +}}}
   5.131 +
   5.132 +=== Output Cable Pinout ===
   5.133 +
   5.134 +{{{
   5.135 +    1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
   5.136 +
   5.137 +6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
   5.138 +
   5.139 +    11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
   5.140 +}}}
   5.141 +
   5.142 +== References ==
   5.143 +
   5.144 +https://en.wikipedia.org/wiki/VGA_connector
   5.145 +
   5.146 +http://papilio.cc/index.php?n=Papilio.VGAWing
   5.147 +
   5.148 +http://lucidscience.com/pro-vga%20video%20generator-2.aspx
   5.149 +
   5.150 +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
     6.1 --- a/docs/wiki/VGA_Output_Examples	Thu May 02 23:21:32 2019 +0200
     6.2 +++ b/docs/wiki/VGA_Output_Examples	Sat May 04 22:54:18 2019 +0200
     6.3 @@ -1,4 +1,12 @@
     6.4 -= VGA Output Example Comparison =
     6.5 += VGA Output Examples =
     6.6 +
     6.7 + * [[Examples/vga|vga]]
     6.8 + * [[Examples/vga-cpu|vga-cpu]]
     6.9 + * [[Examples/vga-dual|vga-dual]]
    6.10 + * [[Examples/vga-pmp|vga-pmp]]
    6.11 + * [[Examples/vga-timer|vga-timer]]
    6.12 +
    6.13 +== Comparison ==
    6.14  
    6.15  In investigating different techniques, the following observations have been
    6.16  made about the behaviour of the different VGA examples:
     7.1 --- a/examples/vga-cpu/README.txt	Thu May 02 23:21:32 2019 +0200
     7.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.3 @@ -1,119 +0,0 @@
     7.4 -Introduction
     7.5 -------------
     7.6 -
     7.7 -This example demonstrates the generation of an analogue VGA signal from a
     7.8 -PIC32 microcontroller using general output pins. Instead of using DMA, which
     7.9 -was the focus of the VGAPIC32 project and is a central feature of the
    7.10 -approaches demonstrated by other examples (vga, vga-dual, vga-pmp, vga-timer),
    7.11 -here the CPU is given the task of transferring pixel data to the output pins.
    7.12 -
    7.13 -Instead of a timer interrupt condition initiating DMA transfers, the interrupt
    7.14 -is handled and a routine invoked to issue the necessary load and store
    7.15 -instructions in a loop. Otherwise, the use of the timer to generate sync
    7.16 -pulses is as in the other examples and the general display state machine is
    7.17 -largely the same.
    7.18 -
    7.19 -The resulting picture is more pleasing than that produced by most of the DMA
    7.20 -examples in that the display pixels have consistent widths. Moreover, the
    7.21 -pixels are also narrower than those produced by the vga-timer example. It is
    7.22 -possible to generate a display with something approaching 200 pixels
    7.23 -horizontally, with 160 pixels being demonstrated.
    7.24 -
    7.25 -However, the CPU now spends a lot of time occupied in an interrupt request
    7.26 -handler generating pixels. This seems less elegant than using DMA, but in
    7.27 -practice, the CPU may be effectively stalled where DMA transfers dominate
    7.28 -access to the RAM. Even if, in such situations, the CPU may be able to access
    7.29 -flash memory to load instructions, programs typically end up accessing RAM at
    7.30 -some point, and this would effectively limit the concurrency within the
    7.31 -system. Certainly, this approach seems to result in slower programs than the
    7.32 -plain DMA-based approach.
    7.33 -
    7.34 -One potential advantage of this approach is in the flexibility that might be
    7.35 -achieved by manipulating the pixel data. With DMA, data is transferred as it
    7.36 -is found and is generally not transformed (although there are some features in
    7.37 -the PIC32 DMA controller for certain kinds of data), whereas we might envisage
    7.38 -supporting display modes employing fewer bits for the output signal, reducing
    7.39 -the number of colours but also the size of the framebuffer.
    7.40 -
    7.41 -Hardware Details
    7.42 -================
    7.43 -
    7.44 -The pin usage of this solution is documented below.
    7.45 -
    7.46 -PIC32MX270F256B-50I/SP Pin Assignments
    7.47 ---------------------------------------
    7.48 -
    7.49 -MCLR#          1  \/  28
    7.50 -HSYNC/OC1/RA0  2      27
    7.51 -VSYNC/OC2/RA1  3      26 RB15/U1TX
    7.52 -       D0/RB0  4      25 RB14
    7.53 -       D1/RB1  5      24 RB13/U1RX
    7.54 -       D2/RB2  6      23
    7.55 -       D3/RB3  7      22 RB11/PGEC2
    7.56 -               8      21 RB10/PGEC3
    7.57 -          RA2  9      20
    7.58 -          RA3 10      19
    7.59 -       D4/RB4 11      18 RB9
    7.60 -              12      17 RB8
    7.61 -              13      16 RB7/D7
    7.62 -       D5/RB5 14      15
    7.63 -
    7.64 -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
    7.65 -unlike the MX170 variant).
    7.66 -
    7.67 -UART Connections
    7.68 -----------------
    7.69 -
    7.70 -UART1 is exposed by the RB13 and RB15 pins.
    7.71 -
    7.72 -Data Signal Routing
    7.73 --------------------
    7.74 -
    7.75 -For one bit of intensity, two bits per colour channel:
    7.76 -
    7.77 -D7 -> 2200R -> I
    7.78 -
    7.79 -I -> diode -> R
    7.80 -I -> diode -> G
    7.81 -I -> diode -> B
    7.82 -
    7.83 -D6 (not connected)
    7.84 -
    7.85 -D5 -> 470R -> R
    7.86 -D4 -> 1000R -> R
    7.87 -D3 -> 470R -> G
    7.88 -D2 -> 1000R -> G
    7.89 -D1 -> 470R -> B
    7.90 -D0 -> 1000R -> B
    7.91 -
    7.92 -HSYNC -> HS
    7.93 -VSYNC -> VS
    7.94 -
    7.95 -Output Socket Pinout
    7.96 ---------------------
    7.97 -
    7.98 -  5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
    7.99 -
   7.100 -      10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
   7.101 -
   7.102 -  15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
   7.103 -
   7.104 -Output Cable Pinout
   7.105 --------------------
   7.106 -
   7.107 -      1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
   7.108 -
   7.109 -  6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
   7.110 -
   7.111 -      11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
   7.112 -
   7.113 -References
   7.114 -----------
   7.115 -
   7.116 -https://en.wikipedia.org/wiki/VGA_connector
   7.117 -
   7.118 -http://papilio.cc/index.php?n=Papilio.VGAWing
   7.119 -
   7.120 -http://lucidscience.com/pro-vga%20video%20generator-2.aspx
   7.121 -
   7.122 -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
     8.1 --- a/examples/vga-dual/README.txt	Thu May 02 23:21:32 2019 +0200
     8.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.3 @@ -1,109 +0,0 @@
     8.4 -Introduction
     8.5 -------------
     8.6 -
     8.7 -This example demonstrates the generation of an analogue VGA signal from a
     8.8 -PIC32 microcontroller using general output pins. It follows on from the work
     8.9 -done in the VGAPIC32 project. The result is not entirely satisfactory:
    8.10 -
    8.11 - * Every fourth pixel is wider than the others, this apparently being an
    8.12 -   artefact of the DMA transfer mechanism.
    8.13 -
    8.14 -It might be possible to introduce some kind of delay and even out the pixel
    8.15 -widths, but this has not been investigated with hardware. However, unlike the
    8.16 -vga-pmp example, there is no accompanying signal to potentially orchestrate
    8.17 -the staging of individual pixels at a slightly delayed rate. Potentially, the
    8.18 -peripheral clock signal might be generated and processed to make such a
    8.19 -signal.
    8.20 -
    8.21 -Unlike the vga example, this example employs two DMA channels for pixel data
    8.22 -which are interleaved to investigate a potential remedy for the wide pixel
    8.23 -effect. Unfortunately, despite each channel contributing every other word (or
    8.24 -group of four pixels), the effect persists. However, the picture is perhaps
    8.25 -more stable than in the vga example.
    8.26 -
    8.27 -One significant problem with this example is that scrolling causes the DMA
    8.28 -channels to become ordered incorrectly. This does not affect the vga-timer
    8.29 -example which also employs two DMA channels.
    8.30 -
    8.31 -Hardware Details
    8.32 -================
    8.33 -
    8.34 -The pin usage of this solution is documented below.
    8.35 -
    8.36 -PIC32MX270F256B-50I/SP Pin Assignments
    8.37 ---------------------------------------
    8.38 -
    8.39 -MCLR#          1  \/  28
    8.40 -HSYNC/OC1/RA0  2      27
    8.41 -VSYNC/OC2/RA1  3      26 RB15/U1TX
    8.42 -       D0/RB0  4      25 RB14
    8.43 -       D1/RB1  5      24 RB13/U1RX
    8.44 -       D2/RB2  6      23
    8.45 -       D3/RB3  7      22 RB11/PGEC2
    8.46 -               8      21 RB10/PGEC3
    8.47 -          RA2  9      20
    8.48 -          RA3 10      19
    8.49 -       D4/RB4 11      18 RB9
    8.50 -              12      17 RB8
    8.51 -              13      16 RB7/D7
    8.52 -       D5/RB5 14      15
    8.53 -
    8.54 -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
    8.55 -unlike the MX170 variant).
    8.56 -
    8.57 -UART Connections
    8.58 -----------------
    8.59 -
    8.60 -UART1 is exposed by the RB13 and RB15 pins.
    8.61 -
    8.62 -Data Signal Routing
    8.63 --------------------
    8.64 -
    8.65 -For one bit of intensity, two bits per colour channel:
    8.66 -
    8.67 -D7 -> 2200R -> I
    8.68 -
    8.69 -I -> diode -> R
    8.70 -I -> diode -> G
    8.71 -I -> diode -> B
    8.72 -
    8.73 -D6 (not connected)
    8.74 -
    8.75 -D5 -> 470R -> R
    8.76 -D4 -> 1000R -> R
    8.77 -D3 -> 470R -> G
    8.78 -D2 -> 1000R -> G
    8.79 -D1 -> 470R -> B
    8.80 -D0 -> 1000R -> B
    8.81 -
    8.82 -HSYNC -> HS
    8.83 -VSYNC -> VS
    8.84 -
    8.85 -Output Socket Pinout
    8.86 ---------------------
    8.87 -
    8.88 -  5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
    8.89 -
    8.90 -      10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
    8.91 -
    8.92 -  15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
    8.93 -
    8.94 -Output Cable Pinout
    8.95 --------------------
    8.96 -
    8.97 -      1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
    8.98 -
    8.99 -  6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
   8.100 -
   8.101 -      11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
   8.102 -
   8.103 -References
   8.104 -----------
   8.105 -
   8.106 -https://en.wikipedia.org/wiki/VGA_connector
   8.107 -
   8.108 -http://papilio.cc/index.php?n=Papilio.VGAWing
   8.109 -
   8.110 -http://lucidscience.com/pro-vga%20video%20generator-2.aspx
   8.111 -
   8.112 -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
     9.1 --- a/examples/vga-pmp/README.txt	Thu May 02 23:21:32 2019 +0200
     9.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.3 @@ -1,111 +0,0 @@
     9.4 -Introduction
     9.5 -------------
     9.6 -
     9.7 -This example demonstrates the generation of an analogue VGA signal from a
     9.8 -PIC32 microcontroller using the parallel mode (parallel master port, PMP)
     9.9 -peripheral. The result is not entirely satisfactory:
    9.10 -
    9.11 - * Pixels are very narrow unless buffered using a flip-flop driven by the
    9.12 -   peripheral, this being a characteristic of the way the peripheral works, it
    9.13 -   normally being used to drive memory and display controllers.
    9.14 -
    9.15 - * Introducing a flip-flop means that the final pixel from the pixel data
    9.16 -   remains asserted and must be reset using a second DMA channel.
    9.17 -
    9.18 - * Every fourth pixel is wider than the others, this apparently being an
    9.19 -   artefact of the DMA transfer mechanism.
    9.20 -
    9.21 -It might be possible introduce some kind of delay to the write strobe (PMWR)
    9.22 -and even out the pixel widths, but this has not been investigated.
    9.23 -
    9.24 -It appears to be the case that the system and peripheral clock frequencies
    9.25 -need to be matched. In this example, a frequency of 48MHz has been chosen.
    9.26 -
    9.27 -Hardware Details
    9.28 -================
    9.29 -
    9.30 -The pin usage of this solution is documented below.
    9.31 -
    9.32 -PIC32MX270F256B-50I/SP Pin Assignments
    9.33 ---------------------------------------
    9.34 -
    9.35 -MCLR#          1  \/  28
    9.36 -  D7/PMD7/RA0  2      27
    9.37 -  D6/PMD6/RA1  3      26 RB15/U1TX
    9.38 -  D0/PMD0/RB0  4      25 RB14
    9.39 -  D1/PMD1/RB1  5      24 RB13/(PMRD)/U1RX
    9.40 -  D2/PMD2/RB2  6      23
    9.41 -     PMWR/RB3  7      22 RB11/PGEC2
    9.42 -               8      21 RB10/PGEC3
    9.43 -          RA2  9      20
    9.44 -   (PMA0)/RA3 10      19
    9.45 -HSYNC/OC1/RB4 11      18 RB9/PMD3/D3
    9.46 -              12      17 RB8/PMD4/D4
    9.47 -              13      16 RB7/PMD5/D5
    9.48 -VSYNC/OC2/RB5 14      15
    9.49 -
    9.50 -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
    9.51 -unlike the MX170 variant).
    9.52 -
    9.53 -UART Connections
    9.54 -----------------
    9.55 -
    9.56 -UART1 is exposed by the RB13 and RB15 pins.
    9.57 -
    9.58 -Data Signal Routing
    9.59 --------------------
    9.60 -
    9.61 -A flip-flop is used to buffer the outputs:
    9.62 -
    9.63 -Dn   -> 74HC273:Dn
    9.64 -        74HC273:Qn -> Qn
    9.65 -VCC  -> 74HC273:MR#
    9.66 -PMWR -> 74HC273:CP
    9.67 -
    9.68 -For two bits of intensity, two bits per colour channel:
    9.69 -
    9.70 -Q7 -> 2200R -> I
    9.71 -Q6 -> 4700R -> I
    9.72 -
    9.73 -I -> diode -> R
    9.74 -I -> diode -> G
    9.75 -I -> diode -> B
    9.76 -
    9.77 -Q5 -> 470R -> R
    9.78 -Q4 -> 1000R -> R
    9.79 -Q3 -> 470R -> G
    9.80 -Q2 -> 1000R -> G
    9.81 -Q1 -> 470R -> B
    9.82 -Q0 -> 1000R -> B
    9.83 -
    9.84 -HSYNC -> HS
    9.85 -VSYNC -> VS
    9.86 -
    9.87 -Output Socket Pinout
    9.88 ---------------------
    9.89 -
    9.90 -  5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
    9.91 -
    9.92 -      10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
    9.93 -
    9.94 -  15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
    9.95 -
    9.96 -Output Cable Pinout
    9.97 --------------------
    9.98 -
    9.99 -      1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
   9.100 -
   9.101 -  6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
   9.102 -
   9.103 -      11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
   9.104 -
   9.105 -References
   9.106 -----------
   9.107 -
   9.108 -https://en.wikipedia.org/wiki/VGA_connector
   9.109 -
   9.110 -http://papilio.cc/index.php?n=Papilio.VGAWing
   9.111 -
   9.112 -http://lucidscience.com/pro-vga%20video%20generator-2.aspx
   9.113 -
   9.114 -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
    10.1 --- a/examples/vga-timer/README.txt	Thu May 02 23:21:32 2019 +0200
    10.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.3 @@ -1,145 +0,0 @@
    10.4 -Introduction
    10.5 -------------
    10.6 -
    10.7 -This example demonstrates the generation of an analogue VGA signal from a
    10.8 -PIC32 microcontroller using general output pins. Unlike the vga and vga-pmp
    10.9 -examples, it employs a regular interrupt condition to schedule single-byte
   10.10 -(single-pixel) DMA transfers instead of a single whole-line transfer.
   10.11 -
   10.12 -The principal advantage of this method over the whole-line transfer method is
   10.13 -its production of pixels with consistent widths. The principal disadvantage is
   10.14 -the significant loss of horizontal resolution due to the latencies involved in
   10.15 -propagating interrupt conditions to the DMA controller and thereby initiating
   10.16 -each transfer.
   10.17 -
   10.18 -Employing a peripheral clock that has half the frequency of the system clock
   10.19 -should ensure the stability of the picture, since the lower frequency may make
   10.20 -transfers easier to schedule. The peripheral clock should provide a more
   10.21 -forgiving deadline for each transfer, permitting late transfers to complete on
   10.22 -time.
   10.23 -
   10.24 -Meanwhile, matching the system and peripheral clock frequencies appears to
   10.25 -leave the scheduling of transfers open to uncertainty, with transfers being
   10.26 -more readily delayed by other activity in the system, and with instability of
   10.27 -the picture being the result.
   10.28 -
   10.29 -Unlike the vga example, but in common with the vga-dual example, this example
   10.30 -employs two DMA channels for pixel data which are interleaved to investigate a
   10.31 -potential remedy for the wide pixel effect. This seems to preserve consistent
   10.32 -pixel widths only with a transfer cell size of 1: other cell sizes suffer from
   10.33 -the wide pixel problem. Despite not offering the greater throughput of larger
   10.34 -cell sizes, merely employing dual channels increases throughput for a cell
   10.35 -size of 1, making the technique worth using.
   10.36 -
   10.37 -In contrast to the vga and vga-pmp examples, a special DMA channel is employed
   10.38 -to initiate the pixel transfer process without actually transferring any pixel
   10.39 -data itself. The channel arrangement is as follows:
   10.40 -
   10.41 -  Transfer Initiator  DMA Channel   Transfer Activity
   10.42 -  ------------------  -----------   -----------------
   10.43 -  Timer2              DMA1          zerodata -> PORTB
   10.44 -  Timer3              DMA0          linedata -> PORTB
   10.45 -  Timer3              DMA2          linedata -> PORTB
   10.46 -  Timer3              DMA3          zerodata -> PORTB
   10.47 -
   10.48 -The real purpose of this channel (DMA1) is to capture the Timer2 interrupt
   10.49 -condition and to enable the following channels (DMA0, DMA2) through channel
   10.50 -chaining.  Having been enabled, DMA0 and DMA2 are then able to conduct
   10.51 -transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or
   10.52 -"zero" channel to ensure that the pixel level is set to black at the end of
   10.53 -each display line.
   10.54 -
   10.55 -In principle, other initiating conditions can be used instead of Timer3, which
   10.56 -is configured to produce such conditions as frequently as possible: 
   10.57 -
   10.58 -  * A persistent interrupt condition can be employed instead. For example,
   10.59 -    configuring UART2 and setting the UART2 transfer interrupt, employing this
   10.60 -    interrupt condition for DMA0 and DMA2, produces the same effect.
   10.61 -
   10.62 -  * An external interrupt such as INT2 can be configured, and the peripheral
   10.63 -    clock can be routed through the CLKO pin and back into the microcontroller
   10.64 -    via an appropriate pin. With INT2 being employed as the interrupt
   10.65 -    condition for DMA0 and DMA2, the same effect is produced.
   10.66 -
   10.67 -Hardware Details
   10.68 -================
   10.69 -
   10.70 -The pin usage of this solution is documented below.
   10.71 -
   10.72 -PIC32MX270F256B-50I/SP Pin Assignments
   10.73 ---------------------------------------
   10.74 -
   10.75 -MCLR#          1  \/  28
   10.76 -HSYNC/OC1/RA0  2      27
   10.77 -VSYNC/OC2/RA1  3      26 RB15/U1TX
   10.78 -       D0/RB0  4      25 RB14
   10.79 -       D1/RB1  5      24 RB13/U1RX
   10.80 -       D2/RB2  6      23
   10.81 -       D3/RB3  7      22 RB11/PGEC2
   10.82 -               8      21 RB10/PGEC3
   10.83 -          RA2  9      20
   10.84 -          RA3 10      19
   10.85 -       D4/RB4 11      18 RB9
   10.86 -              12      17 RB8
   10.87 -              13      16 RB7/D7
   10.88 -       D5/RB5 14      15
   10.89 -
   10.90 -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
   10.91 -unlike the MX170 variant).
   10.92 -
   10.93 -UART Connections
   10.94 -----------------
   10.95 -
   10.96 -UART1 is exposed by the RB13 and RB15 pins.
   10.97 -
   10.98 -Data Signal Routing
   10.99 --------------------
  10.100 -
  10.101 -For one bit of intensity, two bits per colour channel:
  10.102 -
  10.103 -D7 -> 2200R -> I
  10.104 -
  10.105 -I -> diode -> R
  10.106 -I -> diode -> G
  10.107 -I -> diode -> B
  10.108 -
  10.109 -D6 (not connected)
  10.110 -
  10.111 -D5 -> 470R -> R
  10.112 -D4 -> 1000R -> R
  10.113 -D3 -> 470R -> G
  10.114 -D2 -> 1000R -> G
  10.115 -D1 -> 470R -> B
  10.116 -D0 -> 1000R -> B
  10.117 -
  10.118 -HSYNC -> HS
  10.119 -VSYNC -> VS
  10.120 -
  10.121 -Output Socket Pinout
  10.122 ---------------------
  10.123 -
  10.124 -  5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
  10.125 -
  10.126 -      10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
  10.127 -
  10.128 -  15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
  10.129 -
  10.130 -Output Cable Pinout
  10.131 --------------------
  10.132 -
  10.133 -      1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
  10.134 -
  10.135 -  6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
  10.136 -
  10.137 -      11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
  10.138 -
  10.139 -References
  10.140 -----------
  10.141 -
  10.142 -https://en.wikipedia.org/wiki/VGA_connector
  10.143 -
  10.144 -http://papilio.cc/index.php?n=Papilio.VGAWing
  10.145 -
  10.146 -http://lucidscience.com/pro-vga%20video%20generator-2.aspx
  10.147 -
  10.148 -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
    11.1 --- a/examples/vga/README.txt	Thu May 02 23:21:32 2019 +0200
    11.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.3 @@ -1,100 +0,0 @@
    11.4 -Introduction
    11.5 -------------
    11.6 -
    11.7 -This example demonstrates the generation of an analogue VGA signal from a
    11.8 -PIC32 microcontroller using general output pins. It follows on from the work
    11.9 -done in the VGAPIC32 project. The result is not entirely satisfactory:
   11.10 -
   11.11 - * Every fourth pixel is wider than the others, this apparently being an
   11.12 -   artefact of the DMA transfer mechanism.
   11.13 -
   11.14 -It might be possible to introduce some kind of delay and even out the pixel
   11.15 -widths, but this has not been investigated with hardware. However, unlike the
   11.16 -vga-pmp example, there is no accompanying signal to potentially orchestrate
   11.17 -the staging of individual pixels at a slightly delayed rate.
   11.18 -
   11.19 -Attempts to introduce other remedies to the wide pixel problem have been made
   11.20 -with the vga-dual and vga-timer examples.
   11.21 -
   11.22 -Hardware Details
   11.23 -================
   11.24 -
   11.25 -The pin usage of this solution is documented below.
   11.26 -
   11.27 -PIC32MX270F256B-50I/SP Pin Assignments
   11.28 ---------------------------------------
   11.29 -
   11.30 -MCLR#          1  \/  28
   11.31 -HSYNC/OC1/RA0  2      27
   11.32 -VSYNC/OC2/RA1  3      26 RB15/U1TX
   11.33 -       D0/RB0  4      25 RB14
   11.34 -       D1/RB1  5      24 RB13/U1RX
   11.35 -       D2/RB2  6      23
   11.36 -       D3/RB3  7      22 RB11/PGEC2
   11.37 -               8      21 RB10/PGEC3
   11.38 -          RA2  9      20
   11.39 -          RA3 10      19
   11.40 -       D4/RB4 11      18 RB9
   11.41 -              12      17 RB8
   11.42 -              13      16 RB7/D7
   11.43 -       D5/RB5 14      15
   11.44 -
   11.45 -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
   11.46 -unlike the MX170 variant).
   11.47 -
   11.48 -UART Connections
   11.49 -----------------
   11.50 -
   11.51 -UART1 is exposed by the RB13 and RB15 pins.
   11.52 -
   11.53 -Data Signal Routing
   11.54 --------------------
   11.55 -
   11.56 -For one bit of intensity, two bits per colour channel:
   11.57 -
   11.58 -D7 -> 2200R -> I
   11.59 -
   11.60 -I -> diode -> R
   11.61 -I -> diode -> G
   11.62 -I -> diode -> B
   11.63 -
   11.64 -D6 (not connected)
   11.65 -
   11.66 -D5 -> 470R -> R
   11.67 -D4 -> 1000R -> R
   11.68 -D3 -> 470R -> G
   11.69 -D2 -> 1000R -> G
   11.70 -D1 -> 470R -> B
   11.71 -D0 -> 1000R -> B
   11.72 -
   11.73 -HSYNC -> HS
   11.74 -VSYNC -> VS
   11.75 -
   11.76 -Output Socket Pinout
   11.77 ---------------------
   11.78 -
   11.79 -  5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
   11.80 -
   11.81 -      10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
   11.82 -
   11.83 -  15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
   11.84 -
   11.85 -Output Cable Pinout
   11.86 --------------------
   11.87 -
   11.88 -      1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
   11.89 -
   11.90 -  6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
   11.91 -
   11.92 -      11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
   11.93 -
   11.94 -References
   11.95 -----------
   11.96 -
   11.97 -https://en.wikipedia.org/wiki/VGA_connector
   11.98 -
   11.99 -http://papilio.cc/index.php?n=Papilio.VGAWing
  11.100 -
  11.101 -http://lucidscience.com/pro-vga%20video%20generator-2.aspx
  11.102 -
  11.103 -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga