paul@298 | 1 | /* |
paul@298 | 2 | * RTC (real-time clock) support for various devices. |
paul@298 | 3 | * |
paul@298 | 4 | * Copyright (C) 2023, 2024 Paul Boddie <paul@boddie.org.uk> |
paul@298 | 5 | * |
paul@298 | 6 | * This program is free software; you can redistribute it and/or |
paul@298 | 7 | * modify it under the terms of the GNU General Public License as |
paul@298 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@298 | 9 | * the License, or (at your option) any later version. |
paul@298 | 10 | * |
paul@298 | 11 | * This program is distributed in the hope that it will be useful, |
paul@298 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@298 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@298 | 14 | * GNU General Public License for more details. |
paul@298 | 15 | * |
paul@298 | 16 | * You should have received a copy of the GNU General Public License |
paul@298 | 17 | * along with this program; if not, write to the Free Software |
paul@298 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@298 | 19 | * Boston, MA 02110-1301, USA |
paul@298 | 20 | */ |
paul@298 | 21 | |
paul@298 | 22 | #pragma once |
paul@298 | 23 | |
paul@298 | 24 | #ifdef __cplusplus |
paul@298 | 25 | |
paul@298 | 26 | // Register locations. |
paul@298 | 27 | |
paul@298 | 28 | enum Regs : unsigned |
paul@298 | 29 | { |
paul@298 | 30 | Rtc_control = 0x000, // RTCCR |
paul@298 | 31 | Rtc_seconds = 0x004, // RTCSR |
paul@298 | 32 | Rtc_alarm_seconds = 0x008, // RTCSAR |
paul@298 | 33 | Rtc_regulator = 0x00c, // RTCGR |
paul@298 | 34 | |
paul@298 | 35 | Hibernate_control = 0x020, // HCR |
paul@298 | 36 | Hibernate_wakeup_filter_counter = 0x024, // HWFCR |
paul@298 | 37 | Hibernate_reset_counter = 0x028, // HRCR |
paul@298 | 38 | Hibernate_wakeup_control = 0x02c, // HWCR |
paul@298 | 39 | Hibernate_wakeup_status = 0x030, // HWRSR |
paul@298 | 40 | Hibernate_scratch_pattern = 0x034, // HSPR |
paul@298 | 41 | Hibernate_write_enable_pattern = 0x03c, // WENR |
paul@298 | 42 | Hibernate_wakeup_pin_configure = 0x048, // WKUPPINCR |
paul@298 | 43 | }; |
paul@298 | 44 | |
paul@298 | 45 | // Field definitions. |
paul@298 | 46 | |
paul@298 | 47 | enum Control_bits : unsigned |
paul@298 | 48 | { |
paul@298 | 49 | Control_write_ready = 0x80, // WRDY |
paul@298 | 50 | Control_1Hz = 0x40, // 1HZ |
paul@298 | 51 | Control_1Hz_irq_enable = 0x20, // 1HZIE |
paul@298 | 52 | Control_alarm = 0x10, // AF |
paul@298 | 53 | Control_alarm_irq_enable = 0x08, // AIE |
paul@298 | 54 | Control_alarm_enable = 0x04, // AE |
paul@298 | 55 | Control_external_divided = 0x02, // SELEXC (JZ4780) |
paul@298 | 56 | Control_rtc_enable = 0x01, // RTCE |
paul@298 | 57 | }; |
paul@298 | 58 | |
paul@298 | 59 | enum Regulator_bits : unsigned |
paul@298 | 60 | { |
paul@298 | 61 | Regulator_lock = 0x80000000, // LOCK |
paul@298 | 62 | Regulator_adjust_count_mask = 0x03ff0000, // ADJC |
paul@298 | 63 | Regulator_1Hz_cycle_count_mask = 0x0000ffff, // NC1HZ |
paul@298 | 64 | }; |
paul@298 | 65 | |
paul@298 | 66 | enum Regulator_limits : unsigned |
paul@298 | 67 | { |
paul@298 | 68 | Regulator_adjust_count_limit = 0x03ff, // ADJC |
paul@298 | 69 | Regulator_1Hz_cycle_count_limit = 0xffff, // NC1HZ |
paul@298 | 70 | }; |
paul@298 | 71 | |
paul@298 | 72 | enum Regulator_shifts : unsigned |
paul@298 | 73 | { |
paul@298 | 74 | Regulator_adjust_count_shift = 16, // ADJC |
paul@298 | 75 | Regulator_1Hz_cycle_count_shift = 0, // NC1HZ |
paul@298 | 76 | }; |
paul@298 | 77 | |
paul@298 | 78 | enum Hibernate_control_bits : unsigned |
paul@298 | 79 | { |
paul@298 | 80 | Hibernate_power_down = 0x01, // PD |
paul@298 | 81 | }; |
paul@298 | 82 | |
paul@298 | 83 | enum Hibernate_wakeup_filter_counter_bits : unsigned |
paul@298 | 84 | { |
paul@298 | 85 | Wakeup_minimum_time_mask = 0xffe0, // HWFCR |
paul@298 | 86 | }; |
paul@298 | 87 | |
paul@298 | 88 | enum Hibernate_reset_counter_bits : unsigned |
paul@298 | 89 | { |
paul@298 | 90 | Reset_assert_time_mask = 0x7800, // HRCR |
paul@298 | 91 | }; |
paul@298 | 92 | |
paul@298 | 93 | enum Hibernate_wakeup_control_bits : unsigned |
paul@298 | 94 | { |
paul@298 | 95 | Power_detect_enable_mask = 0xfffffff8, // EPDET |
paul@298 | 96 | Rtc_alarm_wakeup_enable = 0x00000001, // EALM |
paul@298 | 97 | }; |
paul@298 | 98 | |
paul@298 | 99 | enum Hibernate_wakeup_status_bits : unsigned |
paul@298 | 100 | { |
paul@298 | 101 | Accident_power_down = 0x0100, // APD |
paul@298 | 102 | Hibernate_reset = 0x0020, // HR |
paul@298 | 103 | Pad_pin_reset = 0x0010, // PPR |
paul@298 | 104 | Wakeup_pin_status = 0x0002, // PIN |
paul@298 | 105 | Rtc_alarm_status = 0x0001, // ALM |
paul@298 | 106 | }; |
paul@298 | 107 | |
paul@298 | 108 | enum Hibernate_write_enable_pattern_bits : unsigned |
paul@298 | 109 | { |
paul@298 | 110 | Write_enable_status = 0x80000000, // WEN |
paul@298 | 111 | Write_enable_pattern_mask = 0x0000ffff, // WENPAT |
paul@298 | 112 | Write_enable_pattern = 0x0000a55a, // WENPAT |
paul@298 | 113 | }; |
paul@298 | 114 | |
paul@298 | 115 | enum Hibernate_wakeup_pin_configure_bits : unsigned |
paul@298 | 116 | { |
paul@298 | 117 | Rtc_oscillator_test_enable = 0x00080000, // OSC_TE |
paul@298 | 118 | Oscillator_xtclk_rtclk = 0x00040000, // OSC_RETON |
paul@298 | 119 | Oscillator_xtclk_low = 0x00000000, // OSC_RETON |
paul@298 | 120 | Rtc_internal_oscillator_enable = 0x00010000, // OSC_EN |
paul@298 | 121 | Wakeup_pin_extended_press_mask = 0x000000f0, // P_JUD_LEN |
paul@298 | 122 | Wakeup_pin_extended_press_enable = 0x0000000f, // P_RST_LEN |
paul@298 | 123 | }; |
paul@298 | 124 | |
paul@298 | 125 | #endif /* __cplusplus */ |