paul@160 | 1 | /* |
paul@160 | 2 | * Clock and power management. This exposes the combined functionality |
paul@160 | 3 | * provided by the X1600 and related SoCs. The power management |
paul@160 | 4 | * functionality could be exposed using a separate driver. |
paul@160 | 5 | * |
paul@160 | 6 | * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@160 | 7 | * |
paul@160 | 8 | * This program is free software; you can redistribute it and/or |
paul@160 | 9 | * modify it under the terms of the GNU General Public License as |
paul@160 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@160 | 11 | * the License, or (at your option) any later version. |
paul@160 | 12 | * |
paul@160 | 13 | * This program is distributed in the hope that it will be useful, |
paul@160 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@160 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@160 | 16 | * GNU General Public License for more details. |
paul@160 | 17 | * |
paul@160 | 18 | * You should have received a copy of the GNU General Public License |
paul@160 | 19 | * along with this program; if not, write to the Free Software |
paul@160 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@160 | 21 | * Boston, MA 02110-1301, USA |
paul@160 | 22 | */ |
paul@160 | 23 | |
paul@160 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@160 | 25 | #include "cpm-x1600.h" |
paul@160 | 26 | #include <math.h> |
paul@161 | 27 | #include <stdio.h> |
paul@160 | 28 | |
paul@160 | 29 | |
paul@160 | 30 | |
paul@161 | 31 | // Register locations. |
paul@161 | 32 | |
paul@160 | 33 | enum Regs : unsigned |
paul@160 | 34 | { |
paul@160 | 35 | Clock_control = 0x000, // CPCCR |
paul@160 | 36 | Low_power_control = 0x004, // LCR |
paul@160 | 37 | Clock_gate0 = 0x020, // CLKGR0 |
paul@160 | 38 | Clock_gate1 = 0x028, // CLKGR1 |
paul@160 | 39 | Sleep_control = 0x024, // OPCR (oscillator and power control) |
paul@160 | 40 | Clock_status = 0x0d4, // CPCSR |
paul@160 | 41 | Ddr_divider = 0x02c, // DDRCDR |
paul@160 | 42 | Mac_divider = 0x054, // MACCDR |
paul@160 | 43 | I2s_divider0 = 0x060, // I2SCDR |
paul@160 | 44 | I2s_divider1 = 0x070, // I2S1CDR |
paul@160 | 45 | Lcd_divider = 0x064, // LPCDR |
paul@160 | 46 | Msc_divider0 = 0x068, // MSC0CDR |
paul@160 | 47 | Msc_divider1 = 0x0a4, // MSC1CDR |
paul@160 | 48 | Sfc_divider = 0x074, // SFCCDR |
paul@160 | 49 | Ssi_divider = 0x05c, // SSICDR |
paul@160 | 50 | Cim_divider = 0x078, // CIMCDR |
paul@160 | 51 | Pwm_divider = 0x06c, // PWMCDR |
paul@160 | 52 | Can_divider0 = 0x0a0, // CAN0CDR |
paul@160 | 53 | Can_divider1 = 0x0a8, // CAN1CDR |
paul@160 | 54 | Cdbus_divider = 0x0ac, // CDBUSCDR |
paul@160 | 55 | Macphy0_divider = 0x0e4, // MPHY0C |
paul@160 | 56 | Cpm_interrupt = 0x0b0, // CPM_INTR |
paul@160 | 57 | Cpm_interrupt_en = 0x0b4, // CPM_INTRE |
paul@160 | 58 | Cpm_swi = 0x0bc, // CPM_SFTINT |
paul@160 | 59 | Ddr_gate = 0x0d0, // DRCG |
paul@160 | 60 | Cpm_scratch_prot = 0x038, // CPSPPR |
paul@160 | 61 | Cpm_scratch = 0x034, // CPSPR |
paul@160 | 62 | Usb_param_control0 = 0x03c, // USBPCR |
paul@160 | 63 | Usb_reset_detect = 0x040, // USBRDT |
paul@160 | 64 | Usb_vbus_jitter = 0x044, // USBVBFIL |
paul@160 | 65 | Usb_param_control1 = 0x048, // USBPCR1 |
paul@160 | 66 | Pll_control = 0x00c, // CPPCR |
paul@160 | 67 | Pll_control_A = 0x010, // CPAPCR |
paul@160 | 68 | Pll_control_M = 0x014, // CPMPCR |
paul@160 | 69 | Pll_control_E = 0x018, // CPEPCR |
paul@160 | 70 | Pll_fraction_A = 0x084, // CPAPACR |
paul@160 | 71 | Pll_fraction_M = 0x088, // CPMPACR |
paul@160 | 72 | Pll_fraction_E = 0x08c, // CPEPACR |
paul@160 | 73 | |
paul@161 | 74 | // Special value |
paul@161 | 75 | |
paul@161 | 76 | Reg_undefined = 0xfff, |
paul@160 | 77 | }; |
paul@160 | 78 | |
paul@160 | 79 | enum Clock_source_bits : unsigned |
paul@160 | 80 | { |
paul@160 | 81 | // Clock_control |
paul@160 | 82 | |
paul@160 | 83 | Clock_source_main = 30, // SEL_SRC (output to SCLK_A) |
paul@160 | 84 | Clock_source_cpu = 28, // SEL_CPLL (output to CCLK) |
paul@160 | 85 | Clock_source_hclock0 = 26, // SEL_H0PLL (output to AHB0) |
paul@160 | 86 | Clock_source_hclock2 = 24, // SEL_H2PLL (output to AHB2) |
paul@160 | 87 | |
paul@161 | 88 | // Divider registers |
paul@160 | 89 | |
paul@160 | 90 | Clock_source_can0 = 30, // CA0CS |
paul@160 | 91 | Clock_source_can1 = 30, // CA1CS |
paul@161 | 92 | Clock_source_cdbus = 30, // CDCS |
paul@161 | 93 | Clock_source_cim = 30, // CIMPCS |
paul@161 | 94 | Clock_source_ddr = 30, // DCS |
paul@161 | 95 | Clock_source_i2s = 31, // I2PCS |
paul@161 | 96 | Clock_source_lcd = 30, // LPCS |
paul@161 | 97 | Clock_source_mac = 30, // MACPCS |
paul@161 | 98 | Clock_source_msc0 = 30, // MPCS |
paul@161 | 99 | Clock_source_msc1 = 30, // MPCS |
paul@161 | 100 | Clock_source_pwm = 30, // PWMPCS |
paul@161 | 101 | Clock_source_sfc = 30, // SFCS |
paul@161 | 102 | Clock_source_ssi = 30, // SPCS |
paul@160 | 103 | |
paul@161 | 104 | // Special value |
paul@160 | 105 | |
paul@161 | 106 | Clock_source_undefined = 32, |
paul@160 | 107 | }; |
paul@160 | 108 | |
paul@161 | 109 | enum Clock_source_values : unsigned |
paul@160 | 110 | { |
paul@161 | 111 | Source_mME_main = 0, |
paul@161 | 112 | Source_mME_pll_M = 1, |
paul@161 | 113 | Source_mME_pll_E = 2, |
paul@160 | 114 | |
paul@161 | 115 | // Special value |
paul@160 | 116 | |
paul@161 | 117 | Source_mask = 0x3, |
paul@160 | 118 | }; |
paul@160 | 119 | |
paul@160 | 120 | enum Clock_gate_bits : unsigned |
paul@160 | 121 | { |
paul@161 | 122 | // Clock_control |
paul@161 | 123 | |
paul@161 | 124 | Clock_gate_main = 23, // GATE_SCLKA |
paul@161 | 125 | |
paul@160 | 126 | // Clock_gate0 |
paul@160 | 127 | |
paul@160 | 128 | Clock_gate_ddr = 31, // DDR |
paul@160 | 129 | Clock_gate_ahb0 = 29, // AHB0 |
paul@160 | 130 | Clock_gate_apb0 = 28, // APB0 |
paul@160 | 131 | Clock_gate_rtc = 27, // RTC |
paul@160 | 132 | Clock_gate_aes = 24, // AES |
paul@160 | 133 | Clock_gate_lcd_pixel = 23, // LCD |
paul@160 | 134 | Clock_gate_cim = 22, // CIM |
paul@160 | 135 | Clock_gate_dma = 21, // PDMA |
paul@160 | 136 | Clock_gate_ost = 20, // OST |
paul@160 | 137 | Clock_gate_ssi0 = 19, // SSI0 |
paul@160 | 138 | Clock_gate_timer = 18, // TCU |
paul@160 | 139 | Clock_gate_dtrng = 17, // DTRNG |
paul@160 | 140 | Clock_gate_uart2 = 16, // UART2 |
paul@160 | 141 | Clock_gate_uart1 = 15, // UART1 |
paul@160 | 142 | Clock_gate_uart0 = 14, // UART0 |
paul@160 | 143 | Clock_gate_sadc = 13, // SADC |
paul@160 | 144 | Clock_gate_audio = 11, // AUDIO |
paul@160 | 145 | Clock_gate_ssi_slv = 10, // SSI_SLV |
paul@160 | 146 | Clock_gate_i2c1 = 8, // I2C1 |
paul@160 | 147 | Clock_gate_i2c0 = 7, // I2C0 |
paul@160 | 148 | Clock_gate_msc1 = 5, // MSC1 |
paul@160 | 149 | Clock_gate_msc0 = 4, // MSC0 |
paul@160 | 150 | Clock_gate_otg = 3, // OTG |
paul@160 | 151 | Clock_gate_sfc = 2, // SFC |
paul@160 | 152 | Clock_gate_efuse = 1, // EFUSE |
paul@160 | 153 | Clock_gate_nemc = 0, // NEMC |
paul@160 | 154 | |
paul@160 | 155 | // Clock_gate1 |
paul@160 | 156 | |
paul@160 | 157 | Clock_gate_arb = 30, // ARB |
paul@160 | 158 | Clock_gate_mipi_csi = 28, // MIPI_CSI |
paul@160 | 159 | Clock_gate_intc = 26, // INTC |
paul@160 | 160 | Clock_gate_gmac0 = 23, // GMAC0 |
paul@160 | 161 | Clock_gate_uart3 = 16, // UART3 |
paul@160 | 162 | Clock_gate_i2s0_tx = 9, // I2S0_dev_tclk |
paul@160 | 163 | Clock_gate_i2s0_rx = 8, // I2S0_dev_rclk |
paul@160 | 164 | Clock_gate_hash = 6, // HASH |
paul@160 | 165 | Clock_gate_pwm = 5, // PWM |
paul@160 | 166 | Clock_gate_cdbus = 2, // CDBUS |
paul@160 | 167 | Clock_gate_can1 = 1, // CAN1 |
paul@160 | 168 | Clock_gate_can0 = 0, // CAN0 |
paul@160 | 169 | |
paul@160 | 170 | // Special value |
paul@160 | 171 | |
paul@160 | 172 | Clock_gate_undefined = 32, |
paul@160 | 173 | }; |
paul@160 | 174 | |
paul@161 | 175 | enum Clock_change_enable_bits : unsigned |
paul@161 | 176 | { |
paul@161 | 177 | Clock_change_enable_cpu = 22, |
paul@161 | 178 | Clock_change_enable_ahb0 = 21, |
paul@161 | 179 | Clock_change_enable_ahb2 = 20, |
paul@161 | 180 | Clock_change_enable_ddr = 29, |
paul@161 | 181 | Clock_change_enable_mac = 29, |
paul@161 | 182 | Clock_change_enable_i2s = 29, |
paul@161 | 183 | Clock_change_enable_lcd = 29, |
paul@161 | 184 | Clock_change_enable_msc0 = 29, |
paul@161 | 185 | Clock_change_enable_msc1 = 29, |
paul@161 | 186 | Clock_change_enable_sfc = 29, |
paul@161 | 187 | Clock_change_enable_ssi = 29, |
paul@161 | 188 | Clock_change_enable_cim = 29, |
paul@161 | 189 | Clock_change_enable_pwm = 29, |
paul@161 | 190 | Clock_change_enable_can0 = 29, |
paul@161 | 191 | Clock_change_enable_can1 = 29, |
paul@161 | 192 | Clock_change_enable_cdbus = 29, |
paul@160 | 193 | |
paul@161 | 194 | // Special value |
paul@161 | 195 | |
paul@161 | 196 | Clock_change_enable_undefined = 32, |
paul@160 | 197 | }; |
paul@160 | 198 | |
paul@161 | 199 | enum Clock_busy_bits : unsigned |
paul@161 | 200 | { |
paul@161 | 201 | Clock_busy_cpu = 0, |
paul@161 | 202 | Clock_busy_ddr = 28, |
paul@161 | 203 | Clock_busy_mac = 28, |
paul@161 | 204 | Clock_busy_lcd = 28, |
paul@161 | 205 | Clock_busy_msc0 = 28, |
paul@161 | 206 | Clock_busy_msc1 = 28, |
paul@161 | 207 | Clock_busy_sfc = 28, |
paul@161 | 208 | Clock_busy_ssi = 28, |
paul@161 | 209 | Clock_busy_cim = 28, |
paul@161 | 210 | Clock_busy_pwm = 28, |
paul@161 | 211 | Clock_busy_can0 = 28, |
paul@161 | 212 | Clock_busy_can1 = 28, |
paul@161 | 213 | Clock_busy_cdbus = 28, |
paul@160 | 214 | |
paul@161 | 215 | // Special value |
paul@161 | 216 | |
paul@161 | 217 | Clock_busy_undefined = 32, |
paul@160 | 218 | }; |
paul@160 | 219 | |
paul@161 | 220 | enum Clock_divider_bits : unsigned |
paul@160 | 221 | { |
paul@161 | 222 | Clock_divider_can0 = 0, // CAN0CDR |
paul@161 | 223 | Clock_divider_can1 = 0, // CAN1CDR |
paul@161 | 224 | Clock_divider_cdbus = 0, // CDBUSCDR |
paul@161 | 225 | Clock_divider_cim = 0, // CIMCDR |
paul@161 | 226 | Clock_divider_cpu = 0, // CDIV |
paul@161 | 227 | Clock_divider_ddr = 0, // DDRCDR |
paul@161 | 228 | Clock_divider_hclock0 = 8, // H0DIV (fast AHB peripherals) |
paul@161 | 229 | Clock_divider_hclock2 = 12, // H2DIV (fast AHB peripherals) |
paul@161 | 230 | Clock_divider_l2cache = 4, // L2CDIV |
paul@161 | 231 | Clock_divider_lcd = 0, // LPCDR |
paul@161 | 232 | Clock_divider_mac = 0, // MACCDR |
paul@161 | 233 | Clock_divider_msc0 = 0, // MSC0CDR |
paul@161 | 234 | Clock_divider_msc1 = 0, // MSC1CDR |
paul@161 | 235 | Clock_divider_pclock = 16, // PDIV (slow APB peripherals) |
paul@161 | 236 | Clock_divider_pwm = 0, // PWMCDR |
paul@161 | 237 | Clock_divider_sfc = 0, // SFCCDR |
paul@161 | 238 | Clock_divider_ssi = 0, // SSICDR |
paul@160 | 239 | |
paul@161 | 240 | // Special value |
paul@161 | 241 | |
paul@161 | 242 | Clock_divider_undefined = 32, |
paul@160 | 243 | }; |
paul@160 | 244 | |
paul@160 | 245 | enum Pll_bits : unsigned |
paul@160 | 246 | { |
paul@160 | 247 | // Pll_control_A, Pll_control_M, Pll_control_E |
paul@160 | 248 | |
paul@160 | 249 | Pll_multiplier = 20, // xPLLM |
paul@160 | 250 | Pll_input_division = 14, // xPLLN |
paul@160 | 251 | Pll_output_division1 = 11, // xPLLOD1 |
paul@160 | 252 | Pll_output_division0 = 8, // xPLLOD0 |
paul@160 | 253 | Pll_stable = 3, // xPLL_ON |
paul@160 | 254 | Pll_enabled = 0, // xPLLEN |
paul@160 | 255 | }; |
paul@160 | 256 | |
paul@160 | 257 | enum Pll_bypass_bits : unsigned |
paul@160 | 258 | { |
paul@160 | 259 | Pll_bypass_A = 30, // APLL_BP |
paul@160 | 260 | Pll_bypass_M = 28, // MPLL_BP |
paul@160 | 261 | Pll_bypass_E = 26, // EPLL_BP |
paul@160 | 262 | }; |
paul@160 | 263 | |
paul@160 | 264 | |
paul@160 | 265 | |
paul@165 | 266 | // Common clock abstraction. |
paul@165 | 267 | |
paul@165 | 268 | class Clock_base |
paul@165 | 269 | { |
paul@165 | 270 | protected: |
paul@165 | 271 | |
paul@165 | 272 | // Clock sources and source selection. |
paul@165 | 273 | |
paul@165 | 274 | int num_inputs; |
paul@165 | 275 | enum Clock_identifiers *inputs; |
paul@165 | 276 | uint32_t source_reg; |
paul@165 | 277 | enum Clock_source_bits source_bit; |
paul@165 | 278 | |
paul@165 | 279 | public: |
paul@165 | 280 | explicit Clock_base(int num_inputs = 0, |
paul@165 | 281 | enum Clock_identifiers inputs[] = NULL, |
paul@165 | 282 | uint32_t source_reg = Reg_undefined, |
paul@165 | 283 | enum Clock_source_bits source_bit = Clock_source_undefined) |
paul@165 | 284 | : num_inputs(num_inputs), inputs(inputs), |
paul@165 | 285 | source_reg(source_reg), source_bit(source_bit) |
paul@165 | 286 | { |
paul@165 | 287 | } |
paul@165 | 288 | |
paul@165 | 289 | // Clock control. |
paul@165 | 290 | |
paul@165 | 291 | virtual int have_clock(Cpm_regs ®s); |
paul@165 | 292 | virtual void start_clock(Cpm_regs ®s); |
paul@165 | 293 | virtual void stop_clock(Cpm_regs ®s); |
paul@165 | 294 | |
paul@165 | 295 | // Clock divider. |
paul@165 | 296 | |
paul@165 | 297 | virtual uint32_t get_divider(Cpm_regs ®s); |
paul@165 | 298 | virtual void set_divider(Cpm_regs ®s, uint32_t division); |
paul@165 | 299 | |
paul@165 | 300 | // Clock source. |
paul@165 | 301 | |
paul@165 | 302 | virtual uint8_t get_source(Cpm_regs ®s); |
paul@165 | 303 | virtual void set_source(Cpm_regs ®s, uint8_t source); |
paul@165 | 304 | |
paul@165 | 305 | // Clock source frequency. |
paul@165 | 306 | |
paul@165 | 307 | virtual uint32_t get_source_frequency(Cpm_regs ®s); |
paul@165 | 308 | |
paul@165 | 309 | // Output frequency. |
paul@165 | 310 | |
paul@165 | 311 | virtual uint32_t get_frequency(Cpm_regs ®s); |
paul@165 | 312 | }; |
paul@165 | 313 | |
paul@165 | 314 | |
paul@165 | 315 | |
paul@165 | 316 | // PLL descriptions. |
paul@165 | 317 | |
paul@165 | 318 | class Pll : public Clock_base |
paul@165 | 319 | { |
paul@165 | 320 | uint32_t control_reg; |
paul@165 | 321 | enum Pll_bypass_bits bypass_bit; |
paul@165 | 322 | |
paul@165 | 323 | public: |
paul@165 | 324 | explicit Pll(int num_inputs, enum Clock_identifiers inputs[], |
paul@165 | 325 | uint32_t control_reg, enum Pll_bypass_bits bypass_bit) |
paul@165 | 326 | : Clock_base(num_inputs, inputs), control_reg(control_reg), bypass_bit(bypass_bit) |
paul@165 | 327 | { |
paul@165 | 328 | } |
paul@165 | 329 | |
paul@165 | 330 | // PLL_specific control. |
paul@165 | 331 | |
paul@165 | 332 | int have_pll(Cpm_regs ®s); |
paul@165 | 333 | int pll_enabled(Cpm_regs ®s); |
paul@165 | 334 | int pll_bypassed(Cpm_regs ®s); |
paul@165 | 335 | |
paul@165 | 336 | // Clock control. |
paul@165 | 337 | |
paul@165 | 338 | int have_clock(Cpm_regs ®s); |
paul@165 | 339 | void start_clock(Cpm_regs ®s); |
paul@165 | 340 | void stop_clock(Cpm_regs ®s); |
paul@165 | 341 | |
paul@165 | 342 | // General frequency modifiers. |
paul@165 | 343 | |
paul@165 | 344 | uint16_t get_multiplier(Cpm_regs ®s); |
paul@165 | 345 | void set_multiplier(Cpm_regs ®s, uint16_t multiplier); |
paul@165 | 346 | uint8_t get_input_division(Cpm_regs ®s); |
paul@165 | 347 | void set_input_division(Cpm_regs ®s, uint8_t divider); |
paul@165 | 348 | uint8_t get_output_division(Cpm_regs ®s); |
paul@165 | 349 | void set_output_division(Cpm_regs ®s, uint8_t divider); |
paul@165 | 350 | |
paul@165 | 351 | // PLL output frequency. |
paul@165 | 352 | |
paul@165 | 353 | uint32_t get_frequency(Cpm_regs ®s); |
paul@165 | 354 | |
paul@165 | 355 | // Other operations. |
paul@165 | 356 | |
paul@165 | 357 | void set_pll_parameters(Cpm_regs ®s, uint16_t multiplier, |
paul@165 | 358 | uint8_t in_divider, uint8_t out_divider); |
paul@165 | 359 | }; |
paul@165 | 360 | |
paul@165 | 361 | |
paul@165 | 362 | |
paul@161 | 363 | // Clock descriptions. |
paul@161 | 364 | |
paul@165 | 365 | class Clock : public Clock_base |
paul@161 | 366 | { |
paul@161 | 367 | uint32_t gate_reg; |
paul@161 | 368 | enum Clock_gate_bits gate_bit; |
paul@161 | 369 | uint32_t change_enable_reg; |
paul@161 | 370 | enum Clock_change_enable_bits change_enable_bit; |
paul@161 | 371 | uint32_t busy_reg; |
paul@161 | 372 | enum Clock_busy_bits busy_bit; |
paul@161 | 373 | uint32_t divider_reg; |
paul@161 | 374 | enum Clock_divider_bits divider_bit; |
paul@161 | 375 | uint32_t divider_mask; |
paul@161 | 376 | |
paul@165 | 377 | // Clock control. |
paul@161 | 378 | |
paul@165 | 379 | void change_disable(Cpm_regs ®s); |
paul@165 | 380 | void change_enable(Cpm_regs ®s); |
paul@165 | 381 | void wait_busy(Cpm_regs ®s); |
paul@161 | 382 | |
paul@165 | 383 | public: |
paul@165 | 384 | explicit Clock(int num_inputs = 0, |
paul@165 | 385 | enum Clock_identifiers inputs[] = NULL, |
paul@165 | 386 | uint32_t source_reg = Reg_undefined, |
paul@165 | 387 | enum Clock_source_bits source_bit = Clock_source_undefined, |
paul@165 | 388 | uint32_t gate_reg = Reg_undefined, |
paul@165 | 389 | enum Clock_gate_bits gate_bit = Clock_gate_undefined, |
paul@165 | 390 | uint32_t change_enable_reg = Reg_undefined, |
paul@165 | 391 | enum Clock_change_enable_bits change_enable_bit = Clock_change_enable_undefined, |
paul@165 | 392 | uint32_t busy_reg = Reg_undefined, |
paul@165 | 393 | enum Clock_busy_bits busy_bit = Clock_busy_undefined, |
paul@165 | 394 | uint32_t divider_reg = Reg_undefined, |
paul@165 | 395 | enum Clock_divider_bits divider_bit = Clock_divider_undefined, |
paul@165 | 396 | uint32_t divider_mask = 0) |
paul@165 | 397 | : Clock_base(num_inputs, inputs, source_reg, source_bit), |
paul@165 | 398 | gate_reg(gate_reg), gate_bit(gate_bit), |
paul@165 | 399 | change_enable_reg(change_enable_reg), change_enable_bit(change_enable_bit), |
paul@165 | 400 | busy_reg(busy_reg), busy_bit(busy_bit), |
paul@165 | 401 | divider_reg(divider_reg), divider_bit(divider_bit), divider_mask(divider_mask) |
paul@165 | 402 | { |
paul@165 | 403 | } |
paul@161 | 404 | |
paul@165 | 405 | // Clock control. |
paul@161 | 406 | |
paul@165 | 407 | int have_clock(Cpm_regs ®s); |
paul@165 | 408 | void start_clock(Cpm_regs ®s); |
paul@165 | 409 | void stop_clock(Cpm_regs ®s); |
paul@161 | 410 | |
paul@165 | 411 | // Clock divider. |
paul@161 | 412 | |
paul@165 | 413 | uint32_t get_divider(Cpm_regs ®s); |
paul@165 | 414 | void set_divider(Cpm_regs ®s, uint32_t division); |
paul@161 | 415 | |
paul@165 | 416 | // Clock source. |
paul@161 | 417 | |
paul@165 | 418 | void set_source(Cpm_regs ®s, uint8_t source); |
paul@161 | 419 | }; |
paul@161 | 420 | |
paul@161 | 421 | |
paul@161 | 422 | |
paul@165 | 423 | // Clock instances. |
paul@165 | 424 | |
paul@165 | 425 | #define Clock_inputs(...) ((enum Clock_identifiers []) {__VA_ARGS__}) |
paul@165 | 426 | |
paul@165 | 427 | Clock clock_ahb2_apb(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), |
paul@165 | 428 | Clock_control, Clock_source_hclock2); |
paul@165 | 429 | |
paul@165 | 430 | Clock clock_aic_bitclk; |
paul@165 | 431 | |
paul@165 | 432 | Clock clock_aic_pclk; |
paul@165 | 433 | |
paul@165 | 434 | Clock clock_can0(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external), |
paul@165 | 435 | Can_divider0, Clock_source_can0, |
paul@165 | 436 | Clock_gate1, Clock_gate_can0, |
paul@165 | 437 | Can_divider0, Clock_change_enable_can0, |
paul@165 | 438 | Can_divider0, Clock_busy_can0, |
paul@165 | 439 | Can_divider0, Clock_divider_can0, 0xff); |
paul@165 | 440 | |
paul@165 | 441 | Clock clock_can1(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external), |
paul@165 | 442 | Can_divider1, Clock_source_can1, |
paul@165 | 443 | Clock_gate1, Clock_gate_can1, |
paul@165 | 444 | Can_divider1, Clock_change_enable_can1, |
paul@165 | 445 | Can_divider1, Clock_busy_can1, |
paul@165 | 446 | Can_divider1, Clock_divider_can1, 0xff); |
paul@165 | 447 | |
paul@165 | 448 | Clock clock_cdbus(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 449 | Cdbus_divider, Clock_source_cdbus, |
paul@165 | 450 | Clock_gate1, Clock_gate_cdbus, |
paul@165 | 451 | Cdbus_divider, Clock_change_enable_cdbus, |
paul@165 | 452 | Cdbus_divider, Clock_busy_cdbus, |
paul@165 | 453 | Cdbus_divider, Clock_divider_cdbus, 0xff); |
paul@165 | 454 | |
paul@165 | 455 | Clock clock_cim(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 456 | Cim_divider, Clock_source_cim, |
paul@165 | 457 | Clock_gate0, Clock_gate_cim, |
paul@165 | 458 | Cim_divider, Clock_change_enable_cim, |
paul@165 | 459 | Cim_divider, Clock_busy_cim, |
paul@165 | 460 | Cim_divider, Clock_divider_cim, 0xff); |
paul@165 | 461 | |
paul@165 | 462 | Clock clock_cpu(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), |
paul@165 | 463 | Clock_control, Clock_source_cpu, |
paul@165 | 464 | Reg_undefined, Clock_gate_undefined, |
paul@165 | 465 | Clock_control, Clock_change_enable_cpu, |
paul@165 | 466 | Clock_status, Clock_busy_cpu, |
paul@165 | 467 | Clock_control, Clock_divider_cpu, 0x0f); |
paul@165 | 468 | |
paul@165 | 469 | Clock clock_ddr(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), |
paul@165 | 470 | Ddr_divider, Clock_source_ddr, |
paul@165 | 471 | Clock_gate0, Clock_gate_ddr, |
paul@165 | 472 | Ddr_divider, Clock_change_enable_ddr, |
paul@165 | 473 | Ddr_divider, Clock_busy_ddr, |
paul@165 | 474 | Ddr_divider, Clock_divider_ddr, 0x0f); |
paul@165 | 475 | |
paul@165 | 476 | Clock clock_dma(1, Clock_inputs(Clock_pclock), |
paul@165 | 477 | Reg_undefined, Clock_source_undefined, |
paul@165 | 478 | Clock_gate0, Clock_gate_dma); |
paul@165 | 479 | |
paul@165 | 480 | Clock clock_emac; |
paul@165 | 481 | |
paul@165 | 482 | Clock clock_external; |
paul@165 | 483 | |
paul@165 | 484 | Clock clock_hclock0(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), |
paul@165 | 485 | Clock_control, Clock_source_hclock0, |
paul@165 | 486 | Clock_gate0, Clock_gate_ahb0, |
paul@165 | 487 | Clock_control, Clock_change_enable_ahb0, |
paul@165 | 488 | Reg_undefined, Clock_busy_undefined, |
paul@165 | 489 | Clock_control, Clock_divider_hclock0, 0x0f); |
paul@165 | 490 | |
paul@165 | 491 | Clock clock_hclock2(1, Clock_inputs(Clock_ahb2_apb), |
paul@165 | 492 | Reg_undefined, Clock_source_undefined, |
paul@165 | 493 | Clock_gate0, Clock_gate_apb0, |
paul@165 | 494 | Clock_control, Clock_change_enable_ahb2, |
paul@165 | 495 | Reg_undefined, Clock_busy_undefined, |
paul@165 | 496 | Clock_control, Clock_divider_hclock2, 0x0f); |
paul@165 | 497 | |
paul@165 | 498 | Clock clock_hdmi; |
paul@165 | 499 | |
paul@165 | 500 | Clock clock_i2c(1, Clock_inputs(Clock_pclock), |
paul@165 | 501 | Reg_undefined, Clock_source_undefined, |
paul@165 | 502 | Clock_gate0, Clock_gate_i2c0); |
paul@165 | 503 | |
paul@165 | 504 | Clock clock_i2c0(1, Clock_inputs(Clock_pclock), |
paul@165 | 505 | Reg_undefined, Clock_source_undefined, |
paul@165 | 506 | Clock_gate0, Clock_gate_i2c0); |
paul@165 | 507 | |
paul@165 | 508 | Clock clock_i2c1(1, Clock_inputs(Clock_pclock), |
paul@165 | 509 | Reg_undefined, Clock_source_undefined, |
paul@165 | 510 | Clock_gate0, Clock_gate_i2c1); |
paul@165 | 511 | |
paul@165 | 512 | Clock clock_i2s; |
paul@165 | 513 | |
paul@165 | 514 | Clock clock_i2s0_rx(2, Clock_inputs(Clock_main, Clock_pll_E), |
paul@165 | 515 | I2s_divider0, Clock_source_i2s, |
paul@165 | 516 | Clock_gate1, Clock_gate_i2s0_rx, |
paul@165 | 517 | I2s_divider0, Clock_change_enable_i2s); |
paul@165 | 518 | |
paul@165 | 519 | Clock clock_i2s0_tx(2, Clock_inputs(Clock_main, Clock_pll_E), |
paul@165 | 520 | I2s_divider0, Clock_source_i2s, |
paul@165 | 521 | Clock_gate1, Clock_gate_i2s0_tx, |
paul@165 | 522 | I2s_divider0, Clock_change_enable_i2s); |
paul@165 | 523 | |
paul@165 | 524 | Clock clock_kbc; |
paul@165 | 525 | |
paul@165 | 526 | Clock clock_lcd; |
paul@165 | 527 | |
paul@165 | 528 | Clock clock_lcd_pixel(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 529 | Lcd_divider, Clock_source_lcd, |
paul@165 | 530 | Clock_gate0, Clock_gate_lcd_pixel, |
paul@165 | 531 | Lcd_divider, Clock_change_enable_lcd, |
paul@165 | 532 | Lcd_divider, Clock_busy_lcd, |
paul@165 | 533 | Lcd_divider, Clock_divider_lcd, 0xff); |
paul@165 | 534 | |
paul@165 | 535 | Clock clock_mac(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 536 | Mac_divider, Clock_source_mac, |
paul@165 | 537 | Clock_gate1, Clock_gate_gmac0, |
paul@165 | 538 | Mac_divider, Clock_change_enable_mac, |
paul@165 | 539 | Mac_divider, Clock_busy_mac, |
paul@165 | 540 | Mac_divider, Clock_divider_mac, 0xff); |
paul@165 | 541 | |
paul@165 | 542 | Clock clock_main(3, Clock_inputs(Clock_none, Clock_external, Clock_pll_A), |
paul@165 | 543 | Clock_control, Clock_source_main, |
paul@165 | 544 | Clock_control, Clock_gate_main); |
paul@165 | 545 | |
paul@165 | 546 | Clock clock_msc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 547 | Msc_divider0, Clock_source_msc0, |
paul@165 | 548 | Clock_gate0, Clock_gate_msc0, |
paul@165 | 549 | Msc_divider0, Clock_change_enable_msc0, |
paul@165 | 550 | Msc_divider0, Clock_busy_msc0, |
paul@165 | 551 | Msc_divider0, Clock_divider_msc0, 0xff); |
paul@165 | 552 | |
paul@165 | 553 | Clock clock_msc0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 554 | Msc_divider0, Clock_source_msc0, |
paul@165 | 555 | Clock_gate0, Clock_gate_msc0, |
paul@165 | 556 | Msc_divider0, Clock_change_enable_msc0, |
paul@165 | 557 | Msc_divider0, Clock_busy_msc0, |
paul@165 | 558 | Msc_divider0, Clock_divider_msc0, 0xff); |
paul@165 | 559 | |
paul@165 | 560 | Clock clock_msc1(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 561 | Msc_divider1, Clock_source_msc1, |
paul@165 | 562 | Clock_gate0, Clock_gate_msc1, |
paul@165 | 563 | Msc_divider1, Clock_change_enable_msc1, |
paul@165 | 564 | Msc_divider1, Clock_busy_msc1, |
paul@165 | 565 | Msc_divider1, Clock_divider_msc1, 0xff); |
paul@165 | 566 | |
paul@165 | 567 | Clock clock_none; |
paul@161 | 568 | |
paul@165 | 569 | Clock clock_pclock(1, Clock_inputs(Clock_ahb2_apb), |
paul@165 | 570 | Reg_undefined, Clock_source_undefined, |
paul@165 | 571 | Clock_gate0, Clock_gate_apb0, |
paul@165 | 572 | Reg_undefined, Clock_change_enable_undefined, |
paul@165 | 573 | Reg_undefined, Clock_busy_undefined, |
paul@165 | 574 | Clock_control, Clock_divider_pclock, 0x0f); |
paul@165 | 575 | |
paul@165 | 576 | Pll clock_pll_A(1, Clock_inputs(Clock_external), |
paul@165 | 577 | Pll_control_A, Pll_bypass_A); |
paul@165 | 578 | |
paul@165 | 579 | Pll clock_pll_E(1, Clock_inputs(Clock_external), |
paul@165 | 580 | Pll_control_E, Pll_bypass_E); |
paul@165 | 581 | |
paul@165 | 582 | Pll clock_pll_M(1, Clock_inputs(Clock_external), |
paul@165 | 583 | Pll_control_M, Pll_bypass_M); |
paul@165 | 584 | |
paul@165 | 585 | Clock clock_pwm(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 586 | Pwm_divider, Clock_source_pwm, |
paul@165 | 587 | Clock_gate1, Clock_gate_pwm, |
paul@165 | 588 | Pwm_divider, Clock_change_enable_pwm, |
paul@165 | 589 | Pwm_divider, Clock_busy_pwm, |
paul@165 | 590 | Pwm_divider, Clock_divider_pwm, 0x0f); |
paul@165 | 591 | |
paul@165 | 592 | Clock clock_pwm0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 593 | Pwm_divider, Clock_source_pwm, |
paul@165 | 594 | Clock_gate1, Clock_gate_pwm, |
paul@165 | 595 | Pwm_divider, Clock_change_enable_pwm, |
paul@165 | 596 | Pwm_divider, Clock_busy_pwm, |
paul@165 | 597 | Pwm_divider, Clock_divider_pwm, 0x0f); |
paul@165 | 598 | |
paul@165 | 599 | Clock clock_pwm1; |
paul@165 | 600 | |
paul@165 | 601 | Clock clock_scc; |
paul@165 | 602 | |
paul@165 | 603 | Clock clock_sfc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 604 | Sfc_divider, Clock_source_sfc, |
paul@165 | 605 | Clock_gate0, Clock_gate_sfc, |
paul@165 | 606 | Sfc_divider, Clock_change_enable_sfc, |
paul@165 | 607 | Sfc_divider, Clock_busy_sfc, |
paul@165 | 608 | Sfc_divider, Clock_divider_sfc, 0xff); |
paul@165 | 609 | |
paul@165 | 610 | Clock clock_smb0; |
paul@165 | 611 | |
paul@165 | 612 | Clock clock_smb1; |
paul@165 | 613 | |
paul@165 | 614 | Clock clock_smb2; |
paul@165 | 615 | |
paul@165 | 616 | Clock clock_smb3; |
paul@165 | 617 | |
paul@165 | 618 | Clock clock_smb4; |
paul@165 | 619 | |
paul@165 | 620 | Clock clock_ssi(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), |
paul@165 | 621 | Ssi_divider, Clock_source_ssi, |
paul@165 | 622 | Clock_gate0, Clock_gate_ssi0, |
paul@165 | 623 | Ssi_divider, Clock_change_enable_ssi, |
paul@165 | 624 | Ssi_divider, Clock_busy_ssi, |
paul@165 | 625 | Ssi_divider, Clock_divider_ssi, 0xff); |
paul@165 | 626 | |
paul@165 | 627 | Clock clock_timer(1, Clock_inputs(Clock_pclock), |
paul@165 | 628 | Reg_undefined, Clock_source_undefined, |
paul@165 | 629 | Clock_gate0, Clock_gate_timer); |
paul@165 | 630 | |
paul@165 | 631 | Clock clock_uart0(1, Clock_inputs(Clock_external), |
paul@165 | 632 | Reg_undefined, Clock_source_undefined, |
paul@165 | 633 | Clock_gate0, Clock_gate_uart0); |
paul@165 | 634 | |
paul@165 | 635 | Clock clock_uart1(1, Clock_inputs(Clock_external), |
paul@165 | 636 | Reg_undefined, Clock_source_undefined, |
paul@165 | 637 | Clock_gate0, Clock_gate_uart1); |
paul@165 | 638 | |
paul@165 | 639 | Clock clock_uart2(1, Clock_inputs(Clock_external), |
paul@165 | 640 | Reg_undefined, Clock_source_undefined, |
paul@165 | 641 | Clock_gate0, Clock_gate_uart2); |
paul@165 | 642 | |
paul@165 | 643 | Clock clock_uart3(1, Clock_inputs(Clock_external), |
paul@165 | 644 | Reg_undefined, Clock_source_undefined, |
paul@165 | 645 | Clock_gate1, Clock_gate_uart3); |
paul@165 | 646 | |
paul@165 | 647 | Clock clock_udc; |
paul@165 | 648 | |
paul@165 | 649 | Clock clock_uhc; |
paul@165 | 650 | |
paul@165 | 651 | Clock clock_uprt; |
paul@165 | 652 | |
paul@165 | 653 | |
paul@165 | 654 | |
paul@165 | 655 | // Clock register. |
paul@165 | 656 | |
paul@165 | 657 | static Clock_base *clocks[Clock_identifier_count] = { |
paul@165 | 658 | &clock_ahb2_apb, |
paul@165 | 659 | &clock_aic_bitclk, |
paul@165 | 660 | &clock_aic_pclk, |
paul@165 | 661 | &clock_can0, |
paul@165 | 662 | &clock_can1, |
paul@165 | 663 | &clock_cdbus, |
paul@165 | 664 | &clock_cim, |
paul@165 | 665 | &clock_cpu, |
paul@165 | 666 | &clock_ddr, |
paul@165 | 667 | &clock_dma, |
paul@165 | 668 | &clock_emac, |
paul@165 | 669 | &clock_external, |
paul@165 | 670 | &clock_hclock0, |
paul@165 | 671 | &clock_hclock2, |
paul@165 | 672 | &clock_hdmi, |
paul@165 | 673 | &clock_i2c, |
paul@165 | 674 | &clock_i2c0, |
paul@165 | 675 | &clock_i2c1, |
paul@165 | 676 | &clock_i2s, |
paul@165 | 677 | &clock_i2s0_rx, |
paul@165 | 678 | &clock_i2s0_tx, |
paul@165 | 679 | &clock_kbc, |
paul@165 | 680 | &clock_lcd, |
paul@165 | 681 | &clock_lcd_pixel, |
paul@165 | 682 | &clock_mac, |
paul@165 | 683 | &clock_main, |
paul@165 | 684 | &clock_msc, |
paul@165 | 685 | &clock_msc0, |
paul@165 | 686 | &clock_msc1, |
paul@165 | 687 | &clock_none, |
paul@165 | 688 | &clock_pclock, |
paul@165 | 689 | &clock_pll_A, |
paul@165 | 690 | &clock_pll_E, |
paul@165 | 691 | &clock_pll_M, |
paul@165 | 692 | &clock_pwm, |
paul@165 | 693 | &clock_pwm0, |
paul@165 | 694 | &clock_pwm1, |
paul@165 | 695 | &clock_scc, |
paul@165 | 696 | &clock_sfc, |
paul@165 | 697 | &clock_smb0, |
paul@165 | 698 | &clock_smb1, |
paul@165 | 699 | &clock_smb2, |
paul@165 | 700 | &clock_smb3, |
paul@165 | 701 | &clock_smb4, |
paul@165 | 702 | &clock_ssi, |
paul@165 | 703 | &clock_timer, |
paul@165 | 704 | &clock_uart0, |
paul@165 | 705 | &clock_uart1, |
paul@165 | 706 | &clock_uart2, |
paul@165 | 707 | &clock_uart3, |
paul@165 | 708 | &clock_udc, |
paul@165 | 709 | &clock_uhc, |
paul@165 | 710 | &clock_uprt, |
paul@165 | 711 | }; |
paul@165 | 712 | |
paul@165 | 713 | |
paul@165 | 714 | |
paul@165 | 715 | // Register access. |
paul@165 | 716 | |
paul@165 | 717 | Cpm_regs::Cpm_regs(l4_addr_t addr, uint32_t exclk_freq) |
paul@165 | 718 | : exclk_freq(exclk_freq) |
paul@161 | 719 | { |
paul@165 | 720 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@161 | 721 | } |
paul@161 | 722 | |
paul@165 | 723 | // Utility methods. |
paul@165 | 724 | |
paul@165 | 725 | uint32_t |
paul@165 | 726 | Cpm_regs::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@165 | 727 | { |
paul@165 | 728 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@165 | 729 | } |
paul@165 | 730 | |
paul@165 | 731 | void |
paul@165 | 732 | Cpm_regs::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@165 | 733 | { |
paul@165 | 734 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@165 | 735 | } |
paul@165 | 736 | |
paul@165 | 737 | |
paul@165 | 738 | |
paul@165 | 739 | // Clock control. |
paul@165 | 740 | |
paul@165 | 741 | int |
paul@165 | 742 | Clock_base::have_clock(Cpm_regs ®s) |
paul@165 | 743 | { |
paul@165 | 744 | (void) regs; |
paul@165 | 745 | return true; |
paul@165 | 746 | } |
paul@165 | 747 | |
paul@165 | 748 | void |
paul@165 | 749 | Clock_base::start_clock(Cpm_regs ®s) |
paul@165 | 750 | { |
paul@165 | 751 | (void) regs; |
paul@165 | 752 | } |
paul@165 | 753 | |
paul@165 | 754 | void |
paul@165 | 755 | Clock_base::stop_clock(Cpm_regs ®s) |
paul@165 | 756 | { |
paul@165 | 757 | (void) regs; |
paul@165 | 758 | } |
paul@165 | 759 | |
paul@165 | 760 | // Default divider. |
paul@165 | 761 | |
paul@165 | 762 | uint32_t |
paul@165 | 763 | Clock_base::get_divider(Cpm_regs ®s) |
paul@165 | 764 | { |
paul@165 | 765 | (void) regs; |
paul@165 | 766 | return 1; |
paul@165 | 767 | } |
paul@165 | 768 | |
paul@165 | 769 | void |
paul@165 | 770 | Clock_base::set_divider(Cpm_regs ®s, uint32_t division) |
paul@165 | 771 | { |
paul@165 | 772 | (void) regs; |
paul@165 | 773 | (void) division; |
paul@165 | 774 | } |
paul@165 | 775 | |
paul@165 | 776 | // Clock sources. |
paul@165 | 777 | |
paul@165 | 778 | uint8_t |
paul@165 | 779 | Clock_base::get_source(Cpm_regs ®s) |
paul@165 | 780 | { |
paul@165 | 781 | if (source_bit != Clock_source_undefined) |
paul@165 | 782 | return regs.get_field(source_reg, Source_mask, source_bit); |
paul@165 | 783 | else |
paul@165 | 784 | return 0; |
paul@165 | 785 | } |
paul@165 | 786 | |
paul@165 | 787 | void |
paul@165 | 788 | Clock_base::set_source(Cpm_regs ®s, uint8_t source) |
paul@165 | 789 | { |
paul@165 | 790 | if (source_bit == Clock_source_undefined) |
paul@165 | 791 | return; |
paul@165 | 792 | |
paul@165 | 793 | regs.set_field(source_reg, Source_mask, source_bit, source); |
paul@165 | 794 | } |
paul@165 | 795 | |
paul@165 | 796 | // Clock source frequencies. |
paul@165 | 797 | |
paul@165 | 798 | uint32_t |
paul@165 | 799 | Clock_base::get_source_frequency(Cpm_regs ®s) |
paul@165 | 800 | { |
paul@165 | 801 | // Return the external clock frequency without any input clock. |
paul@165 | 802 | |
paul@165 | 803 | if (num_inputs == 0) |
paul@165 | 804 | return regs.exclk_freq; |
paul@165 | 805 | |
paul@165 | 806 | // Clocks with one source yield that input frequency. |
paul@165 | 807 | |
paul@165 | 808 | else if (num_inputs == 1) |
paul@165 | 809 | return clocks[inputs[0]]->get_frequency(regs); |
paul@165 | 810 | |
paul@165 | 811 | // With multiple sources, obtain the selected source for the clock. |
paul@165 | 812 | |
paul@165 | 813 | uint8_t source = get_source(regs); |
paul@165 | 814 | |
paul@165 | 815 | // Return the frequency of the source. |
paul@165 | 816 | |
paul@165 | 817 | if (source < num_inputs) |
paul@165 | 818 | return clocks[inputs[source]]->get_frequency(regs); |
paul@165 | 819 | else |
paul@165 | 820 | return 0; |
paul@165 | 821 | } |
paul@165 | 822 | |
paul@165 | 823 | // Output clock frequencies. |
paul@165 | 824 | |
paul@165 | 825 | uint32_t |
paul@165 | 826 | Clock_base::get_frequency(Cpm_regs ®s) |
paul@165 | 827 | { |
paul@165 | 828 | return get_source_frequency(regs) / get_divider(regs); |
paul@165 | 829 | } |
paul@165 | 830 | |
paul@165 | 831 | |
paul@165 | 832 | |
paul@165 | 833 | // PLL-specific control. |
paul@165 | 834 | |
paul@165 | 835 | int |
paul@165 | 836 | Pll::have_pll(Cpm_regs ®s) |
paul@165 | 837 | { |
paul@165 | 838 | return regs.get_field(control_reg, 1, Pll_stable); |
paul@165 | 839 | } |
paul@165 | 840 | |
paul@165 | 841 | int |
paul@165 | 842 | Pll::pll_enabled(Cpm_regs ®s) |
paul@165 | 843 | { |
paul@165 | 844 | return regs.get_field(control_reg, 1, Pll_enabled); |
paul@165 | 845 | } |
paul@165 | 846 | |
paul@165 | 847 | int |
paul@165 | 848 | Pll::pll_bypassed(Cpm_regs ®s) |
paul@165 | 849 | { |
paul@165 | 850 | return regs.get_field(control_reg, 1, bypass_bit); |
paul@165 | 851 | } |
paul@165 | 852 | |
paul@165 | 853 | // Clock control. |
paul@165 | 854 | |
paul@165 | 855 | int |
paul@165 | 856 | Pll::have_clock(Cpm_regs ®s) |
paul@165 | 857 | { |
paul@165 | 858 | return have_pll(regs) && pll_enabled(regs); |
paul@165 | 859 | } |
paul@165 | 860 | |
paul@165 | 861 | void |
paul@165 | 862 | Pll::start_clock(Cpm_regs ®s) |
paul@165 | 863 | { |
paul@165 | 864 | regs.set_field(control_reg, 1, Pll_enabled, 1); |
paul@165 | 865 | while (!have_pll(regs)); |
paul@165 | 866 | } |
paul@165 | 867 | |
paul@165 | 868 | void |
paul@165 | 869 | Pll::stop_clock(Cpm_regs ®s) |
paul@161 | 870 | { |
paul@165 | 871 | regs.set_field(control_reg, 1, Pll_enabled, 0); |
paul@165 | 872 | while (have_pll(regs)); |
paul@165 | 873 | } |
paul@165 | 874 | |
paul@165 | 875 | // Feedback (13-bit) multiplier. |
paul@165 | 876 | |
paul@165 | 877 | uint16_t |
paul@165 | 878 | Pll::get_multiplier(Cpm_regs ®s) |
paul@165 | 879 | { |
paul@165 | 880 | return regs.get_field(control_reg, 0x1fff, Pll_multiplier) + 1; |
paul@165 | 881 | } |
paul@165 | 882 | |
paul@165 | 883 | void |
paul@165 | 884 | Pll::set_multiplier(Cpm_regs ®s, uint16_t multiplier) |
paul@165 | 885 | { |
paul@165 | 886 | regs.set_field(control_reg, 0x1fff, Pll_multiplier, multiplier - 1); |
paul@165 | 887 | } |
paul@165 | 888 | |
paul@165 | 889 | // Input (6-bit) divider. |
paul@165 | 890 | |
paul@165 | 891 | uint8_t |
paul@165 | 892 | Pll::get_input_division(Cpm_regs ®s) |
paul@165 | 893 | { |
paul@165 | 894 | return regs.get_field(control_reg, 0x3f, Pll_input_division) + 1; |
paul@165 | 895 | } |
paul@165 | 896 | |
paul@165 | 897 | void |
paul@165 | 898 | Pll::set_input_division(Cpm_regs ®s, uint8_t divider) |
paul@165 | 899 | { |
paul@165 | 900 | regs.set_field(control_reg, 0x3f, Pll_input_division, divider - 1); |
paul@165 | 901 | } |
paul@165 | 902 | |
paul@165 | 903 | // Output (dual 3-bit) dividers. |
paul@165 | 904 | |
paul@165 | 905 | uint8_t |
paul@165 | 906 | Pll::get_output_division(Cpm_regs ®s) |
paul@165 | 907 | { |
paul@165 | 908 | uint8_t d0 = regs.get_field(control_reg, 0x07, Pll_output_division0); |
paul@165 | 909 | uint8_t d1 = regs.get_field(control_reg, 0x07, Pll_output_division1); |
paul@165 | 910 | |
paul@165 | 911 | return d0 * d1; |
paul@165 | 912 | } |
paul@165 | 913 | |
paul@165 | 914 | void |
paul@165 | 915 | Pll::set_output_division(Cpm_regs ®s, uint8_t divider) |
paul@165 | 916 | { |
paul@165 | 917 | // Assert 1 as a minimum. |
paul@165 | 918 | // Divider 0 must be less than or equal to divider 1. |
paul@165 | 919 | |
paul@165 | 920 | uint8_t d0 = (uint8_t) floor(sqrt(divider ? divider : 1)); |
paul@165 | 921 | uint8_t d1 = divider / d0; |
paul@165 | 922 | |
paul@165 | 923 | regs.set_field(control_reg, 0x07, Pll_output_division0, d0); |
paul@165 | 924 | regs.set_field(control_reg, 0x07, Pll_output_division1, d1); |
paul@165 | 925 | } |
paul@165 | 926 | |
paul@165 | 927 | uint32_t |
paul@165 | 928 | Pll::get_frequency(Cpm_regs ®s) |
paul@165 | 929 | { |
paul@165 | 930 | // Test for PLL enable and not PLL bypass. |
paul@165 | 931 | |
paul@165 | 932 | if (pll_enabled(regs)) |
paul@165 | 933 | { |
paul@165 | 934 | if (!pll_bypassed(regs)) |
paul@165 | 935 | return (get_source_frequency(regs) * get_multiplier(regs)) / |
paul@165 | 936 | (get_input_division(regs) * get_output_division(regs)); |
paul@165 | 937 | else |
paul@165 | 938 | return get_source_frequency(regs); |
paul@165 | 939 | } |
paul@165 | 940 | else |
paul@165 | 941 | return 0; |
paul@165 | 942 | } |
paul@165 | 943 | |
paul@165 | 944 | void |
paul@165 | 945 | Pll::set_pll_parameters(Cpm_regs ®s, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@165 | 946 | { |
paul@165 | 947 | set_multiplier(regs, multiplier); |
paul@165 | 948 | set_input_division(regs, in_divider); |
paul@165 | 949 | set_output_division(regs, out_divider); |
paul@161 | 950 | |
paul@165 | 951 | if (pll_enabled(regs) && !pll_bypassed(regs)) |
paul@165 | 952 | while (!have_pll(regs)); |
paul@165 | 953 | } |
paul@165 | 954 | |
paul@165 | 955 | |
paul@165 | 956 | |
paul@165 | 957 | // Clock control. |
paul@165 | 958 | |
paul@165 | 959 | void |
paul@165 | 960 | Clock::change_disable(Cpm_regs ®s) |
paul@165 | 961 | { |
paul@165 | 962 | if (change_enable_bit != Clock_change_enable_undefined) |
paul@165 | 963 | regs.set_field(change_enable_reg, 1, change_enable_bit, 0); |
paul@165 | 964 | } |
paul@165 | 965 | |
paul@165 | 966 | void |
paul@165 | 967 | Clock::change_enable(Cpm_regs ®s) |
paul@165 | 968 | { |
paul@165 | 969 | if (change_enable_bit != Clock_change_enable_undefined) |
paul@165 | 970 | regs.set_field(change_enable_reg, 1, change_enable_bit, 1); |
paul@165 | 971 | } |
paul@165 | 972 | |
paul@165 | 973 | int |
paul@165 | 974 | Clock::have_clock(Cpm_regs ®s) |
paul@165 | 975 | { |
paul@165 | 976 | if (gate_bit != Clock_gate_undefined) |
paul@165 | 977 | return !regs.get_field(gate_reg, 1, gate_bit); |
paul@165 | 978 | else |
paul@165 | 979 | return true; |
paul@165 | 980 | } |
paul@165 | 981 | |
paul@165 | 982 | void |
paul@165 | 983 | Clock::start_clock(Cpm_regs ®s) |
paul@165 | 984 | { |
paul@165 | 985 | if (gate_bit != Clock_gate_undefined) |
paul@165 | 986 | regs.set_field(gate_reg, 1, gate_bit, 0); |
paul@165 | 987 | } |
paul@165 | 988 | |
paul@165 | 989 | void |
paul@165 | 990 | Clock::stop_clock(Cpm_regs ®s) |
paul@165 | 991 | { |
paul@165 | 992 | if (gate_bit != Clock_gate_undefined) |
paul@165 | 993 | regs.set_field(gate_reg, 1, gate_bit, 1); |
paul@165 | 994 | } |
paul@165 | 995 | |
paul@165 | 996 | void |
paul@165 | 997 | Clock::wait_busy(Cpm_regs ®s) |
paul@165 | 998 | { |
paul@165 | 999 | if (busy_bit != Clock_busy_undefined) |
paul@165 | 1000 | while (regs.get_field(busy_reg, 1, busy_bit)); |
paul@165 | 1001 | } |
paul@165 | 1002 | |
paul@165 | 1003 | |
paul@165 | 1004 | |
paul@165 | 1005 | // Clock dividers. |
paul@165 | 1006 | |
paul@165 | 1007 | uint32_t |
paul@165 | 1008 | Clock::get_divider(Cpm_regs ®s) |
paul@165 | 1009 | { |
paul@165 | 1010 | if (divider_bit != Clock_divider_undefined) |
paul@165 | 1011 | return regs.get_field(divider_reg, divider_mask, divider_bit) + 1; |
paul@165 | 1012 | else |
paul@165 | 1013 | return 1; |
paul@165 | 1014 | } |
paul@165 | 1015 | |
paul@165 | 1016 | void |
paul@165 | 1017 | Clock::set_divider(Cpm_regs ®s, uint32_t division) |
paul@165 | 1018 | { |
paul@165 | 1019 | if (divider_bit == Clock_divider_undefined) |
paul@165 | 1020 | return; |
paul@165 | 1021 | |
paul@165 | 1022 | change_enable(regs); |
paul@165 | 1023 | regs.set_field(divider_reg, divider_mask, divider_bit, division - 1); |
paul@165 | 1024 | wait_busy(regs); |
paul@165 | 1025 | change_disable(regs); |
paul@165 | 1026 | } |
paul@165 | 1027 | |
paul@165 | 1028 | void |
paul@165 | 1029 | Clock::set_source(Cpm_regs ®s, uint8_t source) |
paul@165 | 1030 | { |
paul@165 | 1031 | change_enable(regs); |
paul@165 | 1032 | Clock_base::set_source(regs, source); |
paul@165 | 1033 | wait_busy(regs); |
paul@165 | 1034 | change_disable(regs); |
paul@161 | 1035 | } |
paul@161 | 1036 | |
paul@161 | 1037 | |
paul@161 | 1038 | |
paul@160 | 1039 | // If implemented as a Hw::Device, various properties would be |
paul@160 | 1040 | // initialised in the constructor and obtained from the device tree |
paul@160 | 1041 | // definitions. |
paul@160 | 1042 | |
paul@160 | 1043 | Cpm_x1600_chip::Cpm_x1600_chip(l4_addr_t addr, uint32_t exclk_freq) |
paul@165 | 1044 | : _cpm_regs(addr, exclk_freq) |
paul@160 | 1045 | { |
paul@160 | 1046 | // add_cid("cpm"); |
paul@160 | 1047 | // add_cid("cpm-x1600"); |
paul@165 | 1048 | // register_property("exclk_freq", &exclk_freq); |
paul@161 | 1049 | } |
paul@160 | 1050 | |
paul@161 | 1051 | int |
paul@161 | 1052 | Cpm_x1600_chip::have_clock(enum Clock_identifiers clock) |
paul@161 | 1053 | { |
paul@165 | 1054 | return clocks[clock]->have_clock(_cpm_regs); |
paul@161 | 1055 | } |
paul@161 | 1056 | |
paul@161 | 1057 | void |
paul@161 | 1058 | Cpm_x1600_chip::start_clock(enum Clock_identifiers clock) |
paul@160 | 1059 | { |
paul@165 | 1060 | clocks[clock]->start_clock(_cpm_regs); |
paul@161 | 1061 | } |
paul@161 | 1062 | |
paul@161 | 1063 | void |
paul@161 | 1064 | Cpm_x1600_chip::stop_clock(enum Clock_identifiers clock) |
paul@161 | 1065 | { |
paul@165 | 1066 | clocks[clock]->stop_clock(_cpm_regs); |
paul@160 | 1067 | } |
paul@160 | 1068 | |
paul@161 | 1069 | uint32_t |
paul@161 | 1070 | Cpm_x1600_chip::get_divider(enum Clock_identifiers clock) |
paul@160 | 1071 | { |
paul@165 | 1072 | return clocks[clock]->get_divider(_cpm_regs); |
paul@160 | 1073 | } |
paul@160 | 1074 | |
paul@161 | 1075 | void |
paul@161 | 1076 | Cpm_x1600_chip::set_divider(enum Clock_identifiers clock, uint32_t division) |
paul@160 | 1077 | { |
paul@165 | 1078 | clocks[clock]->set_divider(_cpm_regs, division); |
paul@160 | 1079 | } |
paul@160 | 1080 | |
paul@160 | 1081 | uint8_t |
paul@161 | 1082 | Cpm_x1600_chip::get_source(enum Clock_identifiers clock) |
paul@160 | 1083 | { |
paul@165 | 1084 | return clocks[clock]->get_source(_cpm_regs); |
paul@160 | 1085 | } |
paul@160 | 1086 | |
paul@160 | 1087 | void |
paul@161 | 1088 | Cpm_x1600_chip::set_source(enum Clock_identifiers clock, uint8_t source) |
paul@160 | 1089 | { |
paul@165 | 1090 | clocks[clock]->set_source(_cpm_regs, source); |
paul@160 | 1091 | } |
paul@160 | 1092 | |
paul@161 | 1093 | uint32_t |
paul@161 | 1094 | Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock) |
paul@160 | 1095 | { |
paul@165 | 1096 | return clocks[clock]->get_source_frequency(_cpm_regs); |
paul@160 | 1097 | } |
paul@160 | 1098 | |
paul@160 | 1099 | uint32_t |
paul@160 | 1100 | Cpm_x1600_chip::get_frequency(enum Clock_identifiers clock) |
paul@160 | 1101 | { |
paul@165 | 1102 | return clocks[clock]->get_frequency(_cpm_regs); |
paul@160 | 1103 | } |
paul@160 | 1104 | |
paul@160 | 1105 | void |
paul@160 | 1106 | Cpm_x1600_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 1107 | { |
paul@160 | 1108 | switch (clock) |
paul@160 | 1109 | { |
paul@160 | 1110 | // The pixel frequency is based on the selected clock source (SCLK_A, MPLL or |
paul@160 | 1111 | // EPLL). |
paul@160 | 1112 | |
paul@160 | 1113 | case Clock_lcd_pixel: |
paul@165 | 1114 | { |
paul@160 | 1115 | |
paul@160 | 1116 | // Switch to the MPLL and attempt to set the divider. |
paul@160 | 1117 | |
paul@165 | 1118 | Clock_base *lcd = clocks[Clock_lcd_pixel]; |
paul@165 | 1119 | Clock_base *pll = clocks[Clock_pll_M]; |
paul@165 | 1120 | |
paul@165 | 1121 | lcd->set_source(_cpm_regs, Source_mME_pll_M); |
paul@165 | 1122 | pll->start_clock(_cpm_regs); |
paul@165 | 1123 | lcd->set_divider(_cpm_regs, lcd->get_source_frequency(_cpm_regs) / frequency); |
paul@160 | 1124 | break; |
paul@165 | 1125 | } |
paul@160 | 1126 | |
paul@160 | 1127 | default: |
paul@160 | 1128 | break; |
paul@160 | 1129 | } |
paul@160 | 1130 | } |
paul@160 | 1131 | |
paul@165 | 1132 | void |
paul@165 | 1133 | Cpm_x1600_chip::set_pll_parameters(enum Clock_identifiers clock, uint16_t multiplier, |
paul@165 | 1134 | uint8_t in_divider, uint8_t out_divider) |
paul@165 | 1135 | { |
paul@165 | 1136 | Pll *pll = dynamic_cast<Pll *>(clocks[clock]); |
paul@165 | 1137 | |
paul@165 | 1138 | pll->set_pll_parameters(_cpm_regs, multiplier, in_divider, out_divider); |
paul@165 | 1139 | } |
paul@165 | 1140 | |
paul@160 | 1141 | |
paul@160 | 1142 | |
paul@160 | 1143 | // C language interface functions. |
paul@160 | 1144 | |
paul@160 | 1145 | void |
paul@160 | 1146 | *x1600_cpm_init(l4_addr_t cpm_base) |
paul@160 | 1147 | { |
paul@160 | 1148 | /* Initialise the clock and power management peripheral with the |
paul@160 | 1149 | register memory region and a 24MHz EXCLK frequency. */ |
paul@160 | 1150 | |
paul@160 | 1151 | return (void *) new Cpm_x1600_chip(cpm_base, 24000000); |
paul@160 | 1152 | } |
paul@160 | 1153 | |
paul@160 | 1154 | int |
paul@160 | 1155 | x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1156 | { |
paul@160 | 1157 | return static_cast<Cpm_x1600_chip *>(cpm)->have_clock(clock); |
paul@160 | 1158 | } |
paul@160 | 1159 | |
paul@160 | 1160 | void |
paul@160 | 1161 | x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1162 | { |
paul@160 | 1163 | static_cast<Cpm_x1600_chip *>(cpm)->start_clock(clock); |
paul@160 | 1164 | } |
paul@160 | 1165 | |
paul@160 | 1166 | void |
paul@160 | 1167 | x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1168 | { |
paul@160 | 1169 | static_cast<Cpm_x1600_chip *>(cpm)->stop_clock(clock); |
paul@160 | 1170 | } |
paul@160 | 1171 | |
paul@161 | 1172 | uint32_t |
paul@161 | 1173 | x1600_cpm_get_divider(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1174 | { |
paul@161 | 1175 | return static_cast<Cpm_x1600_chip *>(cpm)->get_divider(clock); |
paul@160 | 1176 | } |
paul@160 | 1177 | |
paul@161 | 1178 | void |
paul@161 | 1179 | x1600_cpm_set_divider(void *cpm, enum Clock_identifiers clock, uint32_t divider) |
paul@160 | 1180 | { |
paul@161 | 1181 | return static_cast<Cpm_x1600_chip *>(cpm)->set_divider(clock, divider); |
paul@160 | 1182 | } |
paul@160 | 1183 | |
paul@160 | 1184 | uint8_t |
paul@161 | 1185 | x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1186 | { |
paul@161 | 1187 | return static_cast<Cpm_x1600_chip *>(cpm)->get_source(clock); |
paul@160 | 1188 | } |
paul@160 | 1189 | |
paul@160 | 1190 | void |
paul@161 | 1191 | x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) |
paul@160 | 1192 | { |
paul@161 | 1193 | static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source); |
paul@160 | 1194 | } |
paul@160 | 1195 | |
paul@160 | 1196 | uint32_t |
paul@161 | 1197 | x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1198 | { |
paul@161 | 1199 | return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock); |
paul@160 | 1200 | } |
paul@160 | 1201 | |
paul@160 | 1202 | uint32_t |
paul@160 | 1203 | x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1204 | { |
paul@160 | 1205 | return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock); |
paul@160 | 1206 | } |
paul@160 | 1207 | |
paul@160 | 1208 | void |
paul@160 | 1209 | x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 1210 | { |
paul@160 | 1211 | static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency); |
paul@160 | 1212 | } |
paul@160 | 1213 | |
paul@160 | 1214 | void |
paul@160 | 1215 | x1600_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@160 | 1216 | { |
paul@165 | 1217 | static_cast<Cpm_x1600_chip *>(cpm)->set_pll_parameters(Clock_pll_M, multiplier, in_divider, out_divider); |
paul@160 | 1218 | } |