paul@160 | 1 | /* |
paul@160 | 2 | * Clock and power management. This exposes the combined functionality |
paul@160 | 3 | * provided by the X1600 and related SoCs. The power management |
paul@160 | 4 | * functionality could be exposed using a separate driver. |
paul@160 | 5 | * |
paul@160 | 6 | * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@160 | 7 | * |
paul@160 | 8 | * This program is free software; you can redistribute it and/or |
paul@160 | 9 | * modify it under the terms of the GNU General Public License as |
paul@160 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@160 | 11 | * the License, or (at your option) any later version. |
paul@160 | 12 | * |
paul@160 | 13 | * This program is distributed in the hope that it will be useful, |
paul@160 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@160 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@160 | 16 | * GNU General Public License for more details. |
paul@160 | 17 | * |
paul@160 | 18 | * You should have received a copy of the GNU General Public License |
paul@160 | 19 | * along with this program; if not, write to the Free Software |
paul@160 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@160 | 21 | * Boston, MA 02110-1301, USA |
paul@160 | 22 | */ |
paul@160 | 23 | |
paul@160 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@160 | 25 | #include "cpm-x1600.h" |
paul@160 | 26 | #include <math.h> |
paul@160 | 27 | |
paul@160 | 28 | |
paul@160 | 29 | |
paul@160 | 30 | enum Regs : unsigned |
paul@160 | 31 | { |
paul@160 | 32 | Clock_control = 0x000, // CPCCR |
paul@160 | 33 | Low_power_control = 0x004, // LCR |
paul@160 | 34 | Clock_gate0 = 0x020, // CLKGR0 |
paul@160 | 35 | Clock_gate1 = 0x028, // CLKGR1 |
paul@160 | 36 | Sleep_control = 0x024, // OPCR (oscillator and power control) |
paul@160 | 37 | Clock_status = 0x0d4, // CPCSR |
paul@160 | 38 | Ddr_divider = 0x02c, // DDRCDR |
paul@160 | 39 | Mac_divider = 0x054, // MACCDR |
paul@160 | 40 | I2s_divider0 = 0x060, // I2SCDR |
paul@160 | 41 | I2s_divider1 = 0x070, // I2S1CDR |
paul@160 | 42 | Lcd_divider = 0x064, // LPCDR |
paul@160 | 43 | Msc_divider0 = 0x068, // MSC0CDR |
paul@160 | 44 | Msc_divider1 = 0x0a4, // MSC1CDR |
paul@160 | 45 | Sfc_divider = 0x074, // SFCCDR |
paul@160 | 46 | Ssi_divider = 0x05c, // SSICDR |
paul@160 | 47 | Cim_divider = 0x078, // CIMCDR |
paul@160 | 48 | Pwm_divider = 0x06c, // PWMCDR |
paul@160 | 49 | Can_divider0 = 0x0a0, // CAN0CDR |
paul@160 | 50 | Can_divider1 = 0x0a8, // CAN1CDR |
paul@160 | 51 | Cdbus_divider = 0x0ac, // CDBUSCDR |
paul@160 | 52 | Macphy0_divider = 0x0e4, // MPHY0C |
paul@160 | 53 | Cpm_interrupt = 0x0b0, // CPM_INTR |
paul@160 | 54 | Cpm_interrupt_en = 0x0b4, // CPM_INTRE |
paul@160 | 55 | Cpm_swi = 0x0bc, // CPM_SFTINT |
paul@160 | 56 | Ddr_gate = 0x0d0, // DRCG |
paul@160 | 57 | Cpm_scratch_prot = 0x038, // CPSPPR |
paul@160 | 58 | Cpm_scratch = 0x034, // CPSPR |
paul@160 | 59 | Usb_param_control0 = 0x03c, // USBPCR |
paul@160 | 60 | Usb_reset_detect = 0x040, // USBRDT |
paul@160 | 61 | Usb_vbus_jitter = 0x044, // USBVBFIL |
paul@160 | 62 | Usb_param_control1 = 0x048, // USBPCR1 |
paul@160 | 63 | Pll_control = 0x00c, // CPPCR |
paul@160 | 64 | Pll_control_A = 0x010, // CPAPCR |
paul@160 | 65 | Pll_control_M = 0x014, // CPMPCR |
paul@160 | 66 | Pll_control_E = 0x018, // CPEPCR |
paul@160 | 67 | Pll_fraction_A = 0x084, // CPAPACR |
paul@160 | 68 | Pll_fraction_M = 0x088, // CPMPACR |
paul@160 | 69 | Pll_fraction_E = 0x08c, // CPEPACR |
paul@160 | 70 | }; |
paul@160 | 71 | |
paul@160 | 72 | enum Clock_bits : unsigned |
paul@160 | 73 | { |
paul@160 | 74 | // Clock_control |
paul@160 | 75 | |
paul@160 | 76 | Clock_gate_A = 23, // GATE_SCLKA |
paul@160 | 77 | Clock_cpu_change_enable = 22, // CE_CPU |
paul@160 | 78 | Clock_ahb0_change_enable = 21, // CE_AHB0 |
paul@160 | 79 | Clock_ahb2_change_enable = 20, // CE_AHB2 |
paul@160 | 80 | Clock_pclock_divider = 16, // PDIV (slow APB peripherals) |
paul@160 | 81 | Clock_hclock2_divider = 12, // H2DIV (fast AHB peripherals) |
paul@160 | 82 | Clock_hclock0_divider = 8, // H0DIV (fast AHB peripherals) |
paul@160 | 83 | Clock_l2cache_divider = 4, // L2CDIV |
paul@160 | 84 | Clock_cpu_divider = 0, // CDIV |
paul@160 | 85 | }; |
paul@160 | 86 | |
paul@160 | 87 | enum Clock_source_bits : unsigned |
paul@160 | 88 | { |
paul@160 | 89 | // Clock_control |
paul@160 | 90 | |
paul@160 | 91 | Clock_source_main = 30, // SEL_SRC (output to SCLK_A) |
paul@160 | 92 | Clock_source_cpu = 28, // SEL_CPLL (output to CCLK) |
paul@160 | 93 | Clock_source_hclock0 = 26, // SEL_H0PLL (output to AHB0) |
paul@160 | 94 | Clock_source_hclock2 = 24, // SEL_H2PLL (output to AHB2) |
paul@160 | 95 | |
paul@160 | 96 | // Ddr_divider |
paul@160 | 97 | |
paul@160 | 98 | Clock_source_ddr = 30, // DCS |
paul@160 | 99 | |
paul@160 | 100 | // I2s_divider0 |
paul@160 | 101 | |
paul@160 | 102 | Clock_source_i2s = 31, // I2PCS |
paul@160 | 103 | |
paul@160 | 104 | // Lcd_divider |
paul@160 | 105 | |
paul@160 | 106 | Clock_source_lcd = 30, // LPCS |
paul@160 | 107 | |
paul@160 | 108 | // Mac_divider |
paul@160 | 109 | |
paul@160 | 110 | Clock_source_mac = 30, // MACPCS |
paul@160 | 111 | |
paul@160 | 112 | // Msc_divider0, Msc_divider1 |
paul@160 | 113 | |
paul@160 | 114 | Clock_source_msc0 = 30, // MPCS |
paul@160 | 115 | Clock_source_msc1 = 30, // MPCS |
paul@160 | 116 | |
paul@160 | 117 | // Sfc_divider |
paul@160 | 118 | |
paul@160 | 119 | Clock_source_sfc = 30, // SFCS |
paul@160 | 120 | |
paul@160 | 121 | // Ssi_divider |
paul@160 | 122 | |
paul@160 | 123 | Clock_source_ssi = 30, // SPCS |
paul@160 | 124 | |
paul@160 | 125 | // Cim_divider |
paul@160 | 126 | |
paul@160 | 127 | Clock_source_cim = 30, // CIMPCS |
paul@160 | 128 | |
paul@160 | 129 | // Pwm_divider |
paul@160 | 130 | |
paul@160 | 131 | Clock_source_pwm = 30, // PWMPCS |
paul@160 | 132 | |
paul@160 | 133 | // Can_divider0, Can_divider1 |
paul@160 | 134 | |
paul@160 | 135 | Clock_source_can0 = 30, // CA0CS |
paul@160 | 136 | Clock_source_can1 = 30, // CA1CS |
paul@160 | 137 | |
paul@160 | 138 | // Cdbus_divider |
paul@160 | 139 | |
paul@160 | 140 | Clock_source_cdbus = 30, // CDCS |
paul@160 | 141 | }; |
paul@160 | 142 | |
paul@160 | 143 | enum Clock_sources : unsigned |
paul@160 | 144 | { |
paul@160 | 145 | // Clock_source_main |
paul@160 | 146 | |
paul@160 | 147 | Source_external = 1, // EXCLK |
paul@160 | 148 | Source_pll_A = 2, // APLL |
paul@160 | 149 | |
paul@160 | 150 | // Stoppable clock sources: |
paul@160 | 151 | // Clock_source_cpu, Clock_source_hclock0, Clock_source_hclock2, |
paul@160 | 152 | // Clock_source_ddr |
paul@160 | 153 | |
paul@160 | 154 | Source_mux_stopped = 0, |
paul@160 | 155 | Source_mux_main = 1, // SCLK_A |
paul@160 | 156 | Source_mux_pll_M = 2, // MPLL |
paul@160 | 157 | |
paul@160 | 158 | // Unstoppable clock sources: |
paul@160 | 159 | // Clock_source_mac, Clock_source_i2s, Clock_source_lcd, Clock_source_msc0, |
paul@160 | 160 | // Clock_source_msc1, Clock_source_sfc, Clock_source_ssi, Clock_source_cim, |
paul@160 | 161 | // Clock_source_pwm, Clock_source_can0, Clock_source_can1, Clock_source_cdbus |
paul@160 | 162 | |
paul@160 | 163 | Source_main = 0, // SCLK_A |
paul@160 | 164 | Source_pll_M = 1, // MPLL |
paul@160 | 165 | Source_pll_E = 2, // EPLL |
paul@160 | 166 | |
paul@160 | 167 | Source_i2s_pll_E = 1, // EPLL |
paul@160 | 168 | |
paul@160 | 169 | Source_can_external = 3, // EXCLK |
paul@160 | 170 | }; |
paul@160 | 171 | |
paul@160 | 172 | enum Clock_gate_bits : unsigned |
paul@160 | 173 | { |
paul@160 | 174 | // Clock_gate0 |
paul@160 | 175 | |
paul@160 | 176 | Clock_gate_ddr = 31, // DDR |
paul@160 | 177 | Clock_gate_ahb0 = 29, // AHB0 |
paul@160 | 178 | Clock_gate_apb0 = 28, // APB0 |
paul@160 | 179 | Clock_gate_rtc = 27, // RTC |
paul@160 | 180 | Clock_gate_aes = 24, // AES |
paul@160 | 181 | Clock_gate_lcd_pixel = 23, // LCD |
paul@160 | 182 | Clock_gate_cim = 22, // CIM |
paul@160 | 183 | Clock_gate_dma = 21, // PDMA |
paul@160 | 184 | Clock_gate_ost = 20, // OST |
paul@160 | 185 | Clock_gate_ssi0 = 19, // SSI0 |
paul@160 | 186 | Clock_gate_timer = 18, // TCU |
paul@160 | 187 | Clock_gate_dtrng = 17, // DTRNG |
paul@160 | 188 | Clock_gate_uart2 = 16, // UART2 |
paul@160 | 189 | Clock_gate_uart1 = 15, // UART1 |
paul@160 | 190 | Clock_gate_uart0 = 14, // UART0 |
paul@160 | 191 | Clock_gate_sadc = 13, // SADC |
paul@160 | 192 | Clock_gate_audio = 11, // AUDIO |
paul@160 | 193 | Clock_gate_ssi_slv = 10, // SSI_SLV |
paul@160 | 194 | Clock_gate_i2c1 = 8, // I2C1 |
paul@160 | 195 | Clock_gate_i2c0 = 7, // I2C0 |
paul@160 | 196 | Clock_gate_msc1 = 5, // MSC1 |
paul@160 | 197 | Clock_gate_msc0 = 4, // MSC0 |
paul@160 | 198 | Clock_gate_otg = 3, // OTG |
paul@160 | 199 | Clock_gate_sfc = 2, // SFC |
paul@160 | 200 | Clock_gate_efuse = 1, // EFUSE |
paul@160 | 201 | Clock_gate_nemc = 0, // NEMC |
paul@160 | 202 | |
paul@160 | 203 | // Clock_gate1 |
paul@160 | 204 | |
paul@160 | 205 | Clock_gate_arb = 30, // ARB |
paul@160 | 206 | Clock_gate_mipi_csi = 28, // MIPI_CSI |
paul@160 | 207 | Clock_gate_intc = 26, // INTC |
paul@160 | 208 | Clock_gate_gmac0 = 23, // GMAC0 |
paul@160 | 209 | Clock_gate_uart3 = 16, // UART3 |
paul@160 | 210 | Clock_gate_i2s0_tx = 9, // I2S0_dev_tclk |
paul@160 | 211 | Clock_gate_i2s0_rx = 8, // I2S0_dev_rclk |
paul@160 | 212 | Clock_gate_hash = 6, // HASH |
paul@160 | 213 | Clock_gate_pwm = 5, // PWM |
paul@160 | 214 | Clock_gate_cdbus = 2, // CDBUS |
paul@160 | 215 | Clock_gate_can1 = 1, // CAN1 |
paul@160 | 216 | Clock_gate_can0 = 0, // CAN0 |
paul@160 | 217 | |
paul@160 | 218 | // Special value |
paul@160 | 219 | |
paul@160 | 220 | Clock_gate_undefined = 32, |
paul@160 | 221 | }; |
paul@160 | 222 | |
paul@160 | 223 | // Clock gate register correspondences. |
paul@160 | 224 | |
paul@160 | 225 | static uint32_t clock_gate_reg[Clock_identifier_count] = { |
paul@160 | 226 | /* Clock_aic_bitclk */ 0, |
paul@160 | 227 | /* Clock_aic_pclk */ 0, |
paul@160 | 228 | /* Clock_can0 */ Clock_gate1, |
paul@160 | 229 | /* Clock_can1 */ Clock_gate1, |
paul@160 | 230 | /* Clock_cdbus */ Clock_gate1, |
paul@160 | 231 | /* Clock_cim */ Clock_gate0, |
paul@160 | 232 | /* Clock_ddr */ Clock_gate0, |
paul@160 | 233 | /* Clock_dma */ Clock_gate0, |
paul@160 | 234 | /* Clock_emac */ 0, |
paul@160 | 235 | /* Clock_hdmi */ 0, |
paul@160 | 236 | /* Clock_i2c */ Clock_gate0, |
paul@160 | 237 | /* Clock_i2c0 */ Clock_gate0, |
paul@160 | 238 | /* Clock_i2c1 */ Clock_gate0, |
paul@160 | 239 | /* Clock_i2s */ 0, |
paul@160 | 240 | /* Clock_i2s0_rx */ Clock_gate1, |
paul@160 | 241 | /* Clock_i2s0_tx */ Clock_gate1, |
paul@160 | 242 | /* Clock_kbc */ 0, |
paul@160 | 243 | /* Clock_lcd */ 0, |
paul@160 | 244 | /* Clock_lcd_pixel */ Clock_gate0, |
paul@160 | 245 | /* Clock_mac */ Clock_gate1, |
paul@160 | 246 | /* Clock_msc */ Clock_gate0, |
paul@160 | 247 | /* Clock_msc0 */ Clock_gate0, |
paul@160 | 248 | /* Clock_msc1 */ Clock_gate0, |
paul@160 | 249 | /* Clock_pwm */ Clock_gate1, |
paul@160 | 250 | /* Clock_pwm0 */ Clock_gate1, |
paul@160 | 251 | /* Clock_pwm1 */ 0, |
paul@160 | 252 | /* Clock_scc */ 0, |
paul@160 | 253 | /* Clock_sfc */ Clock_gate0, |
paul@160 | 254 | /* Clock_smb0 */ 0, |
paul@160 | 255 | /* Clock_smb1 */ 0, |
paul@160 | 256 | /* Clock_smb2 */ 0, |
paul@160 | 257 | /* Clock_smb3 */ 0, |
paul@160 | 258 | /* Clock_smb4 */ 0, |
paul@160 | 259 | /* Clock_ssi */ Clock_gate0, |
paul@160 | 260 | /* Clock_timer */ Clock_gate0, |
paul@160 | 261 | /* Clock_uart0 */ Clock_gate0, |
paul@160 | 262 | /* Clock_uart1 */ Clock_gate0, |
paul@160 | 263 | /* Clock_uart2 */ Clock_gate0, |
paul@160 | 264 | /* Clock_uart3 */ Clock_gate1, |
paul@160 | 265 | /* Clock_udc */ 0, |
paul@160 | 266 | /* Clock_uhc */ 0, |
paul@160 | 267 | /* Clock_uprt */ 0, |
paul@160 | 268 | }; |
paul@160 | 269 | |
paul@160 | 270 | // Clock gate register bit correspondences. |
paul@160 | 271 | |
paul@160 | 272 | static enum Clock_gate_bits clock_gate_bit[Clock_identifier_count] = { |
paul@160 | 273 | /* Clock_aic_bitclk */ Clock_gate_undefined, |
paul@160 | 274 | /* Clock_aic_pclk */ Clock_gate_undefined, |
paul@160 | 275 | /* Clock_can0 */ Clock_gate_can0, |
paul@160 | 276 | /* Clock_can1 */ Clock_gate_can1, |
paul@160 | 277 | /* Clock_cdbus */ Clock_gate_cdbus, |
paul@160 | 278 | /* Clock_cim */ Clock_gate_cim, |
paul@160 | 279 | /* Clock_ddr */ Clock_gate_ddr, |
paul@160 | 280 | /* Clock_dma */ Clock_gate_dma, |
paul@160 | 281 | /* Clock_emac */ Clock_gate_undefined, |
paul@160 | 282 | /* Clock_hdmi */ Clock_gate_undefined, |
paul@160 | 283 | /* Clock_i2c */ Clock_gate_i2c0, |
paul@160 | 284 | /* Clock_i2c0 */ Clock_gate_i2c0, |
paul@160 | 285 | /* Clock_i2c1 */ Clock_gate_i2c1, |
paul@160 | 286 | /* Clock_i2s */ Clock_gate_undefined, |
paul@160 | 287 | /* Clock_i2s0_rx */ Clock_gate_i2s0_rx, |
paul@160 | 288 | /* Clock_i2s0_tx */ Clock_gate_i2s0_tx, |
paul@160 | 289 | /* Clock_kbc */ Clock_gate_undefined, |
paul@160 | 290 | /* Clock_lcd */ Clock_gate_undefined, |
paul@160 | 291 | /* Clock_lcd_pixel */ Clock_gate_lcd_pixel, |
paul@160 | 292 | /* Clock_mac */ Clock_gate_gmac0, |
paul@160 | 293 | /* Clock_msc */ Clock_gate_msc0, |
paul@160 | 294 | /* Clock_msc0 */ Clock_gate_msc0, |
paul@160 | 295 | /* Clock_msc1 */ Clock_gate_msc1, |
paul@160 | 296 | /* Clock_pwm */ Clock_gate_pwm, |
paul@160 | 297 | /* Clock_pwm0 */ Clock_gate_pwm, |
paul@160 | 298 | /* Clock_pwm1 */ Clock_gate_undefined, |
paul@160 | 299 | /* Clock_scc */ Clock_gate_undefined, |
paul@160 | 300 | /* Clock_sfc */ Clock_gate_sfc, |
paul@160 | 301 | /* Clock_smb0 */ Clock_gate_undefined, |
paul@160 | 302 | /* Clock_smb1 */ Clock_gate_undefined, |
paul@160 | 303 | /* Clock_smb2 */ Clock_gate_undefined, |
paul@160 | 304 | /* Clock_smb3 */ Clock_gate_undefined, |
paul@160 | 305 | /* Clock_smb4 */ Clock_gate_undefined, |
paul@160 | 306 | /* Clock_ssi */ Clock_gate_ssi0, |
paul@160 | 307 | /* Clock_timer */ Clock_gate_timer, |
paul@160 | 308 | /* Clock_uart0 */ Clock_gate_uart0, |
paul@160 | 309 | /* Clock_uart1 */ Clock_gate_uart1, |
paul@160 | 310 | /* Clock_uart2 */ Clock_gate_uart2, |
paul@160 | 311 | /* Clock_uart3 */ Clock_gate_uart3, |
paul@160 | 312 | /* Clock_udc */ Clock_gate_undefined, |
paul@160 | 313 | /* Clock_uhc */ Clock_gate_undefined, |
paul@160 | 314 | /* Clock_uprt */ Clock_gate_undefined, |
paul@160 | 315 | }; |
paul@160 | 316 | |
paul@160 | 317 | enum Divider_bits : unsigned |
paul@160 | 318 | { |
paul@160 | 319 | Ddr_divider_value = 0, // DDRCDR |
paul@160 | 320 | Lcd_divider_value = 0, // LPCDR |
paul@160 | 321 | }; |
paul@160 | 322 | |
paul@160 | 323 | enum Clock_status_values : unsigned |
paul@160 | 324 | { |
paul@160 | 325 | Lcd_change_enable = 0x20000000, // CE_LCD |
paul@160 | 326 | Lcd_change_busy = 0x10000000, // LCD_BUSY |
paul@160 | 327 | Lcd_clock_stop = 0x08000000, // LCD_STOP |
paul@160 | 328 | }; |
paul@160 | 329 | |
paul@160 | 330 | enum Pll_bits : unsigned |
paul@160 | 331 | { |
paul@160 | 332 | // Pll_control_A, Pll_control_M, Pll_control_E |
paul@160 | 333 | |
paul@160 | 334 | Pll_multiplier = 20, // xPLLM |
paul@160 | 335 | Pll_input_division = 14, // xPLLN |
paul@160 | 336 | Pll_output_division1 = 11, // xPLLOD1 |
paul@160 | 337 | Pll_output_division0 = 8, // xPLLOD0 |
paul@160 | 338 | Pll_stable = 3, // xPLL_ON |
paul@160 | 339 | Pll_enabled = 0, // xPLLEN |
paul@160 | 340 | }; |
paul@160 | 341 | |
paul@160 | 342 | enum Pll_bypass_bits : unsigned |
paul@160 | 343 | { |
paul@160 | 344 | Pll_bypass_A = 30, // APLL_BP |
paul@160 | 345 | Pll_bypass_M = 28, // MPLL_BP |
paul@160 | 346 | Pll_bypass_E = 26, // EPLL_BP |
paul@160 | 347 | }; |
paul@160 | 348 | |
paul@160 | 349 | |
paul@160 | 350 | |
paul@160 | 351 | // If implemented as a Hw::Device, various properties would be |
paul@160 | 352 | // initialised in the constructor and obtained from the device tree |
paul@160 | 353 | // definitions. |
paul@160 | 354 | |
paul@160 | 355 | Cpm_x1600_chip::Cpm_x1600_chip(l4_addr_t addr, uint32_t exclk_freq) |
paul@160 | 356 | : _exclk_freq(exclk_freq) |
paul@160 | 357 | { |
paul@160 | 358 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@160 | 359 | |
paul@160 | 360 | // add_cid("cpm"); |
paul@160 | 361 | // add_cid("cpm-x1600"); |
paul@160 | 362 | // register_property("exclk_freq", &_exclk_freq); |
paul@160 | 363 | } |
paul@160 | 364 | |
paul@160 | 365 | // Clock/timer control. |
paul@160 | 366 | |
paul@160 | 367 | uint32_t |
paul@160 | 368 | Cpm_x1600_chip::get_clock_gate_register(enum Clock_identifiers clock) |
paul@160 | 369 | { |
paul@160 | 370 | return clock_gate_reg[clock]; |
paul@160 | 371 | } |
paul@160 | 372 | |
paul@160 | 373 | uint32_t |
paul@160 | 374 | Cpm_x1600_chip::get_clock_gate_value(enum Clock_identifiers clock) |
paul@160 | 375 | { |
paul@160 | 376 | return 1 << clock_gate_bit[clock]; |
paul@160 | 377 | } |
paul@160 | 378 | |
paul@160 | 379 | int |
paul@160 | 380 | Cpm_x1600_chip::have_clock(enum Clock_identifiers clock) |
paul@160 | 381 | { |
paul@160 | 382 | return !(_regs[get_clock_gate_register(clock)] & get_clock_gate_value(clock)); |
paul@160 | 383 | } |
paul@160 | 384 | |
paul@160 | 385 | void |
paul@160 | 386 | Cpm_x1600_chip::start_clock(enum Clock_identifiers clock) |
paul@160 | 387 | { |
paul@160 | 388 | uint32_t gate = get_clock_gate_register(clock); |
paul@160 | 389 | |
paul@160 | 390 | _regs[gate] = _regs[gate] & ~get_clock_gate_value(clock); |
paul@160 | 391 | } |
paul@160 | 392 | |
paul@160 | 393 | void |
paul@160 | 394 | Cpm_x1600_chip::stop_clock(enum Clock_identifiers clock) |
paul@160 | 395 | { |
paul@160 | 396 | uint32_t gate = get_clock_gate_register(clock); |
paul@160 | 397 | |
paul@160 | 398 | _regs[gate] = _regs[gate] | get_clock_gate_value(clock); |
paul@160 | 399 | } |
paul@160 | 400 | |
paul@160 | 401 | |
paul@160 | 402 | |
paul@160 | 403 | // Utility methods. |
paul@160 | 404 | |
paul@160 | 405 | uint32_t |
paul@160 | 406 | Cpm_x1600_chip::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@160 | 407 | { |
paul@160 | 408 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@160 | 409 | } |
paul@160 | 410 | |
paul@160 | 411 | void |
paul@160 | 412 | Cpm_x1600_chip::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@160 | 413 | { |
paul@160 | 414 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@160 | 415 | } |
paul@160 | 416 | |
paul@160 | 417 | // General clock divider access. |
paul@160 | 418 | |
paul@160 | 419 | uint8_t |
paul@160 | 420 | Cpm_x1600_chip::_get_divider(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@160 | 421 | { |
paul@160 | 422 | return get_field(reg, mask, shift) + 1; |
paul@160 | 423 | } |
paul@160 | 424 | |
paul@160 | 425 | |
paul@160 | 426 | |
paul@160 | 427 | // PLL control. |
paul@160 | 428 | |
paul@160 | 429 | // Return whether the PLL is stable. |
paul@160 | 430 | |
paul@160 | 431 | int |
paul@160 | 432 | Cpm_x1600_chip::have_pll(uint32_t pll_reg) |
paul@160 | 433 | { |
paul@160 | 434 | return _regs[pll_reg] & (1 << Pll_stable); |
paul@160 | 435 | } |
paul@160 | 436 | |
paul@160 | 437 | int |
paul@160 | 438 | Cpm_x1600_chip::pll_enabled(uint32_t pll_reg) |
paul@160 | 439 | { |
paul@160 | 440 | return _regs[pll_reg] & (1 << Pll_enabled); |
paul@160 | 441 | } |
paul@160 | 442 | |
paul@160 | 443 | int |
paul@160 | 444 | Cpm_x1600_chip::pll_bypassed(uint32_t pll_reg) |
paul@160 | 445 | { |
paul@160 | 446 | uint32_t mask; |
paul@160 | 447 | |
paul@160 | 448 | switch (pll_reg) |
paul@160 | 449 | { |
paul@160 | 450 | case Pll_control_A: mask = (1 << Pll_bypass_A); break; |
paul@160 | 451 | case Pll_control_M: mask = (1 << Pll_bypass_M); break; |
paul@160 | 452 | case Pll_control_E: mask = (1 << Pll_bypass_E); break; |
paul@160 | 453 | default: mask = 0; break; |
paul@160 | 454 | } |
paul@160 | 455 | |
paul@160 | 456 | return _regs[Pll_control] & mask; |
paul@160 | 457 | } |
paul@160 | 458 | |
paul@160 | 459 | void |
paul@160 | 460 | Cpm_x1600_chip::pll_enable(uint32_t pll_reg) |
paul@160 | 461 | { |
paul@160 | 462 | _regs[pll_reg] = _regs[pll_reg] | (1 << Pll_enabled); |
paul@160 | 463 | while (!(_regs[pll_reg] & (1 << Pll_stable))); |
paul@160 | 464 | } |
paul@160 | 465 | |
paul@160 | 466 | void |
paul@160 | 467 | Cpm_x1600_chip::pll_disable(uint32_t pll_reg) |
paul@160 | 468 | { |
paul@160 | 469 | _regs[pll_reg] = _regs[pll_reg] & ~(1 << Pll_enabled); |
paul@160 | 470 | while (_regs[pll_reg] & (1 << Pll_stable)); |
paul@160 | 471 | } |
paul@160 | 472 | |
paul@160 | 473 | // Feedback (13-bit) multiplier. |
paul@160 | 474 | |
paul@160 | 475 | uint16_t |
paul@160 | 476 | Cpm_x1600_chip::get_multiplier(uint32_t pll_reg) |
paul@160 | 477 | { |
paul@160 | 478 | return get_field(pll_reg, 0x1fff, Pll_multiplier) + 1; |
paul@160 | 479 | } |
paul@160 | 480 | |
paul@160 | 481 | void |
paul@160 | 482 | Cpm_x1600_chip::set_multiplier(uint32_t pll_reg, uint16_t multiplier) |
paul@160 | 483 | { |
paul@160 | 484 | set_field(pll_reg, 0x1fff, Pll_multiplier, multiplier - 1); |
paul@160 | 485 | } |
paul@160 | 486 | |
paul@160 | 487 | // Input (6-bit) divider. |
paul@160 | 488 | |
paul@160 | 489 | uint8_t |
paul@160 | 490 | Cpm_x1600_chip::get_input_division(uint32_t pll_reg) |
paul@160 | 491 | { |
paul@160 | 492 | return get_field(pll_reg, 0x3f, Pll_input_division) + 1; |
paul@160 | 493 | } |
paul@160 | 494 | |
paul@160 | 495 | void |
paul@160 | 496 | Cpm_x1600_chip::set_input_division(uint32_t pll_reg, uint8_t divider) |
paul@160 | 497 | { |
paul@160 | 498 | set_field(pll_reg, 0x3f, Pll_input_division, divider - 1); |
paul@160 | 499 | } |
paul@160 | 500 | |
paul@160 | 501 | // Output (dual 3-bit) dividers. |
paul@160 | 502 | |
paul@160 | 503 | uint8_t |
paul@160 | 504 | Cpm_x1600_chip::get_output_division(uint32_t pll_reg) |
paul@160 | 505 | { |
paul@160 | 506 | uint8_t d0 = get_field(pll_reg, 0x07, Pll_output_division0); |
paul@160 | 507 | uint8_t d1 = get_field(pll_reg, 0x07, Pll_output_division1); |
paul@160 | 508 | |
paul@160 | 509 | return d0 * d1; |
paul@160 | 510 | } |
paul@160 | 511 | |
paul@160 | 512 | void |
paul@160 | 513 | Cpm_x1600_chip::set_output_division(uint32_t pll_reg, uint8_t divider) |
paul@160 | 514 | { |
paul@160 | 515 | // Assert 1 as a minimum. |
paul@160 | 516 | // Divider 0 must be less than or equal to divider 1. |
paul@160 | 517 | |
paul@160 | 518 | uint8_t d0 = (uint8_t) floor(sqrt(divider ? divider : 1)); |
paul@160 | 519 | uint8_t d1 = divider / d0; |
paul@160 | 520 | |
paul@160 | 521 | set_field(pll_reg, 0x07, Pll_output_division0, d0); |
paul@160 | 522 | set_field(pll_reg, 0x07, Pll_output_division1, d1); |
paul@160 | 523 | } |
paul@160 | 524 | |
paul@160 | 525 | uint32_t |
paul@160 | 526 | Cpm_x1600_chip::get_pll_frequency(uint32_t pll_reg) |
paul@160 | 527 | { |
paul@160 | 528 | // Test for PLL enable and not PLL bypass. |
paul@160 | 529 | |
paul@160 | 530 | if (pll_enabled(pll_reg) && !pll_bypassed(pll_reg)) |
paul@160 | 531 | return (_exclk_freq * get_multiplier(pll_reg)) / |
paul@160 | 532 | (get_input_division(pll_reg) * get_output_division(pll_reg)); |
paul@160 | 533 | else |
paul@160 | 534 | return _exclk_freq; |
paul@160 | 535 | } |
paul@160 | 536 | |
paul@160 | 537 | void |
paul@160 | 538 | Cpm_x1600_chip::set_pll_parameters(uint32_t pll_reg, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@160 | 539 | { |
paul@160 | 540 | set_multiplier(pll_reg, multiplier); |
paul@160 | 541 | set_input_division(pll_reg, in_divider); |
paul@160 | 542 | set_output_division(pll_reg, out_divider); |
paul@160 | 543 | |
paul@160 | 544 | if (pll_enabled(pll_reg) && !pll_bypassed(pll_reg)) |
paul@160 | 545 | while (!have_pll(pll_reg)); |
paul@160 | 546 | } |
paul@160 | 547 | |
paul@160 | 548 | |
paul@160 | 549 | |
paul@160 | 550 | // CPU clock (CCLK) divider. |
paul@160 | 551 | |
paul@160 | 552 | uint8_t |
paul@160 | 553 | Cpm_x1600_chip::get_cpu_divider() |
paul@160 | 554 | { |
paul@160 | 555 | return _get_divider(Clock_control, 0xf, Clock_cpu_divider); |
paul@160 | 556 | } |
paul@160 | 557 | |
paul@160 | 558 | // Fast peripheral clock (H0CLK) divider. |
paul@160 | 559 | |
paul@160 | 560 | uint8_t |
paul@160 | 561 | Cpm_x1600_chip::get_hclock0_divider() |
paul@160 | 562 | { |
paul@160 | 563 | return _get_divider(Clock_control, 0xf, Clock_hclock0_divider); |
paul@160 | 564 | } |
paul@160 | 565 | |
paul@160 | 566 | // Fast peripheral clock (H2CLK) divider. |
paul@160 | 567 | |
paul@160 | 568 | uint8_t |
paul@160 | 569 | Cpm_x1600_chip::get_hclock2_divider() |
paul@160 | 570 | { |
paul@160 | 571 | return _get_divider(Clock_control, 0xf, Clock_hclock2_divider); |
paul@160 | 572 | } |
paul@160 | 573 | |
paul@160 | 574 | // Slow peripheral clock (PCLK) divider. |
paul@160 | 575 | |
paul@160 | 576 | uint8_t |
paul@160 | 577 | Cpm_x1600_chip::get_pclock_divider() |
paul@160 | 578 | { |
paul@160 | 579 | return _get_divider(Clock_control, 0xf, Clock_pclock_divider); |
paul@160 | 580 | } |
paul@160 | 581 | |
paul@160 | 582 | // LCD clock (LPCLK) divider for LCD pixel clock. |
paul@160 | 583 | |
paul@160 | 584 | uint8_t |
paul@160 | 585 | Cpm_x1600_chip::get_lcd_pixel_divider(uint8_t controller) |
paul@160 | 586 | { |
paul@160 | 587 | (void) controller; |
paul@160 | 588 | return _get_divider(Lcd_divider, 0xff, Lcd_divider_value); |
paul@160 | 589 | } |
paul@160 | 590 | |
paul@160 | 591 | // Memory clock (DDR_CLK) divider. |
paul@160 | 592 | |
paul@160 | 593 | uint8_t |
paul@160 | 594 | Cpm_x1600_chip::get_memory_divider() |
paul@160 | 595 | { |
paul@160 | 596 | return _get_divider(Ddr_divider, 0xf, Ddr_divider_value); |
paul@160 | 597 | } |
paul@160 | 598 | |
paul@160 | 599 | // LCD pixel clock divider. |
paul@160 | 600 | |
paul@160 | 601 | void |
paul@160 | 602 | Cpm_x1600_chip::set_lcd_pixel_divider(uint8_t controller, uint16_t division) |
paul@160 | 603 | { |
paul@160 | 604 | if (controller > 0) |
paul@160 | 605 | return; |
paul@160 | 606 | |
paul@160 | 607 | if ((division < 1) || (division > 256)) |
paul@160 | 608 | return; |
paul@160 | 609 | |
paul@160 | 610 | // Enable change. |
paul@160 | 611 | |
paul@160 | 612 | _regs[Lcd_divider] = _regs[Lcd_divider] | Lcd_change_enable; |
paul@160 | 613 | |
paul@160 | 614 | // Set the divider. |
paul@160 | 615 | |
paul@160 | 616 | set_field(Lcd_divider, 0xff, Lcd_divider_value, division - 1); |
paul@160 | 617 | |
paul@160 | 618 | // Restart clock and disable change. |
paul@160 | 619 | |
paul@160 | 620 | while (_regs[Lcd_divider] & Lcd_change_busy); |
paul@160 | 621 | _regs[Lcd_divider] = _regs[Lcd_divider] & ~Lcd_change_enable; |
paul@160 | 622 | } |
paul@160 | 623 | |
paul@160 | 624 | |
paul@160 | 625 | |
paul@160 | 626 | // Clock sources. |
paul@160 | 627 | |
paul@160 | 628 | uint8_t |
paul@160 | 629 | Cpm_x1600_chip::get_memory_source() |
paul@160 | 630 | { |
paul@160 | 631 | return get_field(Ddr_divider, 0x3, Clock_source_ddr); |
paul@160 | 632 | } |
paul@160 | 633 | |
paul@160 | 634 | uint32_t |
paul@160 | 635 | Cpm_x1600_chip::get_memory_source_frequency() |
paul@160 | 636 | { |
paul@160 | 637 | switch (get_memory_source()) |
paul@160 | 638 | { |
paul@160 | 639 | case Source_mux_main: |
paul@160 | 640 | return get_main_frequency(); |
paul@160 | 641 | case Source_mux_pll_M: |
paul@160 | 642 | return get_pll_frequency(Pll_control_M); |
paul@160 | 643 | default: |
paul@160 | 644 | return 0; |
paul@160 | 645 | } |
paul@160 | 646 | } |
paul@160 | 647 | |
paul@160 | 648 | uint8_t |
paul@160 | 649 | Cpm_x1600_chip::get_cpu_source() |
paul@160 | 650 | { |
paul@160 | 651 | return get_field(Clock_control, 0x3, Clock_source_cpu); |
paul@160 | 652 | } |
paul@160 | 653 | |
paul@160 | 654 | uint32_t |
paul@160 | 655 | Cpm_x1600_chip::get_cpu_source_frequency() |
paul@160 | 656 | { |
paul@160 | 657 | switch (get_cpu_source()) |
paul@160 | 658 | { |
paul@160 | 659 | case Source_mux_main: |
paul@160 | 660 | return get_main_frequency(); |
paul@160 | 661 | case Source_mux_pll_M: |
paul@160 | 662 | return get_pll_frequency(Pll_control_M); |
paul@160 | 663 | default: |
paul@160 | 664 | return 0; |
paul@160 | 665 | } |
paul@160 | 666 | } |
paul@160 | 667 | |
paul@160 | 668 | uint8_t |
paul@160 | 669 | Cpm_x1600_chip::get_hclock0_source() |
paul@160 | 670 | { |
paul@160 | 671 | return get_field(Clock_control, 0x3, Clock_source_hclock0); |
paul@160 | 672 | } |
paul@160 | 673 | |
paul@160 | 674 | uint32_t |
paul@160 | 675 | Cpm_x1600_chip::get_hclock0_source_frequency() |
paul@160 | 676 | { |
paul@160 | 677 | switch (get_hclock0_source()) |
paul@160 | 678 | { |
paul@160 | 679 | case Source_mux_main: |
paul@160 | 680 | return get_main_frequency(); |
paul@160 | 681 | case Source_mux_pll_M: |
paul@160 | 682 | return get_pll_frequency(Pll_control_M); |
paul@160 | 683 | default: |
paul@160 | 684 | return 0; |
paul@160 | 685 | } |
paul@160 | 686 | } |
paul@160 | 687 | |
paul@160 | 688 | uint8_t |
paul@160 | 689 | Cpm_x1600_chip::get_hclock2_source() |
paul@160 | 690 | { |
paul@160 | 691 | return get_field(Clock_control, 0x3, Clock_source_hclock2); |
paul@160 | 692 | } |
paul@160 | 693 | |
paul@160 | 694 | uint32_t |
paul@160 | 695 | Cpm_x1600_chip::get_hclock2_source_frequency() |
paul@160 | 696 | { |
paul@160 | 697 | switch (get_hclock2_source()) |
paul@160 | 698 | { |
paul@160 | 699 | case Source_mux_main: |
paul@160 | 700 | return get_main_frequency(); |
paul@160 | 701 | case Source_mux_pll_M: |
paul@160 | 702 | return get_pll_frequency(Pll_control_M); |
paul@160 | 703 | default: |
paul@160 | 704 | return 0; |
paul@160 | 705 | } |
paul@160 | 706 | } |
paul@160 | 707 | |
paul@160 | 708 | void |
paul@160 | 709 | Cpm_x1600_chip::set_hclock2_source(uint8_t source) |
paul@160 | 710 | { |
paul@160 | 711 | set_field(Clock_control, 0x3, Clock_source_hclock2, source); |
paul@160 | 712 | } |
paul@160 | 713 | |
paul@160 | 714 | uint8_t |
paul@160 | 715 | Cpm_x1600_chip::get_lcd_source(uint8_t controller) |
paul@160 | 716 | { |
paul@160 | 717 | (void) controller; |
paul@160 | 718 | return get_field(Lcd_divider, 0x3, Clock_source_lcd); |
paul@160 | 719 | } |
paul@160 | 720 | |
paul@160 | 721 | uint32_t |
paul@160 | 722 | Cpm_x1600_chip::get_lcd_source_frequency(uint8_t controller) |
paul@160 | 723 | { |
paul@160 | 724 | switch (get_lcd_source(controller)) |
paul@160 | 725 | { |
paul@160 | 726 | case Source_main: |
paul@160 | 727 | return get_main_frequency(); |
paul@160 | 728 | case Source_pll_M: |
paul@160 | 729 | return get_pll_frequency(Pll_control_M); |
paul@160 | 730 | case Source_pll_E: |
paul@160 | 731 | return get_pll_frequency(Pll_control_E); |
paul@160 | 732 | default: |
paul@160 | 733 | return 0; |
paul@160 | 734 | } |
paul@160 | 735 | } |
paul@160 | 736 | |
paul@160 | 737 | void |
paul@160 | 738 | Cpm_x1600_chip::set_lcd_source(uint8_t controller, uint8_t source) |
paul@160 | 739 | { |
paul@160 | 740 | if (controller > 0) |
paul@160 | 741 | return; |
paul@160 | 742 | |
paul@160 | 743 | // Stop clock and enable change. |
paul@160 | 744 | |
paul@160 | 745 | _regs[Lcd_divider] = _regs[Lcd_divider] | Lcd_change_enable | Lcd_clock_stop; |
paul@160 | 746 | |
paul@160 | 747 | // Set the source. |
paul@160 | 748 | |
paul@160 | 749 | set_field(Lcd_divider, 0x03, Clock_source_lcd, source); |
paul@160 | 750 | |
paul@160 | 751 | // Restart clock and disable change. |
paul@160 | 752 | |
paul@160 | 753 | while (_regs[Lcd_divider] & Lcd_change_busy); |
paul@160 | 754 | _regs[Lcd_divider] = _regs[Lcd_divider] & ~(Lcd_change_enable | Lcd_clock_stop); |
paul@160 | 755 | } |
paul@160 | 756 | |
paul@160 | 757 | uint8_t |
paul@160 | 758 | Cpm_x1600_chip::get_pclock_source() |
paul@160 | 759 | { |
paul@160 | 760 | return get_hclock2_source(); |
paul@160 | 761 | } |
paul@160 | 762 | |
paul@160 | 763 | uint32_t |
paul@160 | 764 | Cpm_x1600_chip::get_pclock_source_frequency() |
paul@160 | 765 | { |
paul@160 | 766 | return get_hclock2_source_frequency(); |
paul@160 | 767 | } |
paul@160 | 768 | |
paul@160 | 769 | void |
paul@160 | 770 | Cpm_x1600_chip::set_pclock_source(uint8_t source) |
paul@160 | 771 | { |
paul@160 | 772 | set_hclock2_source(source); |
paul@160 | 773 | } |
paul@160 | 774 | |
paul@160 | 775 | |
paul@160 | 776 | |
paul@160 | 777 | // Source frequency, used by various clock sources. |
paul@160 | 778 | |
paul@160 | 779 | uint8_t |
paul@160 | 780 | Cpm_x1600_chip::get_main_source() |
paul@160 | 781 | { |
paul@160 | 782 | return get_field(Clock_control, 0x3, Clock_source_main); |
paul@160 | 783 | } |
paul@160 | 784 | |
paul@160 | 785 | uint32_t |
paul@160 | 786 | Cpm_x1600_chip::get_main_frequency() |
paul@160 | 787 | { |
paul@160 | 788 | switch (get_main_source()) |
paul@160 | 789 | { |
paul@160 | 790 | case Source_pll_A: |
paul@160 | 791 | return get_pll_frequency(Pll_control_A); |
paul@160 | 792 | case Source_external: |
paul@160 | 793 | return _exclk_freq; |
paul@160 | 794 | default: |
paul@160 | 795 | return 0; |
paul@160 | 796 | } |
paul@160 | 797 | } |
paul@160 | 798 | |
paul@160 | 799 | // Clock frequency for the CPU. |
paul@160 | 800 | |
paul@160 | 801 | uint32_t |
paul@160 | 802 | Cpm_x1600_chip::get_cpu_frequency() |
paul@160 | 803 | { |
paul@160 | 804 | return get_cpu_source_frequency() / get_cpu_divider(); |
paul@160 | 805 | } |
paul@160 | 806 | |
paul@160 | 807 | // Clock frequency for fast peripherals. |
paul@160 | 808 | |
paul@160 | 809 | uint32_t |
paul@160 | 810 | Cpm_x1600_chip::get_hclock0_frequency() |
paul@160 | 811 | { |
paul@160 | 812 | return get_hclock0_source_frequency() / get_hclock0_divider(); |
paul@160 | 813 | } |
paul@160 | 814 | |
paul@160 | 815 | // Clock frequency for fast peripherals. |
paul@160 | 816 | |
paul@160 | 817 | uint32_t |
paul@160 | 818 | Cpm_x1600_chip::get_hclock2_frequency() |
paul@160 | 819 | { |
paul@160 | 820 | return get_hclock2_source_frequency() / get_hclock2_divider(); |
paul@160 | 821 | } |
paul@160 | 822 | |
paul@160 | 823 | // Clock frequency for slow peripherals. |
paul@160 | 824 | |
paul@160 | 825 | uint32_t |
paul@160 | 826 | Cpm_x1600_chip::get_pclock_frequency() |
paul@160 | 827 | { |
paul@160 | 828 | return get_pclock_source_frequency() / get_pclock_divider(); |
paul@160 | 829 | } |
paul@160 | 830 | |
paul@160 | 831 | // Clock frequency for the memory. |
paul@160 | 832 | |
paul@160 | 833 | uint32_t |
paul@160 | 834 | Cpm_x1600_chip::get_memory_frequency() |
paul@160 | 835 | { |
paul@160 | 836 | return get_memory_source_frequency() / get_memory_divider(); |
paul@160 | 837 | } |
paul@160 | 838 | |
paul@160 | 839 | uint32_t |
paul@160 | 840 | Cpm_x1600_chip::get_apll_frequency() |
paul@160 | 841 | { |
paul@160 | 842 | return get_pll_frequency(Pll_control_A); |
paul@160 | 843 | } |
paul@160 | 844 | |
paul@160 | 845 | uint32_t |
paul@160 | 846 | Cpm_x1600_chip::get_epll_frequency() |
paul@160 | 847 | { |
paul@160 | 848 | return get_pll_frequency(Pll_control_E); |
paul@160 | 849 | } |
paul@160 | 850 | |
paul@160 | 851 | uint32_t |
paul@160 | 852 | Cpm_x1600_chip::get_mpll_frequency() |
paul@160 | 853 | { |
paul@160 | 854 | return get_pll_frequency(Pll_control_M); |
paul@160 | 855 | } |
paul@160 | 856 | |
paul@160 | 857 | |
paul@160 | 858 | |
paul@160 | 859 | uint32_t |
paul@160 | 860 | Cpm_x1600_chip::get_frequency(enum Clock_identifiers clock) |
paul@160 | 861 | { |
paul@160 | 862 | switch (clock) |
paul@160 | 863 | { |
paul@160 | 864 | // NOTE: Returning only the frequency for controller 0. |
paul@160 | 865 | |
paul@160 | 866 | case Clock_lcd_pixel: |
paul@160 | 867 | return get_lcd_source_frequency(0) / get_lcd_pixel_divider(0); |
paul@160 | 868 | |
paul@160 | 869 | // NOTE: Consider a better error result. |
paul@160 | 870 | |
paul@160 | 871 | default: |
paul@160 | 872 | return 0; |
paul@160 | 873 | } |
paul@160 | 874 | } |
paul@160 | 875 | |
paul@160 | 876 | void |
paul@160 | 877 | Cpm_x1600_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 878 | { |
paul@160 | 879 | switch (clock) |
paul@160 | 880 | { |
paul@160 | 881 | // The pixel frequency is based on the selected clock source (SCLK_A, MPLL or |
paul@160 | 882 | // EPLL). |
paul@160 | 883 | |
paul@160 | 884 | case Clock_lcd_pixel: |
paul@160 | 885 | |
paul@160 | 886 | // Switch to the MPLL and attempt to set the divider. |
paul@160 | 887 | |
paul@160 | 888 | set_lcd_source(0, Source_pll_M); |
paul@160 | 889 | pll_enable(Pll_control_M); |
paul@160 | 890 | set_lcd_pixel_divider(0, get_lcd_source_frequency() / frequency); |
paul@160 | 891 | break; |
paul@160 | 892 | |
paul@160 | 893 | default: |
paul@160 | 894 | break; |
paul@160 | 895 | } |
paul@160 | 896 | } |
paul@160 | 897 | |
paul@160 | 898 | |
paul@160 | 899 | |
paul@160 | 900 | // C language interface functions. |
paul@160 | 901 | |
paul@160 | 902 | void |
paul@160 | 903 | *x1600_cpm_init(l4_addr_t cpm_base) |
paul@160 | 904 | { |
paul@160 | 905 | /* Initialise the clock and power management peripheral with the |
paul@160 | 906 | register memory region and a 24MHz EXCLK frequency. */ |
paul@160 | 907 | |
paul@160 | 908 | return (void *) new Cpm_x1600_chip(cpm_base, 24000000); |
paul@160 | 909 | } |
paul@160 | 910 | |
paul@160 | 911 | int |
paul@160 | 912 | x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 913 | { |
paul@160 | 914 | return static_cast<Cpm_x1600_chip *>(cpm)->have_clock(clock); |
paul@160 | 915 | } |
paul@160 | 916 | |
paul@160 | 917 | void |
paul@160 | 918 | x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 919 | { |
paul@160 | 920 | static_cast<Cpm_x1600_chip *>(cpm)->start_clock(clock); |
paul@160 | 921 | } |
paul@160 | 922 | |
paul@160 | 923 | void |
paul@160 | 924 | x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 925 | { |
paul@160 | 926 | static_cast<Cpm_x1600_chip *>(cpm)->stop_clock(clock); |
paul@160 | 927 | } |
paul@160 | 928 | |
paul@160 | 929 | |
paul@160 | 930 | |
paul@160 | 931 | uint8_t |
paul@160 | 932 | x1600_cpm_get_cpu_divider(void *cpm) |
paul@160 | 933 | { |
paul@160 | 934 | return static_cast<Cpm_x1600_chip *>(cpm)->get_cpu_divider(); |
paul@160 | 935 | } |
paul@160 | 936 | |
paul@160 | 937 | uint8_t |
paul@160 | 938 | x1600_cpm_get_hclock0_divider(void *cpm) |
paul@160 | 939 | { |
paul@160 | 940 | return static_cast<Cpm_x1600_chip *>(cpm)->get_hclock0_divider(); |
paul@160 | 941 | } |
paul@160 | 942 | |
paul@160 | 943 | uint8_t |
paul@160 | 944 | x1600_cpm_get_hclock2_divider(void *cpm) |
paul@160 | 945 | { |
paul@160 | 946 | return static_cast<Cpm_x1600_chip *>(cpm)->get_hclock2_divider(); |
paul@160 | 947 | } |
paul@160 | 948 | |
paul@160 | 949 | uint8_t |
paul@160 | 950 | x1600_cpm_get_lcd_pixel_divider(void *cpm) |
paul@160 | 951 | { |
paul@160 | 952 | return static_cast<Cpm_x1600_chip *>(cpm)->get_lcd_pixel_divider(); |
paul@160 | 953 | } |
paul@160 | 954 | |
paul@160 | 955 | uint8_t |
paul@160 | 956 | x1600_cpm_get_memory_divider(void *cpm) |
paul@160 | 957 | { |
paul@160 | 958 | return static_cast<Cpm_x1600_chip *>(cpm)->get_memory_divider(); |
paul@160 | 959 | } |
paul@160 | 960 | |
paul@160 | 961 | uint8_t |
paul@160 | 962 | x1600_cpm_get_pclock_divider(void *cpm) |
paul@160 | 963 | { |
paul@160 | 964 | return static_cast<Cpm_x1600_chip *>(cpm)->get_pclock_divider(); |
paul@160 | 965 | } |
paul@160 | 966 | |
paul@160 | 967 | |
paul@160 | 968 | |
paul@160 | 969 | uint8_t |
paul@160 | 970 | x1600_cpm_get_hclock0_source(void *cpm) |
paul@160 | 971 | { |
paul@160 | 972 | return static_cast<Cpm_x1600_chip *>(cpm)->get_hclock0_source(); |
paul@160 | 973 | } |
paul@160 | 974 | |
paul@160 | 975 | uint8_t |
paul@160 | 976 | x1600_cpm_get_hclock2_source(void *cpm) |
paul@160 | 977 | { |
paul@160 | 978 | return static_cast<Cpm_x1600_chip *>(cpm)->get_hclock2_source(); |
paul@160 | 979 | } |
paul@160 | 980 | |
paul@160 | 981 | uint8_t |
paul@160 | 982 | x1600_cpm_get_lcd_source(void *cpm) |
paul@160 | 983 | { |
paul@160 | 984 | return static_cast<Cpm_x1600_chip *>(cpm)->get_lcd_source(); |
paul@160 | 985 | } |
paul@160 | 986 | |
paul@160 | 987 | uint8_t |
paul@160 | 988 | x1600_cpm_get_memory_source(void *cpm) |
paul@160 | 989 | { |
paul@160 | 990 | return static_cast<Cpm_x1600_chip *>(cpm)->get_memory_source(); |
paul@160 | 991 | } |
paul@160 | 992 | |
paul@160 | 993 | uint8_t |
paul@160 | 994 | x1600_cpm_get_pclock_source(void *cpm) |
paul@160 | 995 | { |
paul@160 | 996 | return static_cast<Cpm_x1600_chip *>(cpm)->get_pclock_source(); |
paul@160 | 997 | } |
paul@160 | 998 | |
paul@160 | 999 | void |
paul@160 | 1000 | x1600_cpm_set_pclock_source(void *cpm, uint8_t source) |
paul@160 | 1001 | { |
paul@160 | 1002 | static_cast<Cpm_x1600_chip *>(cpm)->set_pclock_source(source); |
paul@160 | 1003 | } |
paul@160 | 1004 | |
paul@160 | 1005 | |
paul@160 | 1006 | |
paul@160 | 1007 | uint32_t |
paul@160 | 1008 | x1600_cpm_get_hclock0_source_frequency(void *cpm) |
paul@160 | 1009 | { |
paul@160 | 1010 | return static_cast<Cpm_x1600_chip *>(cpm)->get_hclock0_source_frequency(); |
paul@160 | 1011 | } |
paul@160 | 1012 | |
paul@160 | 1013 | uint32_t |
paul@160 | 1014 | x1600_cpm_get_hclock2_source_frequency(void *cpm) |
paul@160 | 1015 | { |
paul@160 | 1016 | return static_cast<Cpm_x1600_chip *>(cpm)->get_hclock2_source_frequency(); |
paul@160 | 1017 | } |
paul@160 | 1018 | |
paul@160 | 1019 | uint32_t |
paul@160 | 1020 | x1600_cpm_get_lcd_source_frequency(void *cpm) |
paul@160 | 1021 | { |
paul@160 | 1022 | return static_cast<Cpm_x1600_chip *>(cpm)->get_lcd_source_frequency(); |
paul@160 | 1023 | } |
paul@160 | 1024 | |
paul@160 | 1025 | uint32_t |
paul@160 | 1026 | x1600_cpm_get_memory_source_frequency(void *cpm) |
paul@160 | 1027 | { |
paul@160 | 1028 | return static_cast<Cpm_x1600_chip *>(cpm)->get_memory_source_frequency(); |
paul@160 | 1029 | } |
paul@160 | 1030 | |
paul@160 | 1031 | uint32_t |
paul@160 | 1032 | x1600_cpm_get_pclock_source_frequency(void *cpm) |
paul@160 | 1033 | { |
paul@160 | 1034 | return static_cast<Cpm_x1600_chip *>(cpm)->get_pclock_source_frequency(); |
paul@160 | 1035 | } |
paul@160 | 1036 | |
paul@160 | 1037 | |
paul@160 | 1038 | |
paul@160 | 1039 | uint8_t |
paul@160 | 1040 | x1600_cpm_get_main_source(void *cpm) |
paul@160 | 1041 | { |
paul@160 | 1042 | return static_cast<Cpm_x1600_chip *>(cpm)->get_main_source(); |
paul@160 | 1043 | } |
paul@160 | 1044 | |
paul@160 | 1045 | uint32_t |
paul@160 | 1046 | x1600_cpm_get_main_frequency(void *cpm) |
paul@160 | 1047 | { |
paul@160 | 1048 | return static_cast<Cpm_x1600_chip *>(cpm)->get_main_frequency(); |
paul@160 | 1049 | } |
paul@160 | 1050 | |
paul@160 | 1051 | uint32_t |
paul@160 | 1052 | x1600_cpm_get_cpu_frequency(void *cpm) |
paul@160 | 1053 | { |
paul@160 | 1054 | return static_cast<Cpm_x1600_chip *>(cpm)->get_cpu_frequency(); |
paul@160 | 1055 | } |
paul@160 | 1056 | |
paul@160 | 1057 | uint32_t |
paul@160 | 1058 | x1600_cpm_get_hclock0_frequency(void *cpm) |
paul@160 | 1059 | { |
paul@160 | 1060 | return static_cast<Cpm_x1600_chip *>(cpm)->get_hclock0_frequency(); |
paul@160 | 1061 | } |
paul@160 | 1062 | |
paul@160 | 1063 | uint32_t |
paul@160 | 1064 | x1600_cpm_get_hclock2_frequency(void *cpm) |
paul@160 | 1065 | { |
paul@160 | 1066 | return static_cast<Cpm_x1600_chip *>(cpm)->get_hclock2_frequency(); |
paul@160 | 1067 | } |
paul@160 | 1068 | |
paul@160 | 1069 | uint32_t |
paul@160 | 1070 | x1600_cpm_get_memory_frequency(void *cpm) |
paul@160 | 1071 | { |
paul@160 | 1072 | return static_cast<Cpm_x1600_chip *>(cpm)->get_memory_frequency(); |
paul@160 | 1073 | } |
paul@160 | 1074 | |
paul@160 | 1075 | uint32_t |
paul@160 | 1076 | x1600_cpm_get_pclock_frequency(void *cpm) |
paul@160 | 1077 | { |
paul@160 | 1078 | return static_cast<Cpm_x1600_chip *>(cpm)->get_pclock_frequency(); |
paul@160 | 1079 | } |
paul@160 | 1080 | |
paul@160 | 1081 | uint32_t |
paul@160 | 1082 | x1600_cpm_get_apll_frequency(void *cpm) |
paul@160 | 1083 | { |
paul@160 | 1084 | return static_cast<Cpm_x1600_chip *>(cpm)->get_apll_frequency(); |
paul@160 | 1085 | } |
paul@160 | 1086 | |
paul@160 | 1087 | uint32_t |
paul@160 | 1088 | x1600_cpm_get_epll_frequency(void *cpm) |
paul@160 | 1089 | { |
paul@160 | 1090 | return static_cast<Cpm_x1600_chip *>(cpm)->get_epll_frequency(); |
paul@160 | 1091 | } |
paul@160 | 1092 | |
paul@160 | 1093 | uint32_t |
paul@160 | 1094 | x1600_cpm_get_mpll_frequency(void *cpm) |
paul@160 | 1095 | { |
paul@160 | 1096 | return static_cast<Cpm_x1600_chip *>(cpm)->get_mpll_frequency(); |
paul@160 | 1097 | } |
paul@160 | 1098 | |
paul@160 | 1099 | |
paul@160 | 1100 | |
paul@160 | 1101 | uint32_t |
paul@160 | 1102 | x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1103 | { |
paul@160 | 1104 | return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock); |
paul@160 | 1105 | } |
paul@160 | 1106 | |
paul@160 | 1107 | void |
paul@160 | 1108 | x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 1109 | { |
paul@160 | 1110 | static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency); |
paul@160 | 1111 | } |
paul@160 | 1112 | |
paul@160 | 1113 | void |
paul@160 | 1114 | x1600_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@160 | 1115 | { |
paul@160 | 1116 | static_cast<Cpm_x1600_chip *>(cpm)->set_pll_parameters(Pll_control_M, multiplier, in_divider, out_divider); |
paul@160 | 1117 | } |