paul@173 | 1 | /* |
paul@173 | 2 | * Common clock functionality. |
paul@173 | 3 | * |
paul@173 | 4 | * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> |
paul@173 | 5 | * |
paul@173 | 6 | * This program is free software; you can redistribute it and/or |
paul@173 | 7 | * modify it under the terms of the GNU General Public License as |
paul@173 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@173 | 9 | * the License, or (at your option) any later version. |
paul@173 | 10 | * |
paul@173 | 11 | * This program is distributed in the hope that it will be useful, |
paul@173 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@173 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@173 | 14 | * GNU General Public License for more details. |
paul@173 | 15 | * |
paul@173 | 16 | * You should have received a copy of the GNU General Public License |
paul@173 | 17 | * along with this program; if not, write to the Free Software |
paul@173 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@173 | 19 | * Boston, MA 02110-1301, USA |
paul@173 | 20 | */ |
paul@173 | 21 | |
paul@173 | 22 | #include <l4/devices/hw_mmio_register_block.h> |
paul@173 | 23 | |
paul@173 | 24 | #include "cpm-common.h" |
paul@173 | 25 | #include <math.h> |
paul@173 | 26 | |
paul@173 | 27 | |
paul@173 | 28 | |
paul@173 | 29 | // Register access. |
paul@173 | 30 | |
paul@173 | 31 | Cpm_regs::Cpm_regs(l4_addr_t addr, Clock_base *clocks[], |
paul@173 | 32 | uint32_t exclk_freq) |
paul@173 | 33 | : _clocks(clocks), exclk_freq(exclk_freq) |
paul@173 | 34 | { |
paul@173 | 35 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@173 | 36 | } |
paul@173 | 37 | |
paul@173 | 38 | // Utility methods. |
paul@173 | 39 | |
paul@173 | 40 | uint32_t |
paul@173 | 41 | Cpm_regs::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@173 | 42 | { |
paul@173 | 43 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@173 | 44 | } |
paul@173 | 45 | |
paul@173 | 46 | void |
paul@173 | 47 | Cpm_regs::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@173 | 48 | { |
paul@173 | 49 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@173 | 50 | } |
paul@173 | 51 | |
paul@173 | 52 | Clock_base * |
paul@173 | 53 | Cpm_regs::get_clock(int num) |
paul@173 | 54 | { |
paul@173 | 55 | return _clocks[num]; |
paul@173 | 56 | } |
paul@173 | 57 | |
paul@173 | 58 | |
paul@173 | 59 | |
paul@173 | 60 | // Field methods. |
paul@173 | 61 | |
paul@173 | 62 | uint32_t |
paul@173 | 63 | Field::get_field(Cpm_regs ®s) |
paul@173 | 64 | { |
paul@173 | 65 | if (defined) |
paul@173 | 66 | return regs.get_field(reg, mask, bit); |
paul@173 | 67 | else |
paul@173 | 68 | return 0; |
paul@173 | 69 | } |
paul@173 | 70 | |
paul@173 | 71 | void |
paul@173 | 72 | Field::set_field(Cpm_regs ®s, uint32_t value) |
paul@173 | 73 | { |
paul@173 | 74 | if (defined) |
paul@173 | 75 | regs.set_field(reg, mask, bit, value); |
paul@173 | 76 | } |
paul@173 | 77 | |
paul@173 | 78 | // Undefined field. |
paul@173 | 79 | |
paul@173 | 80 | Field Field::undefined; |
paul@173 | 81 | |
paul@173 | 82 | |
paul@173 | 83 | |
paul@173 | 84 | // Clock sources. |
paul@173 | 85 | |
paul@173 | 86 | enum Clock_identifiers |
paul@173 | 87 | Mux::get_input(int num) |
paul@173 | 88 | { |
paul@173 | 89 | if (num < _num_inputs) |
paul@173 | 90 | return _inputs[num]; |
paul@173 | 91 | else |
paul@173 | 92 | return Clock_undefined; |
paul@173 | 93 | } |
paul@173 | 94 | |
paul@173 | 95 | // Clock sources. |
paul@173 | 96 | |
paul@173 | 97 | uint8_t |
paul@173 | 98 | Source::get_source(Cpm_regs ®s) |
paul@173 | 99 | { |
paul@173 | 100 | if (_source.is_defined()) |
paul@173 | 101 | return _source.get_field(regs); |
paul@173 | 102 | else |
paul@173 | 103 | return 0; |
paul@173 | 104 | } |
paul@173 | 105 | |
paul@173 | 106 | void |
paul@173 | 107 | Source::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 108 | { |
paul@173 | 109 | if (!_source.is_defined()) |
paul@173 | 110 | return; |
paul@173 | 111 | |
paul@173 | 112 | _source.set_field(regs, source); |
paul@173 | 113 | } |
paul@173 | 114 | |
paul@173 | 115 | // Clock source frequencies. |
paul@173 | 116 | |
paul@173 | 117 | uint32_t |
paul@173 | 118 | Source::get_frequency(Cpm_regs ®s) |
paul@173 | 119 | { |
paul@173 | 120 | // Return the external clock frequency without any input clock. |
paul@173 | 121 | |
paul@173 | 122 | if (get_number() == 0) |
paul@173 | 123 | return regs.exclk_freq; |
paul@173 | 124 | |
paul@173 | 125 | // Clocks with one source yield that input frequency. |
paul@173 | 126 | |
paul@173 | 127 | else if (get_number() == 1) |
paul@173 | 128 | return regs.get_clock(get_input(0))->get_frequency(regs); |
paul@173 | 129 | |
paul@173 | 130 | // With multiple sources, obtain the selected source for the clock. |
paul@173 | 131 | |
paul@173 | 132 | uint8_t source = get_source(regs); |
paul@173 | 133 | enum Clock_identifiers input = get_input(source); |
paul@173 | 134 | |
paul@173 | 135 | // Return the frequency of the source. |
paul@173 | 136 | |
paul@173 | 137 | if (input != Clock_undefined) |
paul@173 | 138 | return regs.get_clock(input)->get_frequency(regs); |
paul@173 | 139 | else |
paul@173 | 140 | return 0; |
paul@173 | 141 | } |
paul@173 | 142 | |
paul@173 | 143 | // Undefined source. |
paul@173 | 144 | |
paul@173 | 145 | Source Source::undefined; |
paul@173 | 146 | |
paul@173 | 147 | |
paul@173 | 148 | |
paul@174 | 149 | // Clock dividers. |
paul@174 | 150 | |
paul@174 | 151 | uint32_t |
paul@174 | 152 | Divider::get_divider(Cpm_regs ®s) |
paul@174 | 153 | { |
paul@174 | 154 | if (_divider.is_defined()) |
paul@174 | 155 | return _divider.get_field(regs) + 1; |
paul@174 | 156 | else |
paul@174 | 157 | return 1; |
paul@174 | 158 | } |
paul@174 | 159 | |
paul@174 | 160 | void |
paul@174 | 161 | Divider::set_divider(Cpm_regs ®s, uint32_t division) |
paul@174 | 162 | { |
paul@174 | 163 | if (_divider.is_defined()) |
paul@174 | 164 | _divider.set_field(regs, division - 1); |
paul@174 | 165 | } |
paul@174 | 166 | |
paul@174 | 167 | // Output clock frequencies. |
paul@174 | 168 | |
paul@174 | 169 | uint32_t |
paul@174 | 170 | Divider::get_frequency(Cpm_regs ®s, uint32_t source_frequency) |
paul@174 | 171 | { |
paul@174 | 172 | return source_frequency / get_divider(regs); |
paul@174 | 173 | } |
paul@174 | 174 | |
paul@174 | 175 | // Undefined divider. |
paul@174 | 176 | |
paul@174 | 177 | Divider Divider::undefined; |
paul@174 | 178 | |
paul@174 | 179 | |
paul@174 | 180 | |
paul@174 | 181 | // Feedback (13-bit) multiplier. |
paul@174 | 182 | |
paul@174 | 183 | uint16_t |
paul@174 | 184 | Divider_pll::get_multiplier(Cpm_regs ®s) |
paul@174 | 185 | { |
paul@174 | 186 | return _multiplier.get_field(regs) + 1; |
paul@174 | 187 | } |
paul@174 | 188 | |
paul@174 | 189 | void |
paul@174 | 190 | Divider_pll::set_multiplier(Cpm_regs ®s, uint16_t multiplier) |
paul@174 | 191 | { |
paul@174 | 192 | _multiplier.set_field(regs, multiplier - 1); |
paul@174 | 193 | } |
paul@174 | 194 | |
paul@174 | 195 | // Input (6-bit) divider. |
paul@174 | 196 | |
paul@174 | 197 | uint8_t |
paul@174 | 198 | Divider_pll::get_input_division(Cpm_regs ®s) |
paul@174 | 199 | { |
paul@174 | 200 | return _input_division.get_field(regs) + 1; |
paul@174 | 201 | } |
paul@174 | 202 | |
paul@174 | 203 | void |
paul@174 | 204 | Divider_pll::set_input_division(Cpm_regs ®s, uint8_t divider) |
paul@174 | 205 | { |
paul@174 | 206 | _input_division.set_field(regs, divider - 1); |
paul@174 | 207 | } |
paul@174 | 208 | |
paul@174 | 209 | // Output (dual 3-bit) dividers. |
paul@174 | 210 | |
paul@174 | 211 | uint8_t |
paul@174 | 212 | Divider_pll::get_output_division(Cpm_regs ®s) |
paul@174 | 213 | { |
paul@174 | 214 | uint8_t d0 = _output_division0.get_field(regs); |
paul@174 | 215 | uint8_t d1 = _output_division1.get_field(regs); |
paul@174 | 216 | |
paul@174 | 217 | return d0 * d1; |
paul@174 | 218 | } |
paul@174 | 219 | |
paul@174 | 220 | void |
paul@174 | 221 | Divider_pll::set_output_division(Cpm_regs ®s, uint8_t divider) |
paul@174 | 222 | { |
paul@174 | 223 | // Assert 1 as a minimum. |
paul@174 | 224 | // Divider 0 must be less than or equal to divider 1. |
paul@174 | 225 | |
paul@174 | 226 | uint8_t d0 = (uint8_t) floor(sqrt(divider ? divider : 1)); |
paul@174 | 227 | uint8_t d1 = divider / d0; |
paul@174 | 228 | |
paul@174 | 229 | _output_division0.set_field(regs, d0); |
paul@174 | 230 | _output_division1.set_field(regs, d1); |
paul@174 | 231 | } |
paul@174 | 232 | |
paul@174 | 233 | uint32_t |
paul@174 | 234 | Divider_pll::get_frequency(Cpm_regs ®s, uint32_t source_frequency) |
paul@174 | 235 | { |
paul@174 | 236 | return (source_frequency * get_multiplier(regs)) / |
paul@174 | 237 | (get_input_division(regs) * get_output_division(regs)); |
paul@174 | 238 | } |
paul@174 | 239 | |
paul@174 | 240 | void |
paul@174 | 241 | Divider_pll::set_pll_parameters(Cpm_regs ®s, uint16_t multiplier, |
paul@174 | 242 | uint8_t in_divider, uint8_t out_divider) |
paul@174 | 243 | { |
paul@174 | 244 | set_multiplier(regs, multiplier); |
paul@174 | 245 | set_input_division(regs, in_divider); |
paul@174 | 246 | set_output_division(regs, out_divider); |
paul@174 | 247 | } |
paul@174 | 248 | |
paul@174 | 249 | |
paul@174 | 250 | |
paul@173 | 251 | // Clock control. |
paul@173 | 252 | |
paul@173 | 253 | int |
paul@173 | 254 | Clock_base::have_clock(Cpm_regs ®s) |
paul@173 | 255 | { |
paul@173 | 256 | (void) regs; |
paul@173 | 257 | return true; |
paul@173 | 258 | } |
paul@173 | 259 | |
paul@173 | 260 | void |
paul@173 | 261 | Clock_base::start_clock(Cpm_regs ®s) |
paul@173 | 262 | { |
paul@173 | 263 | (void) regs; |
paul@173 | 264 | } |
paul@173 | 265 | |
paul@173 | 266 | void |
paul@173 | 267 | Clock_base::stop_clock(Cpm_regs ®s) |
paul@173 | 268 | { |
paul@173 | 269 | (void) regs; |
paul@173 | 270 | } |
paul@173 | 271 | |
paul@173 | 272 | // Default divider. |
paul@173 | 273 | |
paul@173 | 274 | uint32_t |
paul@173 | 275 | Clock_base::get_divider(Cpm_regs ®s) |
paul@173 | 276 | { |
paul@173 | 277 | (void) regs; |
paul@173 | 278 | return 1; |
paul@173 | 279 | } |
paul@173 | 280 | |
paul@173 | 281 | void |
paul@173 | 282 | Clock_base::set_divider(Cpm_regs ®s, uint32_t division) |
paul@173 | 283 | { |
paul@173 | 284 | (void) regs; |
paul@173 | 285 | (void) division; |
paul@173 | 286 | } |
paul@173 | 287 | |
paul@173 | 288 | // Clock sources. |
paul@173 | 289 | |
paul@173 | 290 | uint8_t |
paul@173 | 291 | Clock_base::get_source(Cpm_regs ®s) |
paul@173 | 292 | { |
paul@173 | 293 | return _source.get_source(regs); |
paul@173 | 294 | } |
paul@173 | 295 | |
paul@173 | 296 | void |
paul@173 | 297 | Clock_base::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 298 | { |
paul@173 | 299 | _source.set_source(regs, source); |
paul@173 | 300 | } |
paul@173 | 301 | |
paul@173 | 302 | // Clock source frequencies. |
paul@173 | 303 | |
paul@173 | 304 | uint32_t |
paul@173 | 305 | Clock_base::get_source_frequency(Cpm_regs ®s) |
paul@173 | 306 | { |
paul@173 | 307 | return _source.get_frequency(regs); |
paul@173 | 308 | } |
paul@173 | 309 | |
paul@173 | 310 | // Output clock frequencies. |
paul@173 | 311 | |
paul@173 | 312 | uint32_t |
paul@173 | 313 | Clock_base::get_frequency(Cpm_regs ®s) |
paul@173 | 314 | { |
paul@174 | 315 | return get_source_frequency(regs); |
paul@173 | 316 | } |
paul@173 | 317 | |
paul@173 | 318 | |
paul@173 | 319 | |
paul@173 | 320 | // PLL-specific control. |
paul@173 | 321 | |
paul@173 | 322 | int |
paul@173 | 323 | Pll::have_pll(Cpm_regs ®s) |
paul@173 | 324 | { |
paul@173 | 325 | return _stable.get_field(regs); |
paul@173 | 326 | } |
paul@173 | 327 | |
paul@173 | 328 | int |
paul@173 | 329 | Pll::pll_enabled(Cpm_regs ®s) |
paul@173 | 330 | { |
paul@173 | 331 | return _enable.get_field(regs); |
paul@173 | 332 | } |
paul@173 | 333 | |
paul@173 | 334 | int |
paul@173 | 335 | Pll::pll_bypassed(Cpm_regs ®s) |
paul@173 | 336 | { |
paul@173 | 337 | return _bypass.get_field(regs); |
paul@173 | 338 | } |
paul@173 | 339 | |
paul@173 | 340 | // Clock control. |
paul@173 | 341 | |
paul@173 | 342 | int |
paul@173 | 343 | Pll::have_clock(Cpm_regs ®s) |
paul@173 | 344 | { |
paul@173 | 345 | return have_pll(regs) && pll_enabled(regs); |
paul@173 | 346 | } |
paul@173 | 347 | |
paul@173 | 348 | void |
paul@173 | 349 | Pll::start_clock(Cpm_regs ®s) |
paul@173 | 350 | { |
paul@173 | 351 | _enable.set_field(regs, 1); |
paul@173 | 352 | while (!have_pll(regs)); |
paul@173 | 353 | } |
paul@173 | 354 | |
paul@173 | 355 | void |
paul@173 | 356 | Pll::stop_clock(Cpm_regs ®s) |
paul@173 | 357 | { |
paul@173 | 358 | _enable.set_field(regs, 0); |
paul@173 | 359 | while (have_pll(regs)); |
paul@173 | 360 | } |
paul@173 | 361 | |
paul@173 | 362 | // Feedback (13-bit) multiplier. |
paul@173 | 363 | |
paul@173 | 364 | uint16_t |
paul@173 | 365 | Pll::get_multiplier(Cpm_regs ®s) |
paul@173 | 366 | { |
paul@174 | 367 | return _divider.get_multiplier(regs); |
paul@173 | 368 | } |
paul@173 | 369 | |
paul@173 | 370 | void |
paul@173 | 371 | Pll::set_multiplier(Cpm_regs ®s, uint16_t multiplier) |
paul@173 | 372 | { |
paul@174 | 373 | _divider.set_multiplier(regs, multiplier); |
paul@173 | 374 | } |
paul@173 | 375 | |
paul@173 | 376 | // Input (6-bit) divider. |
paul@173 | 377 | |
paul@173 | 378 | uint8_t |
paul@173 | 379 | Pll::get_input_division(Cpm_regs ®s) |
paul@173 | 380 | { |
paul@174 | 381 | return _divider.get_input_division(regs); |
paul@173 | 382 | } |
paul@173 | 383 | |
paul@173 | 384 | void |
paul@173 | 385 | Pll::set_input_division(Cpm_regs ®s, uint8_t divider) |
paul@173 | 386 | { |
paul@174 | 387 | _divider.set_input_division(regs, divider); |
paul@173 | 388 | } |
paul@173 | 389 | |
paul@173 | 390 | // Output (dual 3-bit) dividers. |
paul@173 | 391 | |
paul@173 | 392 | uint8_t |
paul@173 | 393 | Pll::get_output_division(Cpm_regs ®s) |
paul@173 | 394 | { |
paul@174 | 395 | return _divider.get_output_division(regs); |
paul@173 | 396 | } |
paul@173 | 397 | |
paul@173 | 398 | void |
paul@173 | 399 | Pll::set_output_division(Cpm_regs ®s, uint8_t divider) |
paul@173 | 400 | { |
paul@174 | 401 | _divider.set_output_division(regs, divider); |
paul@173 | 402 | } |
paul@173 | 403 | |
paul@173 | 404 | uint32_t |
paul@173 | 405 | Pll::get_frequency(Cpm_regs ®s) |
paul@173 | 406 | { |
paul@173 | 407 | // Test for PLL enable and not PLL bypass. |
paul@173 | 408 | |
paul@173 | 409 | if (pll_enabled(regs)) |
paul@173 | 410 | { |
paul@173 | 411 | if (!pll_bypassed(regs)) |
paul@174 | 412 | return _divider.get_frequency(regs, get_source_frequency(regs)); |
paul@173 | 413 | else |
paul@173 | 414 | return get_source_frequency(regs); |
paul@173 | 415 | } |
paul@173 | 416 | else |
paul@173 | 417 | return 0; |
paul@173 | 418 | } |
paul@173 | 419 | |
paul@173 | 420 | void |
paul@174 | 421 | Pll::set_pll_parameters(Cpm_regs ®s, uint16_t multiplier, |
paul@174 | 422 | uint8_t in_divider, uint8_t out_divider) |
paul@173 | 423 | { |
paul@174 | 424 | set_pll_parameters(regs, multiplier, in_divider, out_divider); |
paul@173 | 425 | |
paul@173 | 426 | if (pll_enabled(regs) && !pll_bypassed(regs)) |
paul@173 | 427 | while (!have_pll(regs)); |
paul@173 | 428 | } |
paul@173 | 429 | |
paul@173 | 430 | |
paul@173 | 431 | |
paul@173 | 432 | // Clock control. |
paul@173 | 433 | |
paul@173 | 434 | void |
paul@173 | 435 | Clock::change_disable(Cpm_regs ®s) |
paul@173 | 436 | { |
paul@173 | 437 | if (_change_enable.is_defined()) |
paul@173 | 438 | _change_enable.set_field(regs, 0); |
paul@173 | 439 | } |
paul@173 | 440 | |
paul@173 | 441 | void |
paul@173 | 442 | Clock::change_enable(Cpm_regs ®s) |
paul@173 | 443 | { |
paul@173 | 444 | if (_change_enable.is_defined()) |
paul@173 | 445 | _change_enable.set_field(regs, 1); |
paul@173 | 446 | } |
paul@173 | 447 | |
paul@173 | 448 | int |
paul@173 | 449 | Clock::have_clock(Cpm_regs ®s) |
paul@173 | 450 | { |
paul@173 | 451 | if (_gate.is_defined()) |
paul@173 | 452 | return !_gate.get_field(regs); |
paul@173 | 453 | else |
paul@173 | 454 | return true; |
paul@173 | 455 | } |
paul@173 | 456 | |
paul@173 | 457 | void |
paul@173 | 458 | Clock::start_clock(Cpm_regs ®s) |
paul@173 | 459 | { |
paul@173 | 460 | if (_gate.is_defined()) |
paul@173 | 461 | _gate.set_field(regs, 0); |
paul@173 | 462 | } |
paul@173 | 463 | |
paul@173 | 464 | void |
paul@173 | 465 | Clock::stop_clock(Cpm_regs ®s) |
paul@173 | 466 | { |
paul@173 | 467 | if (_gate.is_defined()) |
paul@173 | 468 | _gate.set_field(regs, 1); |
paul@173 | 469 | } |
paul@173 | 470 | |
paul@173 | 471 | void |
paul@173 | 472 | Clock::wait_busy(Cpm_regs ®s) |
paul@173 | 473 | { |
paul@173 | 474 | if (_busy.is_defined()) |
paul@173 | 475 | while (_busy.get_field(regs)); |
paul@173 | 476 | } |
paul@173 | 477 | |
paul@173 | 478 | // Clock dividers. |
paul@173 | 479 | |
paul@173 | 480 | uint32_t |
paul@173 | 481 | Clock::get_divider(Cpm_regs ®s) |
paul@173 | 482 | { |
paul@174 | 483 | return _divider.get_divider(regs); |
paul@173 | 484 | } |
paul@173 | 485 | |
paul@173 | 486 | void |
paul@173 | 487 | Clock::set_divider(Cpm_regs ®s, uint32_t division) |
paul@173 | 488 | { |
paul@173 | 489 | change_enable(regs); |
paul@174 | 490 | _divider.set_divider(regs, division); |
paul@173 | 491 | wait_busy(regs); |
paul@173 | 492 | change_disable(regs); |
paul@173 | 493 | } |
paul@173 | 494 | |
paul@173 | 495 | void |
paul@173 | 496 | Clock::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 497 | { |
paul@173 | 498 | change_enable(regs); |
paul@173 | 499 | Clock_base::set_source(regs, source); |
paul@173 | 500 | wait_busy(regs); |
paul@173 | 501 | change_disable(regs); |
paul@173 | 502 | } |
paul@174 | 503 | |
paul@174 | 504 | // Output clock frequencies. |
paul@174 | 505 | |
paul@174 | 506 | uint32_t |
paul@174 | 507 | Clock::get_frequency(Cpm_regs ®s) |
paul@174 | 508 | { |
paul@174 | 509 | return _divider.get_frequency(regs, get_source_frequency(regs)); |
paul@174 | 510 | } |