paul@160 | 1 | /* |
paul@160 | 2 | * Clock and power management. This exposes the combined functionality |
paul@160 | 3 | * provided by the X1600 and related SoCs. The power management |
paul@160 | 4 | * functionality could be exposed using a separate driver. |
paul@160 | 5 | * |
paul@160 | 6 | * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@160 | 7 | * |
paul@160 | 8 | * This program is free software; you can redistribute it and/or |
paul@160 | 9 | * modify it under the terms of the GNU General Public License as |
paul@160 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@160 | 11 | * the License, or (at your option) any later version. |
paul@160 | 12 | * |
paul@160 | 13 | * This program is distributed in the hope that it will be useful, |
paul@160 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@160 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@160 | 16 | * GNU General Public License for more details. |
paul@160 | 17 | * |
paul@160 | 18 | * You should have received a copy of the GNU General Public License |
paul@160 | 19 | * along with this program; if not, write to the Free Software |
paul@160 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@160 | 21 | * Boston, MA 02110-1301, USA |
paul@160 | 22 | */ |
paul@160 | 23 | |
paul@160 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@160 | 25 | #include "cpm-x1600.h" |
paul@160 | 26 | #include <math.h> |
paul@161 | 27 | #include <stdio.h> |
paul@160 | 28 | |
paul@160 | 29 | |
paul@160 | 30 | |
paul@161 | 31 | // Register locations. |
paul@161 | 32 | |
paul@160 | 33 | enum Regs : unsigned |
paul@160 | 34 | { |
paul@160 | 35 | Clock_control = 0x000, // CPCCR |
paul@160 | 36 | Low_power_control = 0x004, // LCR |
paul@160 | 37 | Clock_gate0 = 0x020, // CLKGR0 |
paul@160 | 38 | Clock_gate1 = 0x028, // CLKGR1 |
paul@160 | 39 | Sleep_control = 0x024, // OPCR (oscillator and power control) |
paul@160 | 40 | Clock_status = 0x0d4, // CPCSR |
paul@167 | 41 | Divider_ddr = 0x02c, // DDRCDR |
paul@167 | 42 | Divider_mac = 0x054, // MACCDR |
paul@167 | 43 | Divider0_i2s0 = 0x060, // I2SCDR |
paul@167 | 44 | Divider1_i2s0 = 0x070, // I2S1CDR |
paul@167 | 45 | Divider_lcd = 0x064, // LPCDR |
paul@167 | 46 | Divider_msc0 = 0x068, // MSC0CDR |
paul@167 | 47 | Divider_msc1 = 0x0a4, // MSC1CDR |
paul@167 | 48 | Divider_sfc = 0x074, // SFCCDR |
paul@167 | 49 | Divider_ssi = 0x05c, // SSICDR |
paul@167 | 50 | Divider_cim = 0x078, // CIMCDR |
paul@167 | 51 | Divider_pwm = 0x06c, // PWMCDR |
paul@167 | 52 | Divider_can0 = 0x0a0, // CAN0CDR |
paul@167 | 53 | Divider_can1 = 0x0a8, // CAN1CDR |
paul@167 | 54 | Divider_cdbus = 0x0ac, // CDBUSCDR |
paul@167 | 55 | Divider_macphy0 = 0x0e4, // MPHY0C |
paul@160 | 56 | Cpm_interrupt = 0x0b0, // CPM_INTR |
paul@160 | 57 | Cpm_interrupt_en = 0x0b4, // CPM_INTRE |
paul@160 | 58 | Cpm_swi = 0x0bc, // CPM_SFTINT |
paul@160 | 59 | Ddr_gate = 0x0d0, // DRCG |
paul@160 | 60 | Cpm_scratch_prot = 0x038, // CPSPPR |
paul@160 | 61 | Cpm_scratch = 0x034, // CPSPR |
paul@160 | 62 | Usb_param_control0 = 0x03c, // USBPCR |
paul@160 | 63 | Usb_reset_detect = 0x040, // USBRDT |
paul@160 | 64 | Usb_vbus_jitter = 0x044, // USBVBFIL |
paul@160 | 65 | Usb_param_control1 = 0x048, // USBPCR1 |
paul@160 | 66 | Pll_control = 0x00c, // CPPCR |
paul@160 | 67 | Pll_control_A = 0x010, // CPAPCR |
paul@160 | 68 | Pll_control_M = 0x014, // CPMPCR |
paul@160 | 69 | Pll_control_E = 0x018, // CPEPCR |
paul@160 | 70 | Pll_fraction_A = 0x084, // CPAPACR |
paul@160 | 71 | Pll_fraction_M = 0x088, // CPMPACR |
paul@160 | 72 | Pll_fraction_E = 0x08c, // CPEPACR |
paul@160 | 73 | }; |
paul@160 | 74 | |
paul@161 | 75 | enum Clock_source_values : unsigned |
paul@160 | 76 | { |
paul@161 | 77 | Source_mME_main = 0, |
paul@161 | 78 | Source_mME_pll_M = 1, |
paul@161 | 79 | Source_mME_pll_E = 2, |
paul@160 | 80 | |
paul@161 | 81 | // Special value |
paul@160 | 82 | |
paul@161 | 83 | Source_mask = 0x3, |
paul@160 | 84 | }; |
paul@160 | 85 | |
paul@160 | 86 | |
paul@160 | 87 | |
paul@166 | 88 | // Register field abstraction. |
paul@166 | 89 | |
paul@166 | 90 | class Field |
paul@166 | 91 | { |
paul@166 | 92 | uint32_t reg; |
paul@166 | 93 | uint32_t mask; |
paul@166 | 94 | uint8_t bit; |
paul@166 | 95 | bool defined; |
paul@166 | 96 | |
paul@166 | 97 | public: |
paul@166 | 98 | explicit Field() |
paul@166 | 99 | : defined(false) |
paul@166 | 100 | { |
paul@166 | 101 | } |
paul@166 | 102 | |
paul@166 | 103 | explicit Field(uint32_t reg, uint32_t mask, uint32_t bit) |
paul@166 | 104 | : reg(reg), mask(mask), bit(bit), defined(true) |
paul@166 | 105 | { |
paul@166 | 106 | } |
paul@166 | 107 | |
paul@166 | 108 | uint32_t get_field(Cpm_regs ®s); |
paul@166 | 109 | void set_field(Cpm_regs ®s, uint32_t value); |
paul@166 | 110 | bool is_defined() { return defined; } |
paul@166 | 111 | }; |
paul@166 | 112 | |
paul@166 | 113 | // Undefined fields. |
paul@166 | 114 | |
paul@171 | 115 | Field Gate_undefined, Change_enable_undefined, Busy_undefined, Divider_undefined; |
paul@166 | 116 | |
paul@166 | 117 | |
paul@166 | 118 | |
paul@169 | 119 | // Clock sources. |
paul@169 | 120 | |
paul@169 | 121 | class Mux |
paul@169 | 122 | { |
paul@169 | 123 | int _num_inputs; |
paul@171 | 124 | enum Clock_identifiers *_inputs, _input; |
paul@169 | 125 | |
paul@169 | 126 | public: |
paul@171 | 127 | explicit Mux(int num_inputs, enum Clock_identifiers inputs[]) |
paul@169 | 128 | : _num_inputs(num_inputs), _inputs(inputs) |
paul@169 | 129 | { |
paul@169 | 130 | } |
paul@169 | 131 | |
paul@171 | 132 | explicit Mux(enum Clock_identifiers input) |
paul@171 | 133 | : _num_inputs(1), _inputs(&_input) |
paul@171 | 134 | { |
paul@171 | 135 | _input = input; |
paul@171 | 136 | } |
paul@171 | 137 | |
paul@171 | 138 | explicit Mux() |
paul@171 | 139 | : _num_inputs(0), _inputs(NULL) |
paul@171 | 140 | { |
paul@171 | 141 | } |
paul@171 | 142 | |
paul@169 | 143 | int get_number() { return _num_inputs; } |
paul@169 | 144 | enum Clock_identifiers get_input(int num); |
paul@169 | 145 | }; |
paul@169 | 146 | |
paul@171 | 147 | class Source |
paul@171 | 148 | { |
paul@171 | 149 | Mux _inputs; |
paul@171 | 150 | Field _source; |
paul@171 | 151 | |
paul@171 | 152 | public: |
paul@171 | 153 | explicit Source(Mux inputs, Field source) |
paul@171 | 154 | : _inputs(inputs), _source(source) |
paul@171 | 155 | { |
paul@171 | 156 | } |
paul@171 | 157 | |
paul@171 | 158 | explicit Source(Mux inputs) |
paul@171 | 159 | : _inputs(inputs) |
paul@171 | 160 | { |
paul@171 | 161 | } |
paul@171 | 162 | |
paul@171 | 163 | explicit Source() |
paul@171 | 164 | { |
paul@171 | 165 | } |
paul@171 | 166 | |
paul@171 | 167 | int get_number() { return _inputs.get_number(); } |
paul@171 | 168 | enum Clock_identifiers get_input(int num) { return _inputs.get_input(num); } |
paul@171 | 169 | |
paul@171 | 170 | // Clock source. |
paul@171 | 171 | |
paul@171 | 172 | uint8_t get_source(Cpm_regs ®s); |
paul@171 | 173 | void set_source(Cpm_regs ®s, uint8_t source); |
paul@171 | 174 | }; |
paul@171 | 175 | |
paul@169 | 176 | // Undefined sources. |
paul@169 | 177 | |
paul@171 | 178 | Source Source_undefined; |
paul@169 | 179 | |
paul@169 | 180 | |
paul@169 | 181 | |
paul@165 | 182 | // Common clock abstraction. |
paul@165 | 183 | |
paul@165 | 184 | class Clock_base |
paul@165 | 185 | { |
paul@171 | 186 | Source _source; |
paul@165 | 187 | |
paul@165 | 188 | public: |
paul@171 | 189 | explicit Clock_base(Source source) |
paul@171 | 190 | : _source(source) |
paul@165 | 191 | { |
paul@165 | 192 | } |
paul@165 | 193 | |
paul@165 | 194 | // Clock control. |
paul@165 | 195 | |
paul@165 | 196 | virtual int have_clock(Cpm_regs ®s); |
paul@165 | 197 | virtual void start_clock(Cpm_regs ®s); |
paul@165 | 198 | virtual void stop_clock(Cpm_regs ®s); |
paul@165 | 199 | |
paul@165 | 200 | // Clock divider. |
paul@165 | 201 | |
paul@165 | 202 | virtual uint32_t get_divider(Cpm_regs ®s); |
paul@165 | 203 | virtual void set_divider(Cpm_regs ®s, uint32_t division); |
paul@165 | 204 | |
paul@165 | 205 | // Clock source. |
paul@165 | 206 | |
paul@165 | 207 | virtual uint8_t get_source(Cpm_regs ®s); |
paul@165 | 208 | virtual void set_source(Cpm_regs ®s, uint8_t source); |
paul@165 | 209 | |
paul@165 | 210 | // Clock source frequency. |
paul@165 | 211 | |
paul@165 | 212 | virtual uint32_t get_source_frequency(Cpm_regs ®s); |
paul@165 | 213 | |
paul@165 | 214 | // Output frequency. |
paul@165 | 215 | |
paul@165 | 216 | virtual uint32_t get_frequency(Cpm_regs ®s); |
paul@165 | 217 | }; |
paul@165 | 218 | |
paul@165 | 219 | |
paul@165 | 220 | |
paul@165 | 221 | // PLL descriptions. |
paul@165 | 222 | |
paul@165 | 223 | class Pll : public Clock_base |
paul@165 | 224 | { |
paul@168 | 225 | Field _enable, _stable, _bypass; |
paul@168 | 226 | Field _multiplier, _input_division, _output_division0, _output_division1; |
paul@165 | 227 | |
paul@165 | 228 | public: |
paul@171 | 229 | explicit Pll(Source source, |
paul@168 | 230 | Field enable, Field stable, Field bypass, |
paul@168 | 231 | Field multiplier, Field input_division, |
paul@168 | 232 | Field output_division0, Field output_division1) |
paul@171 | 233 | : Clock_base(source), |
paul@168 | 234 | _enable(enable), _stable(stable), _bypass(bypass), |
paul@168 | 235 | _multiplier(multiplier), _input_division(input_division), |
paul@168 | 236 | _output_division0(output_division0), _output_division1(output_division1) |
paul@165 | 237 | { |
paul@165 | 238 | } |
paul@165 | 239 | |
paul@165 | 240 | // PLL_specific control. |
paul@165 | 241 | |
paul@165 | 242 | int have_pll(Cpm_regs ®s); |
paul@165 | 243 | int pll_enabled(Cpm_regs ®s); |
paul@165 | 244 | int pll_bypassed(Cpm_regs ®s); |
paul@165 | 245 | |
paul@165 | 246 | // Clock control. |
paul@165 | 247 | |
paul@165 | 248 | int have_clock(Cpm_regs ®s); |
paul@165 | 249 | void start_clock(Cpm_regs ®s); |
paul@165 | 250 | void stop_clock(Cpm_regs ®s); |
paul@165 | 251 | |
paul@165 | 252 | // General frequency modifiers. |
paul@165 | 253 | |
paul@165 | 254 | uint16_t get_multiplier(Cpm_regs ®s); |
paul@165 | 255 | void set_multiplier(Cpm_regs ®s, uint16_t multiplier); |
paul@165 | 256 | uint8_t get_input_division(Cpm_regs ®s); |
paul@165 | 257 | void set_input_division(Cpm_regs ®s, uint8_t divider); |
paul@165 | 258 | uint8_t get_output_division(Cpm_regs ®s); |
paul@165 | 259 | void set_output_division(Cpm_regs ®s, uint8_t divider); |
paul@165 | 260 | |
paul@165 | 261 | // PLL output frequency. |
paul@165 | 262 | |
paul@165 | 263 | uint32_t get_frequency(Cpm_regs ®s); |
paul@165 | 264 | |
paul@165 | 265 | // Other operations. |
paul@165 | 266 | |
paul@165 | 267 | void set_pll_parameters(Cpm_regs ®s, uint16_t multiplier, |
paul@165 | 268 | uint8_t in_divider, uint8_t out_divider); |
paul@165 | 269 | }; |
paul@165 | 270 | |
paul@165 | 271 | |
paul@165 | 272 | |
paul@161 | 273 | // Clock descriptions. |
paul@161 | 274 | |
paul@165 | 275 | class Clock : public Clock_base |
paul@161 | 276 | { |
paul@166 | 277 | Field _gate, _change_enable, _busy, _divider; |
paul@161 | 278 | |
paul@165 | 279 | // Clock control. |
paul@161 | 280 | |
paul@165 | 281 | void change_disable(Cpm_regs ®s); |
paul@165 | 282 | void change_enable(Cpm_regs ®s); |
paul@165 | 283 | void wait_busy(Cpm_regs ®s); |
paul@161 | 284 | |
paul@165 | 285 | public: |
paul@171 | 286 | explicit Clock(Source source = Source_undefined, |
paul@166 | 287 | Field gate = Gate_undefined, |
paul@166 | 288 | Field change_enable = Change_enable_undefined, |
paul@166 | 289 | Field busy = Busy_undefined, |
paul@166 | 290 | Field divider = Divider_undefined) |
paul@171 | 291 | : Clock_base(source), |
paul@166 | 292 | _gate(gate), _change_enable(change_enable), _busy(busy), _divider(divider) |
paul@165 | 293 | { |
paul@165 | 294 | } |
paul@161 | 295 | |
paul@165 | 296 | // Clock control. |
paul@161 | 297 | |
paul@165 | 298 | int have_clock(Cpm_regs ®s); |
paul@165 | 299 | void start_clock(Cpm_regs ®s); |
paul@165 | 300 | void stop_clock(Cpm_regs ®s); |
paul@161 | 301 | |
paul@165 | 302 | // Clock divider. |
paul@161 | 303 | |
paul@165 | 304 | uint32_t get_divider(Cpm_regs ®s); |
paul@165 | 305 | void set_divider(Cpm_regs ®s, uint32_t division); |
paul@161 | 306 | |
paul@165 | 307 | // Clock source. |
paul@161 | 308 | |
paul@165 | 309 | void set_source(Cpm_regs ®s, uint8_t source); |
paul@161 | 310 | }; |
paul@161 | 311 | |
paul@161 | 312 | |
paul@161 | 313 | |
paul@167 | 314 | // Register field definitions. |
paul@167 | 315 | |
paul@168 | 316 | Field Clock_source_main (Clock_control, 3, 30); // SEL_SRC (output to SCLK_A) |
paul@168 | 317 | Field Clock_source_cpu (Clock_control, 3, 28); // SEL_CPLL (output to CCLK) |
paul@168 | 318 | Field Clock_source_hclock0 (Clock_control, 3, 26); // SEL_H0PLL (output to AHB0) |
paul@168 | 319 | Field Clock_source_hclock2 (Clock_control, 3, 24); // SEL_H2PLL (output to AHB2) |
paul@168 | 320 | Field Clock_source_can0 (Divider_can0, 3, 30); // CA0CS |
paul@168 | 321 | Field Clock_source_can1 (Divider_can1, 3, 30); // CA1CS |
paul@168 | 322 | Field Clock_source_cdbus (Divider_cdbus, 3, 30); // CDCS |
paul@168 | 323 | Field Clock_source_cim (Divider_cim, 3, 30); // CIMPCS |
paul@168 | 324 | Field Clock_source_ddr (Divider_ddr, 3, 30); // DCS |
paul@168 | 325 | Field Clock_source_i2s (Divider0_i2s0, 1, 31); // I2PCS |
paul@168 | 326 | Field Clock_source_lcd (Divider_lcd, 3, 30); // LPCS |
paul@168 | 327 | Field Clock_source_mac (Divider_mac, 3, 30); // MACPCS |
paul@168 | 328 | Field Clock_source_msc0 (Divider_msc0, 3, 30); // MPCS |
paul@168 | 329 | Field Clock_source_msc1 (Divider_msc1, 3, 30); // MPCS |
paul@168 | 330 | Field Clock_source_pwm (Divider_pwm, 3, 30); // PWMPCS |
paul@168 | 331 | Field Clock_source_sfc (Divider_sfc, 3, 30); // SFCS |
paul@168 | 332 | Field Clock_source_ssi (Divider_ssi, 3, 30); // SPCS |
paul@167 | 333 | |
paul@167 | 334 | Field Clock_busy_cpu (Clock_status, 1, 0); |
paul@167 | 335 | Field Clock_busy_ddr (Divider_ddr, 1, 28); |
paul@167 | 336 | Field Clock_busy_mac (Divider_mac, 1, 28); |
paul@167 | 337 | Field Clock_busy_lcd (Divider_lcd, 1, 28); |
paul@167 | 338 | Field Clock_busy_msc0 (Divider_msc0, 1, 28); |
paul@167 | 339 | Field Clock_busy_msc1 (Divider_msc1, 1, 28); |
paul@167 | 340 | Field Clock_busy_sfc (Divider_sfc, 1, 28); |
paul@167 | 341 | Field Clock_busy_ssi (Divider_ssi, 1, 28); |
paul@167 | 342 | Field Clock_busy_cim (Divider_cim, 1, 28); |
paul@167 | 343 | Field Clock_busy_pwm (Divider_pwm, 1, 28); |
paul@167 | 344 | Field Clock_busy_can0 (Divider_can0, 1, 28); |
paul@167 | 345 | Field Clock_busy_can1 (Divider_can1, 1, 28); |
paul@167 | 346 | Field Clock_busy_cdbus (Divider_cdbus, 1, 28); |
paul@167 | 347 | |
paul@167 | 348 | Field Clock_change_enable_cpu (Clock_control, 1, 22); |
paul@167 | 349 | Field Clock_change_enable_ahb0 (Clock_control, 1, 21); |
paul@167 | 350 | Field Clock_change_enable_ahb2 (Clock_control, 1, 20); |
paul@167 | 351 | Field Clock_change_enable_ddr (Divider_ddr, 1, 29); |
paul@167 | 352 | Field Clock_change_enable_mac (Divider_mac, 1, 29); |
paul@167 | 353 | Field Clock_change_enable_i2s (Divider0_i2s0, 1, 29); |
paul@167 | 354 | Field Clock_change_enable_lcd (Divider_lcd, 1, 29); |
paul@167 | 355 | Field Clock_change_enable_msc0 (Divider_msc0, 1, 29); |
paul@167 | 356 | Field Clock_change_enable_msc1 (Divider_msc1, 1, 29); |
paul@167 | 357 | Field Clock_change_enable_sfc (Divider_sfc, 1, 29); |
paul@167 | 358 | Field Clock_change_enable_ssi (Divider_ssi, 1, 29); |
paul@167 | 359 | Field Clock_change_enable_cim (Divider_cim, 1, 29); |
paul@167 | 360 | Field Clock_change_enable_pwm (Divider_pwm, 1, 29); |
paul@167 | 361 | Field Clock_change_enable_can0 (Divider_can0, 1, 29); |
paul@167 | 362 | Field Clock_change_enable_can1 (Divider_can1, 1, 29); |
paul@167 | 363 | Field Clock_change_enable_cdbus (Divider_cdbus, 1, 29); |
paul@167 | 364 | |
paul@168 | 365 | Field Clock_divider_can0 (Divider_can0, 0xff, 0); // CAN0CDR |
paul@168 | 366 | Field Clock_divider_can1 (Divider_can1, 0xff, 0); // CAN1CDR |
paul@168 | 367 | Field Clock_divider_cdbus (Divider_cdbus, 0xff, 0); // CDBUSCDR |
paul@168 | 368 | Field Clock_divider_cim (Divider_cim, 0xff, 0); // CIMCDR |
paul@168 | 369 | Field Clock_divider_cpu (Clock_control, 0x0f, 0); // CDIV |
paul@168 | 370 | Field Clock_divider_ddr (Divider_ddr, 0x0f, 0); // DDRCDR |
paul@168 | 371 | Field Clock_divider_hclock0 (Clock_control, 0x0f, 8); // H0DIV (fast AHB peripherals) |
paul@168 | 372 | Field Clock_divider_hclock2 (Clock_control, 0x0f, 12); // H2DIV (fast AHB peripherals) |
paul@168 | 373 | Field Clock_divider_l2cache (Clock_control, 0x0f, 4); // L2CDIV |
paul@168 | 374 | Field Clock_divider_lcd (Divider_lcd, 0xff, 0); // LPCDR |
paul@168 | 375 | Field Clock_divider_mac (Divider_mac, 0xff, 0); // MACCDR |
paul@168 | 376 | Field Clock_divider_msc0 (Divider_msc0, 0xff, 0); // MSC0CDR |
paul@168 | 377 | Field Clock_divider_msc1 (Divider_msc1, 0xff, 0); // MSC1CDR |
paul@168 | 378 | Field Clock_divider_pclock (Clock_control, 0x0f, 16); // PDIV (slow APB peripherals) |
paul@168 | 379 | Field Clock_divider_pwm (Divider_pwm, 0x0f, 0); // PWMCDR |
paul@168 | 380 | Field Clock_divider_sfc (Divider_sfc, 0xff, 0); // SFCCDR |
paul@168 | 381 | Field Clock_divider_ssi (Divider_ssi, 0xff, 0); // SSICDR |
paul@167 | 382 | |
paul@168 | 383 | Field Clock_gate_main (Clock_control, 1, 23); // GATE_SCLKA |
paul@168 | 384 | Field Clock_gate_ddr (Clock_gate0, 1, 31); // DDR |
paul@168 | 385 | Field Clock_gate_ahb0 (Clock_gate0, 1, 29); // AHB0 |
paul@168 | 386 | Field Clock_gate_apb0 (Clock_gate0, 1, 28); // APB0 |
paul@168 | 387 | Field Clock_gate_rtc (Clock_gate0, 1, 27); // RTC |
paul@168 | 388 | Field Clock_gate_aes (Clock_gate0, 1, 24); // AES |
paul@168 | 389 | Field Clock_gate_lcd_pixel (Clock_gate0, 1, 23); // LCD |
paul@168 | 390 | Field Clock_gate_cim (Clock_gate0, 1, 22); // CIM |
paul@168 | 391 | Field Clock_gate_dma (Clock_gate0, 1, 21); // PDMA |
paul@168 | 392 | Field Clock_gate_ost (Clock_gate0, 1, 20); // OST |
paul@168 | 393 | Field Clock_gate_ssi0 (Clock_gate0, 1, 19); // SSI0 |
paul@168 | 394 | Field Clock_gate_timer (Clock_gate0, 1, 18); // TCU |
paul@168 | 395 | Field Clock_gate_dtrng (Clock_gate0, 1, 17); // DTRNG |
paul@168 | 396 | Field Clock_gate_uart2 (Clock_gate0, 1, 16); // UART2 |
paul@168 | 397 | Field Clock_gate_uart1 (Clock_gate0, 1, 15); // UART1 |
paul@168 | 398 | Field Clock_gate_uart0 (Clock_gate0, 1, 14); // UART0 |
paul@168 | 399 | Field Clock_gate_sadc (Clock_gate0, 1, 13); // SADC |
paul@168 | 400 | Field Clock_gate_audio (Clock_gate0, 1, 11); // AUDIO |
paul@168 | 401 | Field Clock_gate_ssi_slv (Clock_gate0, 1, 10); // SSI_SLV |
paul@168 | 402 | Field Clock_gate_i2c1 (Clock_gate0, 1, 8); // I2C1 |
paul@168 | 403 | Field Clock_gate_i2c0 (Clock_gate0, 1, 7); // I2C0 |
paul@168 | 404 | Field Clock_gate_msc1 (Clock_gate0, 1, 5); // MSC1 |
paul@168 | 405 | Field Clock_gate_msc0 (Clock_gate0, 1, 4); // MSC0 |
paul@168 | 406 | Field Clock_gate_otg (Clock_gate0, 1, 3); // OTG |
paul@168 | 407 | Field Clock_gate_sfc (Clock_gate0, 1, 2); // SFC |
paul@168 | 408 | Field Clock_gate_efuse (Clock_gate0, 1, 1); // EFUSE |
paul@168 | 409 | Field Clock_gate_nemc (Clock_gate0, 1, 0); // NEMC |
paul@168 | 410 | Field Clock_gate_arb (Clock_gate1, 1, 30); // ARB |
paul@168 | 411 | Field Clock_gate_mipi_csi (Clock_gate1, 1, 28); // MIPI_CSI |
paul@168 | 412 | Field Clock_gate_intc (Clock_gate1, 1, 26); // INTC |
paul@168 | 413 | Field Clock_gate_gmac0 (Clock_gate1, 1, 23); // GMAC0 |
paul@168 | 414 | Field Clock_gate_uart3 (Clock_gate1, 1, 16); // UART3 |
paul@168 | 415 | Field Clock_gate_i2s0_tx (Clock_gate1, 1, 9); // I2S0_dev_tclk |
paul@168 | 416 | Field Clock_gate_i2s0_rx (Clock_gate1, 1, 8); // I2S0_dev_rclk |
paul@168 | 417 | Field Clock_gate_hash (Clock_gate1, 1, 6); // HASH |
paul@168 | 418 | Field Clock_gate_pwm (Clock_gate1, 1, 5); // PWM |
paul@168 | 419 | Field Clock_gate_cdbus (Clock_gate1, 1, 2); // CDBUS |
paul@168 | 420 | Field Clock_gate_can1 (Clock_gate1, 1, 1); // CAN1 |
paul@168 | 421 | Field Clock_gate_can0 (Clock_gate1, 1, 0); // CAN0 |
paul@168 | 422 | |
paul@168 | 423 | Field Pll_enable_A (Pll_control_A, 1, 0); // APLLEN |
paul@168 | 424 | Field Pll_enable_E (Pll_control_E, 1, 0); // EPLLEN |
paul@168 | 425 | Field Pll_enable_M (Pll_control_M, 1, 0); // MPLLEN |
paul@168 | 426 | |
paul@168 | 427 | Field Pll_stable_A (Pll_control_A, 1, 3); // APLL_ON |
paul@168 | 428 | Field Pll_stable_E (Pll_control_E, 1, 3); // EPLL_ON |
paul@168 | 429 | Field Pll_stable_M (Pll_control_M, 1, 3); // MPLL_ON |
paul@168 | 430 | |
paul@168 | 431 | Field Pll_bypass_A (Pll_control_A, 1, 30); // APLL_BP |
paul@168 | 432 | Field Pll_bypass_E (Pll_control_E, 1, 26); // EPLL_BP |
paul@168 | 433 | Field Pll_bypass_M (Pll_control_M, 1, 28); // MPLL_BP |
paul@168 | 434 | |
paul@168 | 435 | Field Pll_multiplier_A (Pll_control_A, 0x1fff, 20); // APLLM |
paul@168 | 436 | Field Pll_multiplier_E (Pll_control_E, 0x1fff, 20); // EPLLM |
paul@168 | 437 | Field Pll_multiplier_M (Pll_control_M, 0x1fff, 20); // MPLLM |
paul@168 | 438 | |
paul@168 | 439 | Field Pll_input_division_A (Pll_control_A, 0x3f, 14); // APLLN |
paul@168 | 440 | Field Pll_input_division_E (Pll_control_E, 0x3f, 14); // EPLLN |
paul@168 | 441 | Field Pll_input_division_M (Pll_control_M, 0x3f, 14); // MPLLN |
paul@168 | 442 | |
paul@168 | 443 | Field Pll_output_division1_A (Pll_control_A, 0x07, 11); // APLLOD1 |
paul@168 | 444 | Field Pll_output_division1_E (Pll_control_E, 0x07, 11); // EPLLOD1 |
paul@168 | 445 | Field Pll_output_division1_M (Pll_control_M, 0x07, 11); // MPLLOD1 |
paul@168 | 446 | |
paul@168 | 447 | Field Pll_output_division0_A (Pll_control_A, 0x07, 8); // APLLOD0 |
paul@168 | 448 | Field Pll_output_division0_E (Pll_control_E, 0x07, 8); // EPLLOD0 |
paul@168 | 449 | Field Pll_output_division0_M (Pll_control_M, 0x07, 8); // MPLLOD0 |
paul@167 | 450 | |
paul@167 | 451 | |
paul@167 | 452 | |
paul@169 | 453 | // Multiplexer instances. |
paul@169 | 454 | |
paul@169 | 455 | #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) |
paul@169 | 456 | |
paul@171 | 457 | Mux mux_external(Clock_external); |
paul@171 | 458 | |
paul@171 | 459 | Mux mux_pclock(Clock_pclock); |
paul@171 | 460 | |
paul@171 | 461 | Mux mux_ahb2_apb(Clock_ahb2_apb); |
paul@169 | 462 | |
paul@169 | 463 | Mux mux_core(3, Clocks(Clock_none, Clock_main, Clock_pll_M)); |
paul@169 | 464 | |
paul@169 | 465 | Mux mux_bus(4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)); |
paul@169 | 466 | |
paul@169 | 467 | Mux mux_dev(3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)); |
paul@169 | 468 | |
paul@169 | 469 | Mux mux_i2s(2, Clocks(Clock_main, Clock_pll_E)); |
paul@169 | 470 | |
paul@169 | 471 | |
paul@169 | 472 | |
paul@165 | 473 | // Clock instances. |
paul@165 | 474 | |
paul@171 | 475 | Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)); |
paul@165 | 476 | |
paul@165 | 477 | Clock clock_aic_bitclk; |
paul@165 | 478 | |
paul@165 | 479 | Clock clock_aic_pclk; |
paul@165 | 480 | |
paul@171 | 481 | Clock clock_can0(Source(mux_bus, Clock_source_can0), |
paul@167 | 482 | Clock_gate_can0, |
paul@167 | 483 | Clock_change_enable_can0, |
paul@167 | 484 | Clock_busy_can0, |
paul@167 | 485 | Clock_divider_can0); |
paul@165 | 486 | |
paul@171 | 487 | Clock clock_can1(Source(mux_bus, Clock_source_can1), |
paul@167 | 488 | Clock_gate_can1, |
paul@167 | 489 | Clock_change_enable_can1, |
paul@167 | 490 | Clock_busy_can1, |
paul@167 | 491 | Clock_divider_can1); |
paul@165 | 492 | |
paul@171 | 493 | Clock clock_cdbus(Source(mux_dev, Clock_source_cdbus), |
paul@167 | 494 | Clock_gate_cdbus, |
paul@167 | 495 | Clock_change_enable_cdbus, |
paul@167 | 496 | Clock_busy_cdbus, |
paul@167 | 497 | Clock_divider_cdbus); |
paul@165 | 498 | |
paul@171 | 499 | Clock clock_cim(Source(mux_dev, Clock_source_cim), |
paul@167 | 500 | Clock_gate_cim, |
paul@167 | 501 | Clock_change_enable_cim, |
paul@167 | 502 | Clock_busy_cim, |
paul@167 | 503 | Clock_divider_cim); |
paul@165 | 504 | |
paul@171 | 505 | Clock clock_cpu(Source(mux_core, Clock_source_cpu), |
paul@166 | 506 | Gate_undefined, |
paul@167 | 507 | Clock_change_enable_cpu, |
paul@167 | 508 | Clock_busy_cpu, |
paul@167 | 509 | Clock_divider_cpu); |
paul@165 | 510 | |
paul@171 | 511 | Clock clock_ddr(Source(mux_core, Clock_source_ddr), |
paul@167 | 512 | Clock_gate_ddr, |
paul@167 | 513 | Clock_change_enable_ddr, |
paul@167 | 514 | Clock_busy_ddr, |
paul@167 | 515 | Clock_divider_ddr); |
paul@165 | 516 | |
paul@171 | 517 | Clock clock_dma(Source(mux_pclock), Clock_gate_dma); |
paul@165 | 518 | |
paul@165 | 519 | Clock clock_emac; |
paul@165 | 520 | |
paul@165 | 521 | Clock clock_external; |
paul@165 | 522 | |
paul@171 | 523 | Clock clock_hclock0(Source(mux_core, Clock_source_hclock0), |
paul@167 | 524 | Clock_gate_ahb0, |
paul@167 | 525 | Clock_change_enable_ahb0, |
paul@166 | 526 | Busy_undefined, |
paul@167 | 527 | Clock_divider_hclock0); |
paul@165 | 528 | |
paul@171 | 529 | Clock clock_hclock2(Source(mux_ahb2_apb), |
paul@167 | 530 | Clock_gate_apb0, |
paul@167 | 531 | Clock_change_enable_ahb2, |
paul@166 | 532 | Busy_undefined, |
paul@167 | 533 | Clock_divider_hclock2); |
paul@165 | 534 | |
paul@165 | 535 | Clock clock_hdmi; |
paul@165 | 536 | |
paul@171 | 537 | Clock clock_i2c(Source(mux_pclock), Clock_gate_i2c0); |
paul@165 | 538 | |
paul@171 | 539 | Clock clock_i2c0(Source(mux_pclock), Clock_gate_i2c0); |
paul@165 | 540 | |
paul@171 | 541 | Clock clock_i2c1(Source(mux_pclock), Clock_gate_i2c1); |
paul@165 | 542 | |
paul@165 | 543 | Clock clock_i2s; |
paul@165 | 544 | |
paul@171 | 545 | Clock clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s), |
paul@167 | 546 | Clock_gate_i2s0_rx, |
paul@167 | 547 | Clock_change_enable_i2s); |
paul@165 | 548 | |
paul@171 | 549 | Clock clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s), |
paul@167 | 550 | Clock_gate_i2s0_tx, |
paul@167 | 551 | Clock_change_enable_i2s); |
paul@165 | 552 | |
paul@165 | 553 | Clock clock_kbc; |
paul@165 | 554 | |
paul@165 | 555 | Clock clock_lcd; |
paul@165 | 556 | |
paul@171 | 557 | Clock clock_lcd_pixel(Source(mux_dev, Clock_source_lcd), |
paul@167 | 558 | Clock_gate_lcd_pixel, |
paul@167 | 559 | Clock_change_enable_lcd, |
paul@167 | 560 | Clock_busy_lcd, |
paul@167 | 561 | Clock_divider_lcd); |
paul@165 | 562 | |
paul@171 | 563 | Clock clock_mac(Source(mux_dev, Clock_source_mac), |
paul@167 | 564 | Clock_gate_gmac0, |
paul@167 | 565 | Clock_change_enable_mac, |
paul@167 | 566 | Clock_busy_mac, |
paul@167 | 567 | Clock_divider_mac); |
paul@165 | 568 | |
paul@171 | 569 | Clock clock_main(Source(mux_core, Clock_source_main), |
paul@167 | 570 | Clock_gate_main); |
paul@165 | 571 | |
paul@171 | 572 | Clock clock_msc(Source(mux_dev, Clock_source_msc0), |
paul@167 | 573 | Clock_gate_msc0, |
paul@167 | 574 | Clock_change_enable_msc0, |
paul@167 | 575 | Clock_busy_msc0, |
paul@167 | 576 | Clock_divider_msc0); |
paul@165 | 577 | |
paul@171 | 578 | Clock clock_msc0(Source(mux_dev, Clock_source_msc0), |
paul@167 | 579 | Clock_gate_msc0, |
paul@167 | 580 | Clock_change_enable_msc0, |
paul@167 | 581 | Clock_busy_msc0, |
paul@167 | 582 | Clock_divider_msc0); |
paul@165 | 583 | |
paul@171 | 584 | Clock clock_msc1(Source(mux_dev, Clock_source_msc1), |
paul@167 | 585 | Clock_gate_msc1, |
paul@167 | 586 | Clock_change_enable_msc1, |
paul@167 | 587 | Clock_busy_msc1, |
paul@167 | 588 | Clock_divider_msc1); |
paul@165 | 589 | |
paul@165 | 590 | Clock clock_none; |
paul@161 | 591 | |
paul@171 | 592 | Clock clock_pclock(Source(mux_ahb2_apb), |
paul@167 | 593 | Clock_gate_apb0, |
paul@166 | 594 | Change_enable_undefined, |
paul@166 | 595 | Busy_undefined, |
paul@167 | 596 | Clock_divider_pclock); |
paul@165 | 597 | |
paul@171 | 598 | Pll clock_pll_A(Source(mux_external), |
paul@168 | 599 | Pll_enable_A, Pll_stable_A, Pll_bypass_A, |
paul@168 | 600 | Pll_multiplier_A, Pll_input_division_A, |
paul@168 | 601 | Pll_output_division0_A, Pll_output_division1_A); |
paul@165 | 602 | |
paul@171 | 603 | Pll clock_pll_E(Source(mux_external), |
paul@168 | 604 | Pll_enable_E, Pll_stable_E, Pll_bypass_E, |
paul@168 | 605 | Pll_multiplier_E, Pll_input_division_E, |
paul@168 | 606 | Pll_output_division0_E, Pll_output_division1_E); |
paul@165 | 607 | |
paul@171 | 608 | Pll clock_pll_M(Source(mux_external), |
paul@168 | 609 | Pll_enable_M, Pll_stable_M, Pll_bypass_M, |
paul@168 | 610 | Pll_multiplier_M, Pll_input_division_M, |
paul@168 | 611 | Pll_output_division0_M, Pll_output_division1_M); |
paul@165 | 612 | |
paul@171 | 613 | Clock clock_pwm(Source(mux_dev, Clock_source_pwm), |
paul@167 | 614 | Clock_gate_pwm, |
paul@167 | 615 | Clock_change_enable_pwm, |
paul@167 | 616 | Clock_busy_pwm, |
paul@167 | 617 | Clock_divider_pwm); |
paul@165 | 618 | |
paul@171 | 619 | Clock clock_pwm0(Source(mux_dev, Clock_source_pwm), |
paul@167 | 620 | Clock_gate_pwm, |
paul@167 | 621 | Clock_change_enable_pwm, |
paul@167 | 622 | Clock_busy_pwm, |
paul@167 | 623 | Clock_divider_pwm); |
paul@165 | 624 | |
paul@165 | 625 | Clock clock_pwm1; |
paul@165 | 626 | |
paul@165 | 627 | Clock clock_scc; |
paul@165 | 628 | |
paul@171 | 629 | Clock clock_sfc(Source(mux_dev, Clock_source_sfc), |
paul@167 | 630 | Clock_gate_sfc, |
paul@167 | 631 | Clock_change_enable_sfc, |
paul@167 | 632 | Clock_busy_sfc, |
paul@167 | 633 | Clock_divider_sfc); |
paul@165 | 634 | |
paul@165 | 635 | Clock clock_smb0; |
paul@165 | 636 | |
paul@165 | 637 | Clock clock_smb1; |
paul@165 | 638 | |
paul@165 | 639 | Clock clock_smb2; |
paul@165 | 640 | |
paul@165 | 641 | Clock clock_smb3; |
paul@165 | 642 | |
paul@165 | 643 | Clock clock_smb4; |
paul@165 | 644 | |
paul@171 | 645 | Clock clock_ssi(Source(mux_dev, Clock_source_ssi), |
paul@167 | 646 | Clock_gate_ssi0, |
paul@167 | 647 | Clock_change_enable_ssi, |
paul@167 | 648 | Clock_busy_ssi, |
paul@167 | 649 | Clock_divider_ssi); |
paul@165 | 650 | |
paul@171 | 651 | Clock clock_timer(Source(mux_pclock), Clock_gate_timer); |
paul@165 | 652 | |
paul@171 | 653 | Clock clock_uart0(Source(mux_external), Clock_gate_uart0); |
paul@165 | 654 | |
paul@171 | 655 | Clock clock_uart1(Source(mux_external), Clock_gate_uart1); |
paul@165 | 656 | |
paul@171 | 657 | Clock clock_uart2(Source(mux_external), Clock_gate_uart2); |
paul@165 | 658 | |
paul@171 | 659 | Clock clock_uart3(Source(mux_external), Clock_gate_uart3); |
paul@165 | 660 | |
paul@165 | 661 | Clock clock_udc; |
paul@165 | 662 | |
paul@165 | 663 | Clock clock_uhc; |
paul@165 | 664 | |
paul@165 | 665 | Clock clock_uprt; |
paul@165 | 666 | |
paul@165 | 667 | |
paul@165 | 668 | |
paul@165 | 669 | // Clock register. |
paul@165 | 670 | |
paul@165 | 671 | static Clock_base *clocks[Clock_identifier_count] = { |
paul@165 | 672 | &clock_ahb2_apb, |
paul@165 | 673 | &clock_aic_bitclk, |
paul@165 | 674 | &clock_aic_pclk, |
paul@165 | 675 | &clock_can0, |
paul@165 | 676 | &clock_can1, |
paul@165 | 677 | &clock_cdbus, |
paul@165 | 678 | &clock_cim, |
paul@165 | 679 | &clock_cpu, |
paul@165 | 680 | &clock_ddr, |
paul@165 | 681 | &clock_dma, |
paul@165 | 682 | &clock_emac, |
paul@165 | 683 | &clock_external, |
paul@165 | 684 | &clock_hclock0, |
paul@165 | 685 | &clock_hclock2, |
paul@165 | 686 | &clock_hdmi, |
paul@165 | 687 | &clock_i2c, |
paul@165 | 688 | &clock_i2c0, |
paul@165 | 689 | &clock_i2c1, |
paul@165 | 690 | &clock_i2s, |
paul@165 | 691 | &clock_i2s0_rx, |
paul@165 | 692 | &clock_i2s0_tx, |
paul@165 | 693 | &clock_kbc, |
paul@165 | 694 | &clock_lcd, |
paul@165 | 695 | &clock_lcd_pixel, |
paul@165 | 696 | &clock_mac, |
paul@165 | 697 | &clock_main, |
paul@165 | 698 | &clock_msc, |
paul@165 | 699 | &clock_msc0, |
paul@165 | 700 | &clock_msc1, |
paul@165 | 701 | &clock_none, |
paul@165 | 702 | &clock_pclock, |
paul@165 | 703 | &clock_pll_A, |
paul@165 | 704 | &clock_pll_E, |
paul@165 | 705 | &clock_pll_M, |
paul@165 | 706 | &clock_pwm, |
paul@165 | 707 | &clock_pwm0, |
paul@165 | 708 | &clock_pwm1, |
paul@165 | 709 | &clock_scc, |
paul@165 | 710 | &clock_sfc, |
paul@165 | 711 | &clock_smb0, |
paul@165 | 712 | &clock_smb1, |
paul@165 | 713 | &clock_smb2, |
paul@165 | 714 | &clock_smb3, |
paul@165 | 715 | &clock_smb4, |
paul@165 | 716 | &clock_ssi, |
paul@165 | 717 | &clock_timer, |
paul@165 | 718 | &clock_uart0, |
paul@165 | 719 | &clock_uart1, |
paul@165 | 720 | &clock_uart2, |
paul@165 | 721 | &clock_uart3, |
paul@165 | 722 | &clock_udc, |
paul@165 | 723 | &clock_uhc, |
paul@165 | 724 | &clock_uprt, |
paul@165 | 725 | }; |
paul@165 | 726 | |
paul@165 | 727 | |
paul@165 | 728 | |
paul@165 | 729 | // Register access. |
paul@165 | 730 | |
paul@165 | 731 | Cpm_regs::Cpm_regs(l4_addr_t addr, uint32_t exclk_freq) |
paul@165 | 732 | : exclk_freq(exclk_freq) |
paul@161 | 733 | { |
paul@165 | 734 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@161 | 735 | } |
paul@161 | 736 | |
paul@165 | 737 | // Utility methods. |
paul@165 | 738 | |
paul@165 | 739 | uint32_t |
paul@165 | 740 | Cpm_regs::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@165 | 741 | { |
paul@165 | 742 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@165 | 743 | } |
paul@165 | 744 | |
paul@165 | 745 | void |
paul@165 | 746 | Cpm_regs::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@165 | 747 | { |
paul@165 | 748 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@165 | 749 | } |
paul@165 | 750 | |
paul@165 | 751 | |
paul@165 | 752 | |
paul@166 | 753 | // Field methods. |
paul@166 | 754 | |
paul@166 | 755 | uint32_t |
paul@166 | 756 | Field::get_field(Cpm_regs ®s) |
paul@166 | 757 | { |
paul@166 | 758 | if (defined) |
paul@166 | 759 | return regs.get_field(reg, mask, bit); |
paul@166 | 760 | else |
paul@166 | 761 | return 0; |
paul@166 | 762 | } |
paul@166 | 763 | |
paul@166 | 764 | void |
paul@166 | 765 | Field::set_field(Cpm_regs ®s, uint32_t value) |
paul@166 | 766 | { |
paul@166 | 767 | if (defined) |
paul@166 | 768 | regs.set_field(reg, mask, bit, value); |
paul@166 | 769 | } |
paul@166 | 770 | |
paul@166 | 771 | |
paul@166 | 772 | |
paul@169 | 773 | // Clock sources. |
paul@169 | 774 | |
paul@169 | 775 | enum Clock_identifiers |
paul@169 | 776 | Mux::get_input(int num) |
paul@169 | 777 | { |
paul@169 | 778 | if (num < _num_inputs) |
paul@169 | 779 | return _inputs[num]; |
paul@169 | 780 | else |
paul@169 | 781 | return Clock_undefined; |
paul@169 | 782 | } |
paul@169 | 783 | |
paul@171 | 784 | // Clock sources. |
paul@171 | 785 | |
paul@171 | 786 | uint8_t |
paul@171 | 787 | Source::get_source(Cpm_regs ®s) |
paul@171 | 788 | { |
paul@171 | 789 | if (_source.is_defined()) |
paul@171 | 790 | return _source.get_field(regs); |
paul@171 | 791 | else |
paul@171 | 792 | return 0; |
paul@171 | 793 | } |
paul@171 | 794 | |
paul@171 | 795 | void |
paul@171 | 796 | Source::set_source(Cpm_regs ®s, uint8_t source) |
paul@171 | 797 | { |
paul@171 | 798 | if (!_source.is_defined()) |
paul@171 | 799 | return; |
paul@171 | 800 | |
paul@171 | 801 | _source.set_field(regs, source); |
paul@171 | 802 | } |
paul@171 | 803 | |
paul@169 | 804 | |
paul@169 | 805 | |
paul@165 | 806 | // Clock control. |
paul@165 | 807 | |
paul@165 | 808 | int |
paul@165 | 809 | Clock_base::have_clock(Cpm_regs ®s) |
paul@165 | 810 | { |
paul@165 | 811 | (void) regs; |
paul@165 | 812 | return true; |
paul@165 | 813 | } |
paul@165 | 814 | |
paul@165 | 815 | void |
paul@165 | 816 | Clock_base::start_clock(Cpm_regs ®s) |
paul@165 | 817 | { |
paul@165 | 818 | (void) regs; |
paul@165 | 819 | } |
paul@165 | 820 | |
paul@165 | 821 | void |
paul@165 | 822 | Clock_base::stop_clock(Cpm_regs ®s) |
paul@165 | 823 | { |
paul@165 | 824 | (void) regs; |
paul@165 | 825 | } |
paul@165 | 826 | |
paul@165 | 827 | // Default divider. |
paul@165 | 828 | |
paul@165 | 829 | uint32_t |
paul@165 | 830 | Clock_base::get_divider(Cpm_regs ®s) |
paul@165 | 831 | { |
paul@165 | 832 | (void) regs; |
paul@165 | 833 | return 1; |
paul@165 | 834 | } |
paul@165 | 835 | |
paul@165 | 836 | void |
paul@165 | 837 | Clock_base::set_divider(Cpm_regs ®s, uint32_t division) |
paul@165 | 838 | { |
paul@165 | 839 | (void) regs; |
paul@165 | 840 | (void) division; |
paul@165 | 841 | } |
paul@165 | 842 | |
paul@165 | 843 | // Clock sources. |
paul@165 | 844 | |
paul@165 | 845 | uint8_t |
paul@165 | 846 | Clock_base::get_source(Cpm_regs ®s) |
paul@165 | 847 | { |
paul@171 | 848 | return _source.get_source(regs); |
paul@165 | 849 | } |
paul@165 | 850 | |
paul@165 | 851 | void |
paul@165 | 852 | Clock_base::set_source(Cpm_regs ®s, uint8_t source) |
paul@165 | 853 | { |
paul@171 | 854 | _source.set_source(regs, source); |
paul@165 | 855 | } |
paul@165 | 856 | |
paul@165 | 857 | // Clock source frequencies. |
paul@165 | 858 | |
paul@165 | 859 | uint32_t |
paul@165 | 860 | Clock_base::get_source_frequency(Cpm_regs ®s) |
paul@165 | 861 | { |
paul@165 | 862 | // Return the external clock frequency without any input clock. |
paul@165 | 863 | |
paul@171 | 864 | if (_source.get_number() == 0) |
paul@165 | 865 | return regs.exclk_freq; |
paul@165 | 866 | |
paul@165 | 867 | // Clocks with one source yield that input frequency. |
paul@165 | 868 | |
paul@171 | 869 | else if (_source.get_number() == 1) |
paul@171 | 870 | return clocks[_source.get_input(0)]->get_frequency(regs); |
paul@165 | 871 | |
paul@165 | 872 | // With multiple sources, obtain the selected source for the clock. |
paul@165 | 873 | |
paul@165 | 874 | uint8_t source = get_source(regs); |
paul@171 | 875 | enum Clock_identifiers input = _source.get_input(source); |
paul@165 | 876 | |
paul@165 | 877 | // Return the frequency of the source. |
paul@165 | 878 | |
paul@169 | 879 | if (input != Clock_undefined) |
paul@169 | 880 | return clocks[input]->get_frequency(regs); |
paul@165 | 881 | else |
paul@165 | 882 | return 0; |
paul@165 | 883 | } |
paul@165 | 884 | |
paul@165 | 885 | // Output clock frequencies. |
paul@165 | 886 | |
paul@165 | 887 | uint32_t |
paul@165 | 888 | Clock_base::get_frequency(Cpm_regs ®s) |
paul@165 | 889 | { |
paul@165 | 890 | return get_source_frequency(regs) / get_divider(regs); |
paul@165 | 891 | } |
paul@165 | 892 | |
paul@165 | 893 | |
paul@165 | 894 | |
paul@165 | 895 | // PLL-specific control. |
paul@165 | 896 | |
paul@165 | 897 | int |
paul@165 | 898 | Pll::have_pll(Cpm_regs ®s) |
paul@165 | 899 | { |
paul@168 | 900 | return _stable.get_field(regs); |
paul@165 | 901 | } |
paul@165 | 902 | |
paul@165 | 903 | int |
paul@165 | 904 | Pll::pll_enabled(Cpm_regs ®s) |
paul@165 | 905 | { |
paul@168 | 906 | return _enable.get_field(regs); |
paul@165 | 907 | } |
paul@165 | 908 | |
paul@165 | 909 | int |
paul@165 | 910 | Pll::pll_bypassed(Cpm_regs ®s) |
paul@165 | 911 | { |
paul@168 | 912 | return _bypass.get_field(regs); |
paul@165 | 913 | } |
paul@165 | 914 | |
paul@165 | 915 | // Clock control. |
paul@165 | 916 | |
paul@165 | 917 | int |
paul@165 | 918 | Pll::have_clock(Cpm_regs ®s) |
paul@165 | 919 | { |
paul@165 | 920 | return have_pll(regs) && pll_enabled(regs); |
paul@165 | 921 | } |
paul@165 | 922 | |
paul@165 | 923 | void |
paul@165 | 924 | Pll::start_clock(Cpm_regs ®s) |
paul@165 | 925 | { |
paul@168 | 926 | _enable.set_field(regs, 1); |
paul@165 | 927 | while (!have_pll(regs)); |
paul@165 | 928 | } |
paul@165 | 929 | |
paul@165 | 930 | void |
paul@165 | 931 | Pll::stop_clock(Cpm_regs ®s) |
paul@161 | 932 | { |
paul@168 | 933 | _enable.set_field(regs, 0); |
paul@165 | 934 | while (have_pll(regs)); |
paul@165 | 935 | } |
paul@165 | 936 | |
paul@165 | 937 | // Feedback (13-bit) multiplier. |
paul@165 | 938 | |
paul@165 | 939 | uint16_t |
paul@165 | 940 | Pll::get_multiplier(Cpm_regs ®s) |
paul@165 | 941 | { |
paul@168 | 942 | return _multiplier.get_field(regs) + 1; |
paul@165 | 943 | } |
paul@165 | 944 | |
paul@165 | 945 | void |
paul@165 | 946 | Pll::set_multiplier(Cpm_regs ®s, uint16_t multiplier) |
paul@165 | 947 | { |
paul@168 | 948 | _multiplier.set_field(regs, multiplier - 1); |
paul@165 | 949 | } |
paul@165 | 950 | |
paul@165 | 951 | // Input (6-bit) divider. |
paul@165 | 952 | |
paul@165 | 953 | uint8_t |
paul@165 | 954 | Pll::get_input_division(Cpm_regs ®s) |
paul@165 | 955 | { |
paul@168 | 956 | return _input_division.get_field(regs) + 1; |
paul@165 | 957 | } |
paul@165 | 958 | |
paul@165 | 959 | void |
paul@165 | 960 | Pll::set_input_division(Cpm_regs ®s, uint8_t divider) |
paul@165 | 961 | { |
paul@168 | 962 | _input_division.set_field(regs, divider - 1); |
paul@165 | 963 | } |
paul@165 | 964 | |
paul@165 | 965 | // Output (dual 3-bit) dividers. |
paul@165 | 966 | |
paul@165 | 967 | uint8_t |
paul@165 | 968 | Pll::get_output_division(Cpm_regs ®s) |
paul@165 | 969 | { |
paul@168 | 970 | uint8_t d0 = _output_division0.get_field(regs); |
paul@168 | 971 | uint8_t d1 = _output_division1.get_field(regs); |
paul@165 | 972 | |
paul@165 | 973 | return d0 * d1; |
paul@165 | 974 | } |
paul@165 | 975 | |
paul@165 | 976 | void |
paul@165 | 977 | Pll::set_output_division(Cpm_regs ®s, uint8_t divider) |
paul@165 | 978 | { |
paul@165 | 979 | // Assert 1 as a minimum. |
paul@165 | 980 | // Divider 0 must be less than or equal to divider 1. |
paul@165 | 981 | |
paul@165 | 982 | uint8_t d0 = (uint8_t) floor(sqrt(divider ? divider : 1)); |
paul@165 | 983 | uint8_t d1 = divider / d0; |
paul@165 | 984 | |
paul@168 | 985 | _output_division0.set_field(regs, d0); |
paul@168 | 986 | _output_division1.set_field(regs, d1); |
paul@165 | 987 | } |
paul@165 | 988 | |
paul@165 | 989 | uint32_t |
paul@165 | 990 | Pll::get_frequency(Cpm_regs ®s) |
paul@165 | 991 | { |
paul@165 | 992 | // Test for PLL enable and not PLL bypass. |
paul@165 | 993 | |
paul@165 | 994 | if (pll_enabled(regs)) |
paul@165 | 995 | { |
paul@165 | 996 | if (!pll_bypassed(regs)) |
paul@165 | 997 | return (get_source_frequency(regs) * get_multiplier(regs)) / |
paul@165 | 998 | (get_input_division(regs) * get_output_division(regs)); |
paul@165 | 999 | else |
paul@165 | 1000 | return get_source_frequency(regs); |
paul@165 | 1001 | } |
paul@165 | 1002 | else |
paul@165 | 1003 | return 0; |
paul@165 | 1004 | } |
paul@165 | 1005 | |
paul@165 | 1006 | void |
paul@165 | 1007 | Pll::set_pll_parameters(Cpm_regs ®s, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@165 | 1008 | { |
paul@165 | 1009 | set_multiplier(regs, multiplier); |
paul@165 | 1010 | set_input_division(regs, in_divider); |
paul@165 | 1011 | set_output_division(regs, out_divider); |
paul@161 | 1012 | |
paul@165 | 1013 | if (pll_enabled(regs) && !pll_bypassed(regs)) |
paul@165 | 1014 | while (!have_pll(regs)); |
paul@165 | 1015 | } |
paul@165 | 1016 | |
paul@165 | 1017 | |
paul@165 | 1018 | |
paul@165 | 1019 | // Clock control. |
paul@165 | 1020 | |
paul@165 | 1021 | void |
paul@165 | 1022 | Clock::change_disable(Cpm_regs ®s) |
paul@165 | 1023 | { |
paul@166 | 1024 | if (_change_enable.is_defined()) |
paul@166 | 1025 | _change_enable.set_field(regs, 0); |
paul@165 | 1026 | } |
paul@165 | 1027 | |
paul@165 | 1028 | void |
paul@165 | 1029 | Clock::change_enable(Cpm_regs ®s) |
paul@165 | 1030 | { |
paul@166 | 1031 | if (_change_enable.is_defined()) |
paul@166 | 1032 | _change_enable.set_field(regs, 1); |
paul@165 | 1033 | } |
paul@165 | 1034 | |
paul@165 | 1035 | int |
paul@165 | 1036 | Clock::have_clock(Cpm_regs ®s) |
paul@165 | 1037 | { |
paul@166 | 1038 | if (_gate.is_defined()) |
paul@166 | 1039 | return !_gate.get_field(regs); |
paul@165 | 1040 | else |
paul@165 | 1041 | return true; |
paul@165 | 1042 | } |
paul@165 | 1043 | |
paul@165 | 1044 | void |
paul@165 | 1045 | Clock::start_clock(Cpm_regs ®s) |
paul@165 | 1046 | { |
paul@166 | 1047 | if (_gate.is_defined()) |
paul@166 | 1048 | _gate.set_field(regs, 0); |
paul@165 | 1049 | } |
paul@165 | 1050 | |
paul@165 | 1051 | void |
paul@165 | 1052 | Clock::stop_clock(Cpm_regs ®s) |
paul@165 | 1053 | { |
paul@166 | 1054 | if (_gate.is_defined()) |
paul@166 | 1055 | _gate.set_field(regs, 1); |
paul@165 | 1056 | } |
paul@165 | 1057 | |
paul@165 | 1058 | void |
paul@165 | 1059 | Clock::wait_busy(Cpm_regs ®s) |
paul@165 | 1060 | { |
paul@166 | 1061 | if (_busy.is_defined()) |
paul@166 | 1062 | while (_busy.get_field(regs)); |
paul@165 | 1063 | } |
paul@165 | 1064 | |
paul@165 | 1065 | |
paul@165 | 1066 | |
paul@165 | 1067 | // Clock dividers. |
paul@165 | 1068 | |
paul@165 | 1069 | uint32_t |
paul@165 | 1070 | Clock::get_divider(Cpm_regs ®s) |
paul@165 | 1071 | { |
paul@166 | 1072 | if (_divider.is_defined()) |
paul@166 | 1073 | return _divider.get_field(regs) + 1; |
paul@165 | 1074 | else |
paul@165 | 1075 | return 1; |
paul@165 | 1076 | } |
paul@165 | 1077 | |
paul@165 | 1078 | void |
paul@165 | 1079 | Clock::set_divider(Cpm_regs ®s, uint32_t division) |
paul@165 | 1080 | { |
paul@170 | 1081 | if (!_divider.is_defined()) |
paul@165 | 1082 | return; |
paul@165 | 1083 | |
paul@165 | 1084 | change_enable(regs); |
paul@166 | 1085 | _divider.set_field(regs, division - 1); |
paul@165 | 1086 | wait_busy(regs); |
paul@165 | 1087 | change_disable(regs); |
paul@165 | 1088 | } |
paul@165 | 1089 | |
paul@165 | 1090 | void |
paul@165 | 1091 | Clock::set_source(Cpm_regs ®s, uint8_t source) |
paul@165 | 1092 | { |
paul@165 | 1093 | change_enable(regs); |
paul@165 | 1094 | Clock_base::set_source(regs, source); |
paul@165 | 1095 | wait_busy(regs); |
paul@165 | 1096 | change_disable(regs); |
paul@161 | 1097 | } |
paul@161 | 1098 | |
paul@161 | 1099 | |
paul@161 | 1100 | |
paul@160 | 1101 | // If implemented as a Hw::Device, various properties would be |
paul@160 | 1102 | // initialised in the constructor and obtained from the device tree |
paul@160 | 1103 | // definitions. |
paul@160 | 1104 | |
paul@160 | 1105 | Cpm_x1600_chip::Cpm_x1600_chip(l4_addr_t addr, uint32_t exclk_freq) |
paul@165 | 1106 | : _cpm_regs(addr, exclk_freq) |
paul@160 | 1107 | { |
paul@160 | 1108 | // add_cid("cpm"); |
paul@160 | 1109 | // add_cid("cpm-x1600"); |
paul@165 | 1110 | // register_property("exclk_freq", &exclk_freq); |
paul@161 | 1111 | } |
paul@160 | 1112 | |
paul@161 | 1113 | int |
paul@161 | 1114 | Cpm_x1600_chip::have_clock(enum Clock_identifiers clock) |
paul@161 | 1115 | { |
paul@165 | 1116 | return clocks[clock]->have_clock(_cpm_regs); |
paul@161 | 1117 | } |
paul@161 | 1118 | |
paul@161 | 1119 | void |
paul@161 | 1120 | Cpm_x1600_chip::start_clock(enum Clock_identifiers clock) |
paul@160 | 1121 | { |
paul@165 | 1122 | clocks[clock]->start_clock(_cpm_regs); |
paul@161 | 1123 | } |
paul@161 | 1124 | |
paul@161 | 1125 | void |
paul@161 | 1126 | Cpm_x1600_chip::stop_clock(enum Clock_identifiers clock) |
paul@161 | 1127 | { |
paul@165 | 1128 | clocks[clock]->stop_clock(_cpm_regs); |
paul@160 | 1129 | } |
paul@160 | 1130 | |
paul@161 | 1131 | uint32_t |
paul@161 | 1132 | Cpm_x1600_chip::get_divider(enum Clock_identifiers clock) |
paul@160 | 1133 | { |
paul@165 | 1134 | return clocks[clock]->get_divider(_cpm_regs); |
paul@160 | 1135 | } |
paul@160 | 1136 | |
paul@161 | 1137 | void |
paul@161 | 1138 | Cpm_x1600_chip::set_divider(enum Clock_identifiers clock, uint32_t division) |
paul@160 | 1139 | { |
paul@165 | 1140 | clocks[clock]->set_divider(_cpm_regs, division); |
paul@160 | 1141 | } |
paul@160 | 1142 | |
paul@160 | 1143 | uint8_t |
paul@161 | 1144 | Cpm_x1600_chip::get_source(enum Clock_identifiers clock) |
paul@160 | 1145 | { |
paul@165 | 1146 | return clocks[clock]->get_source(_cpm_regs); |
paul@160 | 1147 | } |
paul@160 | 1148 | |
paul@160 | 1149 | void |
paul@161 | 1150 | Cpm_x1600_chip::set_source(enum Clock_identifiers clock, uint8_t source) |
paul@160 | 1151 | { |
paul@165 | 1152 | clocks[clock]->set_source(_cpm_regs, source); |
paul@160 | 1153 | } |
paul@160 | 1154 | |
paul@161 | 1155 | uint32_t |
paul@161 | 1156 | Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock) |
paul@160 | 1157 | { |
paul@165 | 1158 | return clocks[clock]->get_source_frequency(_cpm_regs); |
paul@160 | 1159 | } |
paul@160 | 1160 | |
paul@160 | 1161 | uint32_t |
paul@160 | 1162 | Cpm_x1600_chip::get_frequency(enum Clock_identifiers clock) |
paul@160 | 1163 | { |
paul@165 | 1164 | return clocks[clock]->get_frequency(_cpm_regs); |
paul@160 | 1165 | } |
paul@160 | 1166 | |
paul@160 | 1167 | void |
paul@160 | 1168 | Cpm_x1600_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 1169 | { |
paul@160 | 1170 | switch (clock) |
paul@160 | 1171 | { |
paul@160 | 1172 | // The pixel frequency is based on the selected clock source (SCLK_A, MPLL or |
paul@160 | 1173 | // EPLL). |
paul@160 | 1174 | |
paul@160 | 1175 | case Clock_lcd_pixel: |
paul@165 | 1176 | { |
paul@160 | 1177 | |
paul@160 | 1178 | // Switch to the MPLL and attempt to set the divider. |
paul@160 | 1179 | |
paul@165 | 1180 | Clock_base *lcd = clocks[Clock_lcd_pixel]; |
paul@165 | 1181 | Clock_base *pll = clocks[Clock_pll_M]; |
paul@165 | 1182 | |
paul@165 | 1183 | lcd->set_source(_cpm_regs, Source_mME_pll_M); |
paul@165 | 1184 | pll->start_clock(_cpm_regs); |
paul@165 | 1185 | lcd->set_divider(_cpm_regs, lcd->get_source_frequency(_cpm_regs) / frequency); |
paul@160 | 1186 | break; |
paul@165 | 1187 | } |
paul@160 | 1188 | |
paul@160 | 1189 | default: |
paul@160 | 1190 | break; |
paul@160 | 1191 | } |
paul@160 | 1192 | } |
paul@160 | 1193 | |
paul@165 | 1194 | void |
paul@165 | 1195 | Cpm_x1600_chip::set_pll_parameters(enum Clock_identifiers clock, uint16_t multiplier, |
paul@165 | 1196 | uint8_t in_divider, uint8_t out_divider) |
paul@165 | 1197 | { |
paul@165 | 1198 | Pll *pll = dynamic_cast<Pll *>(clocks[clock]); |
paul@165 | 1199 | |
paul@165 | 1200 | pll->set_pll_parameters(_cpm_regs, multiplier, in_divider, out_divider); |
paul@165 | 1201 | } |
paul@165 | 1202 | |
paul@160 | 1203 | |
paul@160 | 1204 | |
paul@160 | 1205 | // C language interface functions. |
paul@160 | 1206 | |
paul@160 | 1207 | void |
paul@160 | 1208 | *x1600_cpm_init(l4_addr_t cpm_base) |
paul@160 | 1209 | { |
paul@160 | 1210 | /* Initialise the clock and power management peripheral with the |
paul@160 | 1211 | register memory region and a 24MHz EXCLK frequency. */ |
paul@160 | 1212 | |
paul@160 | 1213 | return (void *) new Cpm_x1600_chip(cpm_base, 24000000); |
paul@160 | 1214 | } |
paul@160 | 1215 | |
paul@160 | 1216 | int |
paul@160 | 1217 | x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1218 | { |
paul@160 | 1219 | return static_cast<Cpm_x1600_chip *>(cpm)->have_clock(clock); |
paul@160 | 1220 | } |
paul@160 | 1221 | |
paul@160 | 1222 | void |
paul@160 | 1223 | x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1224 | { |
paul@160 | 1225 | static_cast<Cpm_x1600_chip *>(cpm)->start_clock(clock); |
paul@160 | 1226 | } |
paul@160 | 1227 | |
paul@160 | 1228 | void |
paul@160 | 1229 | x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1230 | { |
paul@160 | 1231 | static_cast<Cpm_x1600_chip *>(cpm)->stop_clock(clock); |
paul@160 | 1232 | } |
paul@160 | 1233 | |
paul@161 | 1234 | uint32_t |
paul@161 | 1235 | x1600_cpm_get_divider(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1236 | { |
paul@161 | 1237 | return static_cast<Cpm_x1600_chip *>(cpm)->get_divider(clock); |
paul@160 | 1238 | } |
paul@160 | 1239 | |
paul@161 | 1240 | void |
paul@161 | 1241 | x1600_cpm_set_divider(void *cpm, enum Clock_identifiers clock, uint32_t divider) |
paul@160 | 1242 | { |
paul@161 | 1243 | return static_cast<Cpm_x1600_chip *>(cpm)->set_divider(clock, divider); |
paul@160 | 1244 | } |
paul@160 | 1245 | |
paul@160 | 1246 | uint8_t |
paul@161 | 1247 | x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1248 | { |
paul@161 | 1249 | return static_cast<Cpm_x1600_chip *>(cpm)->get_source(clock); |
paul@160 | 1250 | } |
paul@160 | 1251 | |
paul@160 | 1252 | void |
paul@161 | 1253 | x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) |
paul@160 | 1254 | { |
paul@161 | 1255 | static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source); |
paul@160 | 1256 | } |
paul@160 | 1257 | |
paul@160 | 1258 | uint32_t |
paul@161 | 1259 | x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1260 | { |
paul@161 | 1261 | return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock); |
paul@160 | 1262 | } |
paul@160 | 1263 | |
paul@160 | 1264 | uint32_t |
paul@160 | 1265 | x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1266 | { |
paul@160 | 1267 | return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock); |
paul@160 | 1268 | } |
paul@160 | 1269 | |
paul@160 | 1270 | void |
paul@160 | 1271 | x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 1272 | { |
paul@160 | 1273 | static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency); |
paul@160 | 1274 | } |
paul@160 | 1275 | |
paul@160 | 1276 | void |
paul@160 | 1277 | x1600_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@160 | 1278 | { |
paul@165 | 1279 | static_cast<Cpm_x1600_chip *>(cpm)->set_pll_parameters(Clock_pll_M, multiplier, in_divider, out_divider); |
paul@160 | 1280 | } |