paul@0 | 1 | /* |
paul@0 | 2 | * LCD peripheral support for the JZ4740 and related SoCs. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> |
paul@64 | 5 | * Copyright (C) 2015, 2016, 2017, 2018, |
paul@64 | 6 | * 2020 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 7 | * |
paul@0 | 8 | * This program is free software; you can redistribute it and/or |
paul@0 | 9 | * modify it under the terms of the GNU General Public License as |
paul@0 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 11 | * the License, or (at your option) any later version. |
paul@0 | 12 | * |
paul@0 | 13 | * This program is distributed in the hope that it will be useful, |
paul@0 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 16 | * GNU General Public License for more details. |
paul@0 | 17 | * |
paul@0 | 18 | * You should have received a copy of the GNU General Public License |
paul@0 | 19 | * along with this program; if not, write to the Free Software |
paul@0 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 21 | * Boston, MA 02110-1301, USA |
paul@0 | 22 | */ |
paul@0 | 23 | |
paul@0 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@0 | 25 | #include <l4/sys/cache.h> |
paul@69 | 26 | #include <l4/sys/irq.h> |
paul@0 | 27 | #include <l4/sys/types.h> |
paul@69 | 28 | #include <l4/util/util.h> |
paul@0 | 29 | |
paul@0 | 30 | #include "lcd-jz4740.h" |
paul@0 | 31 | #include "lcd-jz4740-config.h" |
paul@0 | 32 | |
paul@0 | 33 | #include <stdint.h> |
paul@0 | 34 | |
paul@0 | 35 | enum Regs : unsigned |
paul@0 | 36 | { |
paul@0 | 37 | Lcd_config = 0x000, // LCD_CFG |
paul@0 | 38 | Lcd_vsync = 0x004, // LCD_VSYNC |
paul@0 | 39 | Lcd_hsync = 0x008, // LCD_HSYNC |
paul@69 | 40 | Virtual_area = 0x00c, // LCD_VAT |
paul@0 | 41 | Display_hlimits = 0x010, // LCD_DAH |
paul@0 | 42 | Display_vlimits = 0x014, // LCD_DAV |
paul@0 | 43 | Lcd_ps = 0x018, // LCD_PS |
paul@0 | 44 | Lcd_cls = 0x01c, // LCD_CLS |
paul@0 | 45 | Lcd_spl = 0x020, // LCD_SPL |
paul@0 | 46 | Lcd_rev = 0x024, // LCD_REV |
paul@0 | 47 | Lcd_control = 0x030, // LCD_CTRL |
paul@0 | 48 | Lcd_status = 0x034, // LCD_STATE |
paul@0 | 49 | Lcd_irq_id = 0x038, // LCD_IID |
paul@0 | 50 | Desc_address_0 = 0x040, // LCD_DA0 |
paul@0 | 51 | Source_address_0 = 0x044, // LCD_SA0 |
paul@0 | 52 | Frame_id_0 = 0x048, // LCD_FID0 |
paul@0 | 53 | Command_0 = 0x04c, // LCD_CMD0 |
paul@72 | 54 | Counter_position_0 = 0x068, // LCD_CPOS0 |
paul@72 | 55 | Foreground_size_0 = 0x06c, // LCD_DESSIZE0 |
paul@0 | 56 | Desc_address_1 = 0x050, // LCD_DA1 |
paul@0 | 57 | Source_address_1 = 0x054, // LCD_SA1 |
paul@0 | 58 | Frame_id_1 = 0x058, // LCD_FID1 |
paul@0 | 59 | Command_1 = 0x05c, // LCD_CMD1 |
paul@72 | 60 | Counter_position_1 = 0x078, // LCD_CPOS1 |
paul@72 | 61 | Foreground_size_1 = 0x07c, // LCD_DESSIZE1 |
paul@69 | 62 | Rgb_control = 0x090, // LCD_RGBC (JZ4780) |
paul@72 | 63 | Alpha_levels = 0x108, // LCD_ALPHA (JZ4780) |
paul@69 | 64 | Priority_level = 0x2c0, // LCD_PCFG |
paul@69 | 65 | |
paul@69 | 66 | // OSD registers. |
paul@69 | 67 | |
paul@69 | 68 | Osd_config = 0x100, // LCD_OSDC |
paul@69 | 69 | Osd_control = 0x104, // LCD_OSDCTRL |
paul@69 | 70 | Osd_status = 0x108, // LCD_OSDS |
paul@0 | 71 | }; |
paul@0 | 72 | |
paul@0 | 73 | // Lcd_config descriptions. |
paul@0 | 74 | |
paul@0 | 75 | enum Config_values : unsigned |
paul@0 | 76 | { |
paul@0 | 77 | Config_stn_pins_mask = 0x3, |
paul@0 | 78 | Config_mode_mask = 0xf, |
paul@0 | 79 | }; |
paul@0 | 80 | |
paul@0 | 81 | // Field positions for registers employing two values, with the first typically |
paul@0 | 82 | // being the start value and the second being an end value. |
paul@0 | 83 | |
paul@0 | 84 | enum Value_pair_bits : unsigned |
paul@0 | 85 | { |
paul@0 | 86 | Value_first = 16, |
paul@0 | 87 | Value_second = 0, |
paul@0 | 88 | }; |
paul@0 | 89 | |
paul@69 | 90 | // Virtual area bits. |
paul@0 | 91 | |
paul@69 | 92 | enum Virtual_area_values : unsigned |
paul@0 | 93 | { |
paul@69 | 94 | Virtual_area_horizontal_size = Value_first, // sum of display and blank regions (dot/pixel clock periods) |
paul@69 | 95 | Virtual_area_vertical_size = Value_second, // sum of display and blank regions (line periods) |
paul@0 | 96 | }; |
paul@0 | 97 | |
paul@0 | 98 | // Lcd_control descriptions. |
paul@0 | 99 | |
paul@0 | 100 | enum Control_bits : unsigned |
paul@0 | 101 | { |
paul@64 | 102 | Control_pin_modify = 31, // PINMD (change pin usage from 15..0 to 17..10, 8..1) |
paul@64 | 103 | Control_burst_length = 28, // BST (burst length selection) |
paul@64 | 104 | Control_rgb_mode = 27, // RGB (RGB mode) |
paul@64 | 105 | Control_out_underrun = 26, // OFUP (output FIFO underrun protection) |
paul@64 | 106 | Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection) |
paul@64 | 107 | Control_palette_delay = 16, // PDD (load palette delay counter) |
paul@64 | 108 | Control_dac_loopback_test = 14, // DACTE (DAC loopback test) |
paul@64 | 109 | Control_frame_end_irq_enable = 13, // EOFM (end of frame interrupt enable) |
paul@64 | 110 | Control_frame_start_irq_enable = 12, // SOFM (start of frame interrupt enable) |
paul@64 | 111 | Control_out_underrun_irq_enable = 11, // OFUM (output FIFO underrun interrupt enable) |
paul@64 | 112 | Control_in0_underrun_irq_enable = 10, // IFUM0 (input FIFO 0 underrun interrupt enable) |
paul@64 | 113 | Control_in1_underrun_irq_enable = 9, // IFUM1 (input FIFO 1 underrun interrupt enable) |
paul@64 | 114 | Control_disabled_irq_enable = 8, // LDDM (LCD disable done interrupt enable) |
paul@64 | 115 | Control_quick_disabled_irq_enable = 7, // QDM (LCD quick disable done interrupt enable) |
paul@64 | 116 | Control_endian_select = 6, // BEDN (endian selection) |
paul@64 | 117 | Control_bit_order = 5, // PEDN (bit order in bytes) |
paul@64 | 118 | Control_disable = 4, // DIS (disable controller) |
paul@64 | 119 | Control_enable = 3, // ENA (enable controller) |
paul@64 | 120 | Control_bpp = 0, // BPP (bits per pixel) |
paul@0 | 121 | }; |
paul@0 | 122 | |
paul@0 | 123 | enum Burst_length_values : unsigned |
paul@0 | 124 | { |
paul@0 | 125 | Burst_length_4 = 0, // 4 word |
paul@0 | 126 | Burst_length_8 = 1, // 8 word |
paul@0 | 127 | Burst_length_16 = 2, // 16 word |
paul@0 | 128 | |
paul@0 | 129 | // JZ4780 extensions. |
paul@0 | 130 | |
paul@0 | 131 | Burst_length_32 = 3, // 32 word |
paul@0 | 132 | Burst_length_64 = 4, // 64 word |
paul@0 | 133 | Burst_length_mask = 0x7, |
paul@0 | 134 | }; |
paul@0 | 135 | |
paul@0 | 136 | enum Rgb_mode_values : unsigned |
paul@0 | 137 | { |
paul@0 | 138 | Rgb_mode_565 = 0, |
paul@0 | 139 | Rgb_mode_555 = 1, |
paul@0 | 140 | Rgb_mode_mask = 0x1, |
paul@0 | 141 | }; |
paul@0 | 142 | |
paul@0 | 143 | enum Frc_algorithm_values : unsigned |
paul@0 | 144 | { |
paul@0 | 145 | Frc_greyscales_16 = 0, |
paul@0 | 146 | Frc_greyscales_4 = 1, |
paul@0 | 147 | Frc_greyscales_2 = 2, |
paul@0 | 148 | Frc_greyscales_mask = 0x3, |
paul@0 | 149 | }; |
paul@0 | 150 | |
paul@0 | 151 | enum Control_bpp_values : unsigned |
paul@0 | 152 | { |
paul@0 | 153 | Control_bpp_1bpp = 0, |
paul@0 | 154 | Control_bpp_2bpp = 1, |
paul@0 | 155 | Control_bpp_4bpp = 2, |
paul@0 | 156 | Control_bpp_8bpp = 3, |
paul@0 | 157 | Control_bpp_15bpp = 4, |
paul@0 | 158 | Control_bpp_16bpp = 4, |
paul@0 | 159 | Control_bpp_18bpp = 5, |
paul@0 | 160 | Control_bpp_24bpp = 5, |
paul@0 | 161 | Control_bpp_24bpp_comp = 6, |
paul@0 | 162 | Control_bpp_30bpp = 7, |
paul@0 | 163 | Control_bpp_32bpp = 7, |
paul@0 | 164 | Control_bpp_mask = 0x7, |
paul@0 | 165 | }; |
paul@0 | 166 | |
paul@0 | 167 | // Command descriptions. |
paul@0 | 168 | |
paul@0 | 169 | enum Command_bits : unsigned |
paul@0 | 170 | { |
paul@0 | 171 | Command_frame_start_irq = 31, // SOFINT (start of frame interrupt) |
paul@0 | 172 | Command_frame_end_irq = 30, // EOFINT (end of frame interrupt) |
paul@0 | 173 | Command_lcm_command = 29, // JZ4780: CMD (LCM command/data via DMA0) |
paul@0 | 174 | Command_palette_buffer = 28, // PAL (descriptor references palette, not display data) |
paul@0 | 175 | Command_frame_compressed = 27, // JZ4780: COMPEN (16/24bpp compression enabled) |
paul@0 | 176 | Command_frame_enable = 26, // JZ4780: FRM_EN |
paul@0 | 177 | Command_field_even = 25, // JZ4780: FIELD_SEL (interlace even field) |
paul@0 | 178 | Command_16x16_block = 24, // JZ4780: 16x16BLOCK (fetch data by 16x16 block) |
paul@0 | 179 | Command_buffer_length = 0, // LEN |
paul@0 | 180 | }; |
paul@0 | 181 | |
paul@0 | 182 | enum Command_values : unsigned |
paul@0 | 183 | { |
paul@0 | 184 | Command_buffer_length_mask = 0x00ffffff, |
paul@0 | 185 | }; |
paul@0 | 186 | |
paul@69 | 187 | // Status descriptions. |
paul@69 | 188 | |
paul@69 | 189 | enum Status_bits : unsigned |
paul@69 | 190 | { |
paul@69 | 191 | Status_frame_end_irq = 5, |
paul@69 | 192 | Status_frame_start_irq = 4, |
paul@72 | 193 | Status_out_underrun_irq = 3, |
paul@72 | 194 | Status_in0_underrun_irq = 2, |
paul@72 | 195 | Status_in1_underrun_irq = 1, |
paul@69 | 196 | Status_disabled = 0, |
paul@69 | 197 | }; |
paul@69 | 198 | |
paul@69 | 199 | // OSD configuration bits (JZ4780). |
paul@69 | 200 | |
paul@69 | 201 | enum Osd_config_bits : unsigned |
paul@69 | 202 | { |
paul@72 | 203 | Osd_config_fg1_pixel_alpha_enable = 17, |
paul@69 | 204 | Osd_config_fg1_frame_start_irq_enable = 15, |
paul@69 | 205 | Osd_config_fg1_frame_end_irq_enable = 14, |
paul@69 | 206 | Osd_config_fg0_frame_start_irq_enable = 11, |
paul@69 | 207 | Osd_config_fg0_frame_end_irq_enable = 10, |
paul@72 | 208 | Osd_config_fg1_enable = 4, |
paul@72 | 209 | Osd_config_fg0_enable = 3, |
paul@72 | 210 | Osd_config_alpha_enable = 2, |
paul@72 | 211 | Osd_config_fg0_pixel_alpha_enable = 1, |
paul@69 | 212 | Osd_config_enable = 0, |
paul@69 | 213 | }; |
paul@69 | 214 | |
paul@72 | 215 | enum Osd_control_bits : unsigned |
paul@72 | 216 | { |
paul@72 | 217 | Osd_control_ipu_clock_enable = 15, |
paul@72 | 218 | }; |
paul@72 | 219 | |
paul@69 | 220 | // RGB control (JZ4780). |
paul@69 | 221 | |
paul@69 | 222 | enum Rgb_control_bits : unsigned |
paul@69 | 223 | { |
paul@69 | 224 | Rgb_data_padded = 15, // RGBDM |
paul@69 | 225 | Rgb_padding_mode = 14, // DMM |
paul@69 | 226 | Rgb_422 = 8, // 422 |
paul@69 | 227 | Rgb_format_enable = 7, // RGBFMT |
paul@69 | 228 | Rgb_odd_line = 4, // OddRGB |
paul@69 | 229 | Rgb_even_line = 0, // EvenRGB |
paul@69 | 230 | }; |
paul@69 | 231 | |
paul@69 | 232 | enum Rgb_control_values : unsigned |
paul@69 | 233 | { |
paul@69 | 234 | Rgb_padding_end = 0U << Rgb_padding_mode, |
paul@69 | 235 | Rgb_padding_start = 1U << Rgb_padding_mode, |
paul@69 | 236 | Rgb_odd_line_rgb = 0U << Rgb_odd_line, |
paul@69 | 237 | Rgb_odd_line_rbg = 1U << Rgb_odd_line, |
paul@69 | 238 | Rgb_odd_line_grb = 2U << Rgb_odd_line, |
paul@69 | 239 | Rgb_odd_line_gbr = 3U << Rgb_odd_line, |
paul@69 | 240 | Rgb_odd_line_brg = 4U << Rgb_odd_line, |
paul@69 | 241 | Rgb_odd_line_bgr = 5U << Rgb_odd_line, |
paul@69 | 242 | Rgb_even_line_rgb = 0U << Rgb_even_line, |
paul@69 | 243 | Rgb_even_line_rbg = 1U << Rgb_even_line, |
paul@69 | 244 | Rgb_even_line_grb = 2U << Rgb_even_line, |
paul@69 | 245 | Rgb_even_line_gbr = 3U << Rgb_even_line, |
paul@69 | 246 | Rgb_even_line_brg = 4U << Rgb_even_line, |
paul@69 | 247 | Rgb_even_line_bgr = 5U << Rgb_even_line, |
paul@69 | 248 | }; |
paul@69 | 249 | |
paul@72 | 250 | // Alpha levels (JZ4780). |
paul@72 | 251 | |
paul@72 | 252 | enum Alpha_levels_bits : unsigned |
paul@72 | 253 | { |
paul@72 | 254 | Alpha_level_fg1 = 8, |
paul@72 | 255 | Alpha_level_fg0 = 0, |
paul@72 | 256 | }; |
paul@72 | 257 | |
paul@72 | 258 | enum Alpha_levels_values : unsigned |
paul@72 | 259 | { |
paul@72 | 260 | Alpha_level_fg1_mask = 0x0000ff00, |
paul@72 | 261 | Alpha_level_fg0_mask = 0x000000ff, |
paul@72 | 262 | }; |
paul@72 | 263 | |
paul@69 | 264 | // Priority level. |
paul@69 | 265 | |
paul@69 | 266 | enum Priority_level_bits : unsigned |
paul@69 | 267 | { |
paul@69 | 268 | Priority_mode = 31, |
paul@69 | 269 | Priority_highest_burst = 28, |
paul@69 | 270 | Priority_threshold2 = 18, |
paul@69 | 271 | Priority_threshold1 = 9, |
paul@69 | 272 | Priority_threshold0 = 0, |
paul@69 | 273 | }; |
paul@69 | 274 | |
paul@69 | 275 | enum Priority_level_values : unsigned |
paul@69 | 276 | { |
paul@69 | 277 | Priority_mode_dynamic = 0U << Priority_mode, |
paul@69 | 278 | Priority_mode_arbiter = 1U << Priority_mode, |
paul@69 | 279 | }; |
paul@69 | 280 | |
paul@69 | 281 | enum Priority_burst_values : unsigned |
paul@69 | 282 | { |
paul@69 | 283 | Priority_burst_4 = 0, |
paul@69 | 284 | Priority_burst_8 = 1, |
paul@69 | 285 | Priority_burst_16 = 2, |
paul@69 | 286 | Priority_burst_32 = 3, |
paul@69 | 287 | Priority_burst_64 = 4, |
paul@69 | 288 | Priority_burst_16_cont = 5, |
paul@69 | 289 | Priority_burst_disable = 7, |
paul@69 | 290 | }; |
paul@69 | 291 | |
paul@69 | 292 | // Position descriptor member. |
paul@69 | 293 | |
paul@69 | 294 | enum Position_bits : unsigned |
paul@69 | 295 | { |
paul@69 | 296 | Position_bpp = 27, |
paul@69 | 297 | Position_premultiply_lcd = 26, |
paul@69 | 298 | Position_coefficient = 24, |
paul@69 | 299 | Position_y_position = 12, |
paul@69 | 300 | Position_x_position = 0, |
paul@69 | 301 | }; |
paul@69 | 302 | |
paul@69 | 303 | enum Position_values : unsigned |
paul@69 | 304 | { |
paul@69 | 305 | Position_bpp_15_16bpp = 4, |
paul@69 | 306 | Position_bpp_18_24bpp = 5, |
paul@69 | 307 | Position_bpp_30bpp = 7, |
paul@69 | 308 | }; |
paul@69 | 309 | |
paul@0 | 310 | |
paul@0 | 311 | |
paul@0 | 312 | // Utility functions. |
paul@0 | 313 | |
paul@0 | 314 | // Round values up according to the resolution. |
paul@0 | 315 | |
paul@0 | 316 | static uint32_t align(uint32_t value, uint32_t resolution) |
paul@0 | 317 | { |
paul@0 | 318 | return (value + (resolution - 1)) & ~(resolution - 1); |
paul@0 | 319 | } |
paul@0 | 320 | |
paul@0 | 321 | // Value pair encoding. |
paul@0 | 322 | |
paul@0 | 323 | static uint32_t encode_pair(uint32_t start, uint32_t end) |
paul@0 | 324 | { |
paul@0 | 325 | return (start << Value_first) | (end << Value_second); |
paul@0 | 326 | } |
paul@0 | 327 | |
paul@0 | 328 | // RGB conversions. |
paul@0 | 329 | |
paul@0 | 330 | static uint16_t rgb8_to_rgb16(uint8_t rgb) |
paul@0 | 331 | { |
paul@0 | 332 | return ((((rgb & 0xe0) >> 5) * 4) << 11) | ((((rgb & 0x1c) >> 2) * 9) << 6) | ((rgb & 0x03) * 10); |
paul@0 | 333 | } |
paul@0 | 334 | |
paul@0 | 335 | static uint16_t rgb4_to_rgb16(uint8_t rgb) |
paul@0 | 336 | { |
paul@0 | 337 | return ((((rgb & 8) >> 3) * 0x1f) << 11) | ((((rgb & 6) >> 1) * 0x15) << 5) | ((rgb & 1) * 0x1f); |
paul@0 | 338 | } |
paul@0 | 339 | |
paul@0 | 340 | |
paul@0 | 341 | |
paul@0 | 342 | |
paul@0 | 343 | // If implemented as a Hw::Device, various properties would be |
paul@0 | 344 | // initialised in the constructor and obtained from the device tree |
paul@0 | 345 | // definitions. |
paul@0 | 346 | |
paul@0 | 347 | Lcd_jz4740_chip::Lcd_jz4740_chip(l4_addr_t addr, Jz4740_lcd_panel *panel) |
paul@0 | 348 | : _panel(panel) |
paul@0 | 349 | { |
paul@0 | 350 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@72 | 351 | _burst_size = 64; // 64-word burst size (JZ4780) |
paul@72 | 352 | //_burst_size = 16; // 16-word burst size |
paul@0 | 353 | } |
paul@0 | 354 | |
paul@0 | 355 | struct Jz4740_lcd_panel * |
paul@0 | 356 | Lcd_jz4740_chip::get_panel() |
paul@0 | 357 | { |
paul@0 | 358 | return _panel; |
paul@0 | 359 | } |
paul@0 | 360 | |
paul@0 | 361 | void |
paul@0 | 362 | Lcd_jz4740_chip::disable() |
paul@0 | 363 | { |
paul@0 | 364 | // Set the disable bit for normal shutdown. |
paul@0 | 365 | |
paul@69 | 366 | _regs[Lcd_control] = _regs[Lcd_control] | (1U << Control_disable); |
paul@0 | 367 | } |
paul@0 | 368 | |
paul@0 | 369 | void |
paul@0 | 370 | Lcd_jz4740_chip::disable_quick() |
paul@0 | 371 | { |
paul@0 | 372 | // Clear the enable bit for quick shutdown. |
paul@0 | 373 | |
paul@69 | 374 | _regs[Lcd_control] = _regs[Lcd_control] & ~(1U << Control_enable); |
paul@0 | 375 | } |
paul@0 | 376 | |
paul@0 | 377 | void |
paul@0 | 378 | Lcd_jz4740_chip::enable() |
paul@0 | 379 | { |
paul@0 | 380 | // Clear the disable bit and set the enable bit. |
paul@69 | 381 | // JZ4780: OSD status set. |
paul@0 | 382 | |
paul@69 | 383 | _regs[Osd_status] = 0; |
paul@69 | 384 | _regs[Lcd_status] = 0; |
paul@69 | 385 | _regs[Lcd_control] = (_regs[Lcd_control] & ~(1U << Control_disable)) | (1U << Control_enable); |
paul@69 | 386 | } |
paul@69 | 387 | |
paul@69 | 388 | bool |
paul@69 | 389 | Lcd_jz4740_chip::enabled() |
paul@69 | 390 | { |
paul@69 | 391 | return !(_regs[Lcd_status] & (1U << Status_disabled)); |
paul@0 | 392 | } |
paul@0 | 393 | |
paul@0 | 394 | // Calculate and return the pixel clock frequency. |
paul@0 | 395 | |
paul@0 | 396 | int |
paul@0 | 397 | Lcd_jz4740_chip::get_pixel_clock() |
paul@0 | 398 | { |
paul@0 | 399 | int pclk, multiplier; |
paul@0 | 400 | |
paul@0 | 401 | // Serial mode: 3 pixel clock cycles per pixel (one per channel). |
paul@0 | 402 | // Parallel mode: 1 pixel clock cycle per pixel. |
paul@0 | 403 | |
paul@0 | 404 | multiplier = have_serial_tft() ? 3 : 1; |
paul@0 | 405 | |
paul@0 | 406 | // Derive pixel clock rate from frame rate. |
paul@0 | 407 | // This multiplies the number of pixel periods in a line by the number of |
paul@0 | 408 | // lines in a frame, thus obtaining the number of such periods in a frame. |
paul@0 | 409 | // Multiplying this result with the frame rate yields the pixel frequency. |
paul@0 | 410 | |
paul@0 | 411 | pclk = _panel->frame_rate * |
paul@0 | 412 | (_panel->width * multiplier + |
paul@0 | 413 | _panel->hsync + _panel->line_start + _panel->line_end) * |
paul@0 | 414 | (_panel->height + |
paul@0 | 415 | _panel->vsync + _panel->frame_start + _panel->frame_end); |
paul@0 | 416 | |
paul@0 | 417 | // STN panel adjustments. |
paul@0 | 418 | |
paul@0 | 419 | if (have_stn_panel()) |
paul@0 | 420 | { |
paul@0 | 421 | // Colour STN panels apparently need to be driven at three times the rate. |
paul@0 | 422 | |
paul@0 | 423 | if (have_colour_stn()) pclk = (pclk * 3); |
paul@0 | 424 | |
paul@0 | 425 | // Reduce the rate according to the width of the STN connection. |
paul@0 | 426 | // Since the pins setting employs log2(pins), a shift by this value is |
paul@0 | 427 | // equivalent to a division by the number of pins. |
paul@0 | 428 | |
paul@0 | 429 | pclk = pclk >> ((_panel->config & Config_stn_pins_mask) >> Jz4740_lcd_config_stn_pins); |
paul@0 | 430 | |
paul@0 | 431 | // Divide the rate by the number of panels. |
paul@0 | 432 | |
paul@0 | 433 | pclk /= get_panels(); |
paul@0 | 434 | } |
paul@0 | 435 | |
paul@0 | 436 | return pclk; |
paul@0 | 437 | } |
paul@0 | 438 | |
paul@0 | 439 | |
paul@0 | 440 | |
paul@0 | 441 | // Return the panel mode. |
paul@0 | 442 | |
paul@0 | 443 | uint32_t |
paul@0 | 444 | Lcd_jz4740_chip::_mode() |
paul@0 | 445 | { |
paul@0 | 446 | return _panel->config & Config_mode_mask; |
paul@0 | 447 | } |
paul@0 | 448 | |
paul@0 | 449 | // Return the number of panels available. |
paul@0 | 450 | |
paul@0 | 451 | int |
paul@0 | 452 | Lcd_jz4740_chip::get_panels() |
paul@0 | 453 | { |
paul@0 | 454 | uint32_t mode = _mode(); |
paul@0 | 455 | |
paul@0 | 456 | return (mode == Jz4740_lcd_mode_stn_dual_colour) || |
paul@0 | 457 | (mode == Jz4740_lcd_mode_stn_dual_mono) ? 2 : 1; |
paul@0 | 458 | } |
paul@0 | 459 | |
paul@0 | 460 | // Return whether the panel is STN. |
paul@0 | 461 | |
paul@0 | 462 | int |
paul@0 | 463 | Lcd_jz4740_chip::have_stn_panel() |
paul@0 | 464 | { |
paul@0 | 465 | uint32_t mode = _mode(); |
paul@0 | 466 | |
paul@0 | 467 | return ((mode == Jz4740_lcd_mode_stn_single_colour) || |
paul@0 | 468 | (mode == Jz4740_lcd_mode_stn_dual_colour) || |
paul@0 | 469 | (mode == Jz4740_lcd_mode_stn_single_mono) || |
paul@0 | 470 | (mode == Jz4740_lcd_mode_stn_dual_mono)); |
paul@0 | 471 | } |
paul@0 | 472 | |
paul@0 | 473 | // Return whether the panel is colour STN. |
paul@0 | 474 | |
paul@0 | 475 | int |
paul@0 | 476 | Lcd_jz4740_chip::have_colour_stn() |
paul@0 | 477 | { |
paul@0 | 478 | uint32_t mode = _mode(); |
paul@0 | 479 | |
paul@0 | 480 | return ((mode == Jz4740_lcd_mode_stn_single_colour) || |
paul@0 | 481 | (mode == Jz4740_lcd_mode_stn_dual_colour)); |
paul@0 | 482 | } |
paul@0 | 483 | |
paul@0 | 484 | // Return whether the panel is colour STN. |
paul@0 | 485 | |
paul@0 | 486 | int |
paul@0 | 487 | Lcd_jz4740_chip::have_serial_tft() |
paul@0 | 488 | { |
paul@0 | 489 | return _mode() == Jz4740_lcd_mode_tft_serial; |
paul@0 | 490 | } |
paul@0 | 491 | |
paul@0 | 492 | |
paul@0 | 493 | |
paul@69 | 494 | // Return the pixel memory size in bits. |
paul@69 | 495 | |
paul@69 | 496 | l4_size_t |
paul@69 | 497 | Lcd_jz4740_chip::get_pixel_size() |
paul@69 | 498 | { |
paul@69 | 499 | if (_panel->bpp > 16) |
paul@69 | 500 | return 32; |
paul@69 | 501 | else if (_panel->bpp > 8) |
paul@69 | 502 | return 16; |
paul@69 | 503 | else |
paul@69 | 504 | return _panel->bpp; |
paul@69 | 505 | } |
paul@69 | 506 | |
paul@0 | 507 | // Return the line memory size. |
paul@0 | 508 | |
paul@0 | 509 | l4_size_t |
paul@0 | 510 | Lcd_jz4740_chip::get_line_size() |
paul@0 | 511 | { |
paul@0 | 512 | // Lines must be aligned to a word boundary. |
paul@0 | 513 | |
paul@69 | 514 | return align((_panel->width * get_pixel_size()) / 8, sizeof(uint32_t)); |
paul@0 | 515 | } |
paul@0 | 516 | |
paul@0 | 517 | // Return the screen memory size. |
paul@0 | 518 | |
paul@0 | 519 | l4_size_t |
paul@0 | 520 | Lcd_jz4740_chip::get_screen_size() |
paul@0 | 521 | { |
paul@0 | 522 | return get_line_size() * _panel->height; |
paul@0 | 523 | } |
paul@0 | 524 | |
paul@0 | 525 | // Return the aligned size for the DMA transfer. |
paul@0 | 526 | |
paul@0 | 527 | l4_size_t |
paul@0 | 528 | Lcd_jz4740_chip::get_aligned_size() |
paul@0 | 529 | { |
paul@0 | 530 | return align(get_screen_size(), _burst_size * sizeof(uint32_t)); |
paul@0 | 531 | } |
paul@0 | 532 | |
paul@0 | 533 | // Return the size of the palette. |
paul@0 | 534 | |
paul@0 | 535 | l4_size_t |
paul@0 | 536 | Lcd_jz4740_chip::get_palette_size() |
paul@0 | 537 | { |
paul@0 | 538 | // No palette for modes with more than eight bits per pixel. |
paul@0 | 539 | |
paul@0 | 540 | if (_panel->bpp > 8) return 0; |
paul@0 | 541 | |
paul@0 | 542 | // Get the size of a collection of two-byte entries, one per colour. |
paul@0 | 543 | |
paul@69 | 544 | return (1U << (_panel->bpp)) * sizeof(uint16_t); |
paul@0 | 545 | } |
paul@0 | 546 | |
paul@0 | 547 | // Return the aligned size of the palette for the DMA transfer. |
paul@0 | 548 | |
paul@0 | 549 | l4_size_t |
paul@0 | 550 | Lcd_jz4740_chip::get_aligned_palette_size() |
paul@0 | 551 | { |
paul@0 | 552 | return align(get_palette_size(), _burst_size * sizeof(uint32_t)); |
paul@0 | 553 | } |
paul@0 | 554 | |
paul@0 | 555 | // Return the total memory requirements of the framebuffers and palette. |
paul@0 | 556 | |
paul@0 | 557 | l4_size_t |
paul@0 | 558 | Lcd_jz4740_chip::get_total_size() |
paul@0 | 559 | { |
paul@0 | 560 | return get_aligned_size() * get_panels() + get_aligned_palette_size(); |
paul@0 | 561 | } |
paul@0 | 562 | |
paul@0 | 563 | // Return the total memory requirements of any DMA descriptors. |
paul@0 | 564 | |
paul@0 | 565 | l4_size_t |
paul@0 | 566 | Lcd_jz4740_chip::get_descriptors_size() |
paul@0 | 567 | { |
paul@0 | 568 | return 3 * sizeof(struct Jz4740_lcd_descriptor); |
paul@0 | 569 | } |
paul@0 | 570 | |
paul@0 | 571 | |
paul@0 | 572 | |
paul@0 | 573 | // Functions returning addresses of each data region. |
paul@0 | 574 | // The base parameter permits the retrieval of virtual or physical addresses. |
paul@0 | 575 | |
paul@0 | 576 | l4_addr_t |
paul@0 | 577 | Lcd_jz4740_chip::get_palette(l4_addr_t base) |
paul@0 | 578 | { |
paul@0 | 579 | // Use memory at the end of the allocated region for the palette. |
paul@0 | 580 | |
paul@0 | 581 | return base + (get_panels() * get_aligned_size()) - get_aligned_palette_size(); |
paul@0 | 582 | } |
paul@0 | 583 | |
paul@0 | 584 | l4_addr_t |
paul@0 | 585 | Lcd_jz4740_chip::get_framebuffer(int panel, l4_addr_t base) |
paul@0 | 586 | { |
paul@0 | 587 | // Framebuffers for panels are allocated at the start of the region. |
paul@0 | 588 | |
paul@0 | 589 | return base + (panel * get_aligned_size()); |
paul@0 | 590 | } |
paul@0 | 591 | |
paul@0 | 592 | |
paul@0 | 593 | |
paul@0 | 594 | // Palette initialisation. |
paul@0 | 595 | |
paul@0 | 596 | void |
paul@0 | 597 | Lcd_jz4740_chip::init_palette(l4_addr_t palette) |
paul@0 | 598 | { |
paul@69 | 599 | uint8_t colours = 1U << (_panel->bpp); |
paul@0 | 600 | uint16_t *entry = (uint16_t *) palette; |
paul@0 | 601 | uint16_t *end = entry + colours; |
paul@0 | 602 | uint8_t value = 0; |
paul@0 | 603 | |
paul@0 | 604 | while (entry < end) |
paul@0 | 605 | { |
paul@0 | 606 | switch (_panel->bpp) |
paul@0 | 607 | { |
paul@0 | 608 | case 4: |
paul@0 | 609 | *entry = rgb4_to_rgb16(value); |
paul@0 | 610 | break; |
paul@0 | 611 | |
paul@0 | 612 | case 8: |
paul@0 | 613 | *entry = rgb8_to_rgb16(value); |
paul@0 | 614 | break; |
paul@0 | 615 | |
paul@0 | 616 | default: |
paul@0 | 617 | break; |
paul@0 | 618 | } |
paul@0 | 619 | |
paul@0 | 620 | value++; |
paul@0 | 621 | entry++; |
paul@0 | 622 | } |
paul@0 | 623 | } |
paul@0 | 624 | |
paul@0 | 625 | |
paul@0 | 626 | |
paul@0 | 627 | // Return colour depth control value. |
paul@0 | 628 | // NOTE: Not supporting JZ4780 options. |
paul@0 | 629 | |
paul@0 | 630 | uint32_t |
paul@0 | 631 | Lcd_jz4740_chip::_control_bpp() |
paul@0 | 632 | { |
paul@0 | 633 | switch (_panel->bpp) |
paul@0 | 634 | { |
paul@0 | 635 | case 1: return Control_bpp_1bpp; |
paul@0 | 636 | case 2: return Control_bpp_2bpp; |
paul@0 | 637 | case 3 ... 4: return Control_bpp_4bpp; |
paul@0 | 638 | case 5 ... 8: return Control_bpp_8bpp; |
paul@0 | 639 | case 9 ... 15: return Control_bpp_15bpp | (Rgb_mode_555 << Control_rgb_mode); |
paul@0 | 640 | case 17 ... 18: return Control_bpp_18bpp; |
paul@0 | 641 | case 19 ... 32: return Control_bpp_24bpp; |
paul@0 | 642 | case 16: |
paul@0 | 643 | default: return Control_bpp_16bpp; |
paul@0 | 644 | } |
paul@0 | 645 | } |
paul@0 | 646 | |
paul@69 | 647 | // Return colour depth control value. |
paul@69 | 648 | // JZ4780 position details only. |
paul@69 | 649 | |
paul@69 | 650 | uint32_t |
paul@69 | 651 | Lcd_jz4740_chip::_position_bpp() |
paul@69 | 652 | { |
paul@69 | 653 | uint32_t value; |
paul@69 | 654 | |
paul@69 | 655 | switch (_panel->bpp) |
paul@69 | 656 | { |
paul@69 | 657 | case 15: case 16: value = Position_bpp_15_16bpp; break; |
paul@69 | 658 | case 18: case 24: value = Position_bpp_18_24bpp; break; |
paul@69 | 659 | case 30: value = Position_bpp_30bpp; break; |
paul@69 | 660 | default: value = 0; break; |
paul@69 | 661 | } |
paul@69 | 662 | |
paul@69 | 663 | return value << Position_bpp; |
paul@69 | 664 | } |
paul@69 | 665 | |
paul@0 | 666 | // Return a panel-related control value. |
paul@0 | 667 | |
paul@0 | 668 | uint32_t |
paul@0 | 669 | Lcd_jz4740_chip::_control_panel() |
paul@0 | 670 | { |
paul@0 | 671 | if (have_stn_panel()) |
paul@69 | 672 | return _control_stn_frc() << Control_frc_algorithm; |
paul@0 | 673 | else |
paul@0 | 674 | return 0; |
paul@0 | 675 | } |
paul@0 | 676 | |
paul@0 | 677 | // Return a STN-related control value. |
paul@0 | 678 | |
paul@0 | 679 | uint32_t |
paul@0 | 680 | Lcd_jz4740_chip::_control_stn_frc() |
paul@0 | 681 | { |
paul@0 | 682 | if (_panel->bpp <= 2) |
paul@0 | 683 | return Frc_greyscales_2; |
paul@0 | 684 | if (_panel->bpp <= 4) |
paul@0 | 685 | return Frc_greyscales_4; |
paul@0 | 686 | return Frc_greyscales_16; |
paul@0 | 687 | } |
paul@0 | 688 | |
paul@0 | 689 | // Return a transfer-related control value. |
paul@0 | 690 | |
paul@0 | 691 | uint32_t |
paul@0 | 692 | Lcd_jz4740_chip::_control_transfer() |
paul@0 | 693 | { |
paul@0 | 694 | uint32_t length; |
paul@0 | 695 | |
paul@0 | 696 | switch (_burst_size) |
paul@0 | 697 | { |
paul@0 | 698 | case 4: length = Burst_length_4; break; |
paul@0 | 699 | case 8: length = Burst_length_8; break; |
paul@0 | 700 | case 32: length = Burst_length_32; break; |
paul@0 | 701 | case 64: length = Burst_length_64; break; |
paul@0 | 702 | case 16: |
paul@0 | 703 | default: length = Burst_length_16; break; |
paul@0 | 704 | } |
paul@0 | 705 | |
paul@69 | 706 | return (length << Control_burst_length) | (1U << Control_out_underrun); |
paul@69 | 707 | } |
paul@69 | 708 | |
paul@69 | 709 | // Return an interrupt-related control value. |
paul@69 | 710 | |
paul@69 | 711 | uint32_t |
paul@69 | 712 | Lcd_jz4740_chip::_control_irq() |
paul@69 | 713 | { |
paul@73 | 714 | return ((_irq_conditions & Lcd_irq_frame_start) ? (1U << Control_frame_start_irq_enable) : 0) | |
paul@69 | 715 | ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Control_frame_end_irq_enable) : 0); |
paul@69 | 716 | } |
paul@69 | 717 | |
paul@69 | 718 | // Return an interrupt-related OSD configuration value. |
paul@69 | 719 | |
paul@69 | 720 | uint32_t |
paul@69 | 721 | Lcd_jz4740_chip::_osd_config_irq() |
paul@69 | 722 | { |
paul@69 | 723 | return ((_irq_conditions & Lcd_irq_frame_start) ? (1U << Osd_config_fg0_frame_start_irq_enable) : 0) | |
paul@69 | 724 | ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Osd_config_fg0_frame_end_irq_enable) : 0); |
paul@69 | 725 | } |
paul@69 | 726 | |
paul@69 | 727 | // Return an interrupt-related command value. |
paul@69 | 728 | |
paul@69 | 729 | uint32_t |
paul@69 | 730 | Lcd_jz4740_chip::_command_irq() |
paul@69 | 731 | { |
paul@69 | 732 | return ((_irq_conditions & Lcd_irq_frame_start) ? (1U << Command_frame_start_irq) : 0) | |
paul@69 | 733 | ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Command_frame_end_irq) : 0); |
paul@69 | 734 | } |
paul@69 | 735 | |
paul@69 | 736 | // Return an interrupt-related status value. |
paul@69 | 737 | |
paul@69 | 738 | uint32_t |
paul@69 | 739 | Lcd_jz4740_chip::_status_irq() |
paul@69 | 740 | { |
paul@73 | 741 | return ((_irq_conditions & Lcd_irq_frame_start) ? (1U << Status_frame_start_irq) : 0) | |
paul@69 | 742 | ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Status_frame_end_irq) : 0); |
paul@69 | 743 | } |
paul@69 | 744 | |
paul@69 | 745 | uint32_t |
paul@69 | 746 | Lcd_jz4740_chip::_priority_transfer() |
paul@69 | 747 | { |
paul@69 | 748 | uint32_t length; |
paul@69 | 749 | |
paul@69 | 750 | switch (_burst_size) |
paul@69 | 751 | { |
paul@69 | 752 | case 4: length = Priority_burst_4; break; |
paul@69 | 753 | case 8: length = Priority_burst_8; break; |
paul@69 | 754 | case 32: length = Priority_burst_32; break; |
paul@69 | 755 | case 64: length = Priority_burst_64; break; |
paul@69 | 756 | case 16: |
paul@69 | 757 | default: length = Priority_burst_16; break; |
paul@69 | 758 | } |
paul@69 | 759 | |
paul@69 | 760 | return Priority_mode_arbiter | |
paul@69 | 761 | (length << Priority_highest_burst) | |
paul@69 | 762 | (511U << Priority_threshold2) | |
paul@69 | 763 | (400U << Priority_threshold1) | |
paul@69 | 764 | (256U << Priority_threshold0); |
paul@0 | 765 | } |
paul@0 | 766 | |
paul@0 | 767 | // STN panel-specific initialisation. |
paul@0 | 768 | |
paul@0 | 769 | void |
paul@0 | 770 | Lcd_jz4740_chip::_init_stn() |
paul@0 | 771 | { |
paul@0 | 772 | // Divide the height by the number of panels. |
paul@0 | 773 | |
paul@0 | 774 | uint32_t height = _panel->height / get_panels(); |
paul@0 | 775 | |
paul@0 | 776 | // Since the value is log2(pins), 1 << value yields the number of pins. |
paul@0 | 777 | |
paul@0 | 778 | int pins = 1 << ((_panel->config & Config_stn_pins_mask) >> Jz4740_lcd_config_stn_pins); |
paul@0 | 779 | |
paul@0 | 780 | // Round parameters up to a multiple of the number of pins. |
paul@0 | 781 | |
paul@0 | 782 | uint32_t hsync = align(_panel->hsync, pins); |
paul@0 | 783 | uint32_t line_start = align(_panel->line_start, pins); |
paul@0 | 784 | uint32_t line_end = align(_panel->line_end, pins); |
paul@0 | 785 | |
paul@0 | 786 | // Define the start and end positions of visible data on a line and in a frame. |
paul@0 | 787 | // Visible frame data is anchored at line zero, with the start region |
paul@0 | 788 | // preceding this line (and thus appearing at the end of the preceding frame). |
paul@0 | 789 | |
paul@0 | 790 | uint32_t line_start_pos = line_start; |
paul@0 | 791 | uint32_t line_end_pos = line_start_pos + _panel->width; |
paul@0 | 792 | uint32_t frame_start_pos = 0; |
paul@0 | 793 | uint32_t frame_end_pos = frame_start_pos + height; |
paul@0 | 794 | |
paul@0 | 795 | // Define sync pulse locations, with hsync occurring after the visible data. |
paul@0 | 796 | |
paul@0 | 797 | _regs[Lcd_hsync] = encode_pair(line_end_pos, line_end_pos + hsync); |
paul@0 | 798 | _regs[Lcd_vsync] = encode_pair(0, _panel->vsync); |
paul@0 | 799 | |
paul@0 | 800 | // Set the display area and limits. |
paul@0 | 801 | |
paul@69 | 802 | _regs[Virtual_area] = encode_pair(line_end_pos + hsync + line_end, |
paul@69 | 803 | frame_end_pos + _panel->vsync + _panel->frame_end + _panel->frame_start); |
paul@0 | 804 | |
paul@0 | 805 | _regs[Display_hlimits] = encode_pair(line_start_pos, line_end_pos); |
paul@0 | 806 | _regs[Display_vlimits] = encode_pair(frame_start_pos, frame_end_pos); |
paul@0 | 807 | |
paul@0 | 808 | // Set the AC bias signal. |
paul@0 | 809 | |
paul@0 | 810 | _regs[Lcd_ps] = encode_pair(0, _panel->frame_start + height + _panel->vsync + _panel->frame_end); |
paul@0 | 811 | } |
paul@0 | 812 | |
paul@0 | 813 | // TFT panel-specific initialisation. |
paul@0 | 814 | |
paul@0 | 815 | void |
paul@0 | 816 | Lcd_jz4740_chip::_init_tft() |
paul@0 | 817 | { |
paul@0 | 818 | // Define the start and end positions of visible data on a line and in a frame. |
paul@0 | 819 | |
paul@0 | 820 | uint32_t line_start_pos = _panel->line_start + _panel->hsync; |
paul@0 | 821 | uint32_t line_end_pos = line_start_pos + _panel->width; |
paul@0 | 822 | uint32_t frame_start_pos = _panel->frame_start + _panel->vsync; |
paul@0 | 823 | uint32_t frame_end_pos = frame_start_pos + _panel->height; |
paul@0 | 824 | |
paul@0 | 825 | // Define sync pulse locations, with pulses appearing before visible data. |
paul@0 | 826 | |
paul@0 | 827 | _regs[Lcd_hsync] = encode_pair(0, _panel->hsync); |
paul@0 | 828 | _regs[Lcd_vsync] = encode_pair(0, _panel->vsync); |
paul@0 | 829 | |
paul@0 | 830 | // Set the display area and limits. |
paul@0 | 831 | |
paul@69 | 832 | _regs[Virtual_area] = encode_pair(line_end_pos + _panel->line_end, |
paul@69 | 833 | frame_end_pos + _panel->frame_end); |
paul@0 | 834 | |
paul@0 | 835 | _regs[Display_hlimits] = encode_pair(line_start_pos, line_end_pos); |
paul@0 | 836 | _regs[Display_vlimits] = encode_pair(frame_start_pos, frame_end_pos); |
paul@0 | 837 | } |
paul@0 | 838 | |
paul@0 | 839 | // Initialise the panel. |
paul@0 | 840 | // NOTE: Only generic STN and TFT panels are supported. |
paul@0 | 841 | |
paul@0 | 842 | void |
paul@0 | 843 | Lcd_jz4740_chip::_init_panel() |
paul@0 | 844 | { |
paul@0 | 845 | if (have_stn_panel()) |
paul@0 | 846 | _init_stn(); |
paul@0 | 847 | else |
paul@0 | 848 | switch (_mode()) |
paul@0 | 849 | { |
paul@0 | 850 | case Jz4740_lcd_mode_tft_generic: |
paul@0 | 851 | case Jz4740_lcd_mode_tft_casio: |
paul@0 | 852 | case Jz4740_lcd_mode_tft_serial: _init_tft(); |
paul@0 | 853 | |
paul@0 | 854 | default: break; |
paul@0 | 855 | } |
paul@0 | 856 | } |
paul@0 | 857 | |
paul@0 | 858 | // Initialise a DMA descriptor. |
paul@0 | 859 | |
paul@0 | 860 | void |
paul@0 | 861 | Lcd_jz4740_chip::_set_descriptor(struct Jz4740_lcd_descriptor &desc, |
paul@0 | 862 | l4_addr_t source, l4_size_t size, |
paul@0 | 863 | struct Jz4740_lcd_descriptor *next, |
paul@72 | 864 | uint32_t flags, |
paul@72 | 865 | bool frame_enable) |
paul@0 | 866 | { |
paul@0 | 867 | // In the command, indicate the number of words from the source for transfer. |
paul@0 | 868 | |
paul@0 | 869 | desc.next = next; |
paul@72 | 870 | desc.source = frame_enable ? source : 0; |
paul@69 | 871 | desc.identifier = source; |
paul@69 | 872 | desc.command = ((size / sizeof(uint32_t)) & Command_buffer_length_mask) | |
paul@72 | 873 | (frame_enable ? (1U << Command_frame_enable) : 0) | |
paul@69 | 874 | flags; |
paul@69 | 875 | |
paul@69 | 876 | // Initialise "new" descriptor fields. |
paul@69 | 877 | |
paul@69 | 878 | desc.offset = 0; |
paul@69 | 879 | desc.page_width = 0; |
paul@72 | 880 | desc.command_position = (1U << Position_premultiply_lcd) | |
paul@72 | 881 | ((frame_enable ? 1U : 3U) << Position_coefficient) | |
paul@69 | 882 | _position_bpp(); |
paul@72 | 883 | desc.fg_size = 0xff000000 | |
paul@72 | 884 | ((_panel->height - 1) << 12) | |
paul@72 | 885 | ((_panel->width - 1) << 0); |
paul@0 | 886 | } |
paul@0 | 887 | |
paul@0 | 888 | |
paul@0 | 889 | |
paul@0 | 890 | // Initialise the LCD controller with the memory, panel and framebuffer details. |
paul@0 | 891 | // Any palette must be initialised separately using get_palette and init_palette. |
paul@0 | 892 | |
paul@0 | 893 | void |
paul@0 | 894 | Lcd_jz4740_chip::config(struct Jz4740_lcd_descriptor *desc_vaddr, |
paul@0 | 895 | struct Jz4740_lcd_descriptor *desc_paddr, |
paul@0 | 896 | l4_addr_t fb_paddr) |
paul@0 | 897 | { |
paul@69 | 898 | // NOTE: Remarks in the Ingenic Linux 3.0.8 driver suggest that the JZ4775 and |
paul@69 | 899 | // NOTE: JZ4780 do not support palettes. |
paul@69 | 900 | |
paul@0 | 901 | int have_palette = (_panel->bpp <= 8); |
paul@0 | 902 | |
paul@72 | 903 | bool _have_fg1 = true; // NOTE: To be formalised! |
paul@72 | 904 | |
paul@0 | 905 | // Provide the first framebuffer descriptor in single and dual modes. |
paul@0 | 906 | // Flip back and forth between any palette and the framebuffer. |
paul@0 | 907 | |
paul@0 | 908 | _set_descriptor(desc_vaddr[0], get_framebuffer(0, fb_paddr), |
paul@69 | 909 | get_aligned_size(), |
paul@69 | 910 | have_palette ? desc_paddr + 2 : desc_paddr, |
paul@69 | 911 | _command_irq()); |
paul@0 | 912 | |
paul@0 | 913 | // Provide the second framebuffer descriptor only in dual-panel mode. |
paul@0 | 914 | // Only employ this descriptor in the second DMA channel. |
paul@0 | 915 | |
paul@72 | 916 | if ((get_panels() == 2) || _have_fg1) |
paul@0 | 917 | _set_descriptor(desc_vaddr[1], get_framebuffer(1, fb_paddr), |
paul@69 | 918 | get_aligned_size(), |
paul@69 | 919 | desc_paddr + 1, |
paul@72 | 920 | _command_irq(), |
paul@72 | 921 | false); |
paul@0 | 922 | |
paul@0 | 923 | // Initialise palette descriptor details for lower colour depths. |
paul@0 | 924 | |
paul@0 | 925 | if (have_palette) |
paul@0 | 926 | _set_descriptor(desc_vaddr[2], get_palette(fb_paddr), |
paul@69 | 927 | get_aligned_palette_size(), |
paul@0 | 928 | desc_paddr, |
paul@0 | 929 | Command_palette_buffer); |
paul@0 | 930 | |
paul@0 | 931 | // Flush cached structure data. |
paul@0 | 932 | |
paul@0 | 933 | l4_cache_clean_data((unsigned long) desc_vaddr, |
paul@0 | 934 | (unsigned long) desc_vaddr + get_descriptors_size()); |
paul@0 | 935 | |
paul@0 | 936 | // Configure DMA by setting frame descriptor addresses. |
paul@0 | 937 | |
paul@0 | 938 | // Provide the palette descriptor address first, if employed. |
paul@0 | 939 | |
paul@0 | 940 | _regs[Desc_address_0] = (uint32_t) (have_palette ? desc_paddr + 2 : desc_paddr); |
paul@0 | 941 | |
paul@0 | 942 | // Provide a descriptor for the second DMA channel in dual-panel mode. |
paul@0 | 943 | |
paul@72 | 944 | if ((get_panels() == 2) || _have_fg1) |
paul@0 | 945 | _regs[Desc_address_1] = (uint32_t) (desc_paddr + 1); |
paul@0 | 946 | |
paul@0 | 947 | // Initialise panel-related registers. |
paul@0 | 948 | |
paul@0 | 949 | _init_panel(); |
paul@0 | 950 | |
paul@0 | 951 | // Initialise the control and configuration registers. |
paul@69 | 952 | // NOTE: JZ4780 does not support bpp setting here. |
paul@0 | 953 | |
paul@69 | 954 | _regs[Lcd_control] = _control_panel() | _control_bpp() | _control_transfer() | _control_irq(); |
paul@0 | 955 | _regs[Lcd_config] = _panel->config; |
paul@69 | 956 | |
paul@69 | 957 | // NOTE: JZ4780 only. |
paul@69 | 958 | |
paul@69 | 959 | _regs[Rgb_control] = (1U << Rgb_format_enable) | Rgb_odd_line_rgb | Rgb_even_line_rgb; |
paul@69 | 960 | _regs[Priority_level] = _priority_transfer(); |
paul@73 | 961 | _regs[Osd_config] = (1U << Osd_config_enable) | |
paul@72 | 962 | (1U << Osd_config_alpha_enable); |
paul@72 | 963 | _regs[Alpha_levels] = ((255U << Alpha_level_fg1) & Alpha_level_fg1_mask) | |
paul@72 | 964 | ((255U << Alpha_level_fg0) & Alpha_level_fg0_mask); |
paul@69 | 965 | } |
paul@69 | 966 | |
paul@69 | 967 | // Set the interrupt for controller-related events. |
paul@69 | 968 | |
paul@69 | 969 | void |
paul@69 | 970 | Lcd_jz4740_chip::set_irq(l4_cap_idx_t irq, enum Jz4740_lcd_irq_condition conditions) |
paul@69 | 971 | { |
paul@69 | 972 | _irq = irq; |
paul@69 | 973 | _irq_conditions = conditions; |
paul@69 | 974 | } |
paul@69 | 975 | |
paul@69 | 976 | // Wait for an interrupt condition. |
paul@69 | 977 | |
paul@69 | 978 | long |
paul@69 | 979 | Lcd_jz4740_chip::wait_for_irq() |
paul@69 | 980 | { |
paul@69 | 981 | l4_msgtag_t tag; |
paul@69 | 982 | |
paul@69 | 983 | _regs[Lcd_status] = _regs[Lcd_status] & ~(_status_irq()); |
paul@69 | 984 | |
paul@69 | 985 | // Wait for a condition. |
paul@69 | 986 | |
paul@72 | 987 | tag = l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(2000000))); |
paul@72 | 988 | |
paul@69 | 989 | // Acknowledge interrupts. |
paul@69 | 990 | |
paul@72 | 991 | _regs[Lcd_status] = 0; |
paul@69 | 992 | |
paul@72 | 993 | // Return errors. |
paul@72 | 994 | |
paul@72 | 995 | return l4_error(tag); |
paul@0 | 996 | } |
paul@0 | 997 | |
paul@0 | 998 | |
paul@0 | 999 | |
paul@0 | 1000 | // C language interface functions. |
paul@0 | 1001 | |
paul@0 | 1002 | void * |
paul@0 | 1003 | jz4740_lcd_init(l4_addr_t lcd_base, struct Jz4740_lcd_panel *panel) |
paul@0 | 1004 | { |
paul@0 | 1005 | return (void *) new Lcd_jz4740_chip(lcd_base, panel); |
paul@0 | 1006 | } |
paul@0 | 1007 | |
paul@0 | 1008 | void |
paul@0 | 1009 | jz4740_lcd_config(void *lcd, struct Jz4740_lcd_descriptor *desc_vaddr, |
paul@0 | 1010 | struct Jz4740_lcd_descriptor *desc_paddr, |
paul@0 | 1011 | l4_addr_t fb_paddr) |
paul@0 | 1012 | { |
paul@0 | 1013 | static_cast<Lcd_jz4740_chip *>(lcd)->config(desc_vaddr, desc_paddr, fb_paddr); |
paul@0 | 1014 | } |
paul@0 | 1015 | |
paul@0 | 1016 | void |
paul@69 | 1017 | jz4740_lcd_set_irq(void *lcd, l4_cap_idx_t irq, enum Jz4740_lcd_irq_condition conditions) |
paul@69 | 1018 | { |
paul@69 | 1019 | static_cast<Lcd_jz4740_chip *>(lcd)->set_irq(irq, conditions); |
paul@69 | 1020 | } |
paul@69 | 1021 | |
paul@69 | 1022 | long |
paul@69 | 1023 | jz4740_lcd_wait_for_irq(void *lcd) |
paul@69 | 1024 | { |
paul@69 | 1025 | return static_cast<Lcd_jz4740_chip *>(lcd)->wait_for_irq(); |
paul@69 | 1026 | } |
paul@69 | 1027 | |
paul@69 | 1028 | void |
paul@0 | 1029 | jz4740_lcd_disable(void *lcd) |
paul@0 | 1030 | { |
paul@0 | 1031 | static_cast<Lcd_jz4740_chip *>(lcd)->disable(); |
paul@0 | 1032 | } |
paul@0 | 1033 | |
paul@0 | 1034 | void |
paul@0 | 1035 | jz4740_lcd_disable_quick(void *lcd) |
paul@0 | 1036 | { |
paul@0 | 1037 | static_cast<Lcd_jz4740_chip *>(lcd)->disable_quick(); |
paul@0 | 1038 | } |
paul@0 | 1039 | |
paul@0 | 1040 | void |
paul@0 | 1041 | jz4740_lcd_enable(void *lcd) |
paul@0 | 1042 | { |
paul@0 | 1043 | static_cast<Lcd_jz4740_chip *>(lcd)->enable(); |
paul@0 | 1044 | } |
paul@0 | 1045 | |
paul@0 | 1046 | int |
paul@69 | 1047 | jz4740_lcd_enabled(void *lcd) |
paul@69 | 1048 | { |
paul@69 | 1049 | return (int) static_cast<Lcd_jz4740_chip *>(lcd)->enabled(); |
paul@69 | 1050 | } |
paul@69 | 1051 | |
paul@69 | 1052 | int |
paul@0 | 1053 | jz4740_lcd_get_pixel_clock(void *lcd) |
paul@0 | 1054 | { |
paul@0 | 1055 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_pixel_clock(); |
paul@0 | 1056 | } |
paul@0 | 1057 | |
paul@69 | 1058 | l4_size_t |
paul@69 | 1059 | jz4740_lcd_get_descriptors_size(void *lcd) |
paul@69 | 1060 | { |
paul@69 | 1061 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_descriptors_size(); |
paul@69 | 1062 | } |
paul@69 | 1063 | |
paul@69 | 1064 | l4_size_t |
paul@72 | 1065 | jz4740_lcd_get_line_size(void *lcd) |
paul@72 | 1066 | { |
paul@72 | 1067 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_line_size(); |
paul@72 | 1068 | } |
paul@72 | 1069 | |
paul@72 | 1070 | l4_size_t |
paul@69 | 1071 | jz4740_lcd_get_screen_size(void *lcd) |
paul@69 | 1072 | { |
paul@69 | 1073 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_screen_size(); |
paul@69 | 1074 | } |
paul@69 | 1075 | |
paul@0 | 1076 | l4_addr_t |
paul@0 | 1077 | jz4740_lcd_get_palette(void *lcd, l4_addr_t base) |
paul@0 | 1078 | { |
paul@0 | 1079 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_palette(base); |
paul@0 | 1080 | } |
paul@0 | 1081 | |
paul@0 | 1082 | void |
paul@0 | 1083 | jz4740_lcd_init_palette(void *lcd, l4_addr_t palette) |
paul@0 | 1084 | { |
paul@0 | 1085 | static_cast<Lcd_jz4740_chip *>(lcd)->init_palette(palette); |
paul@0 | 1086 | } |