paul@123 | 1 | /* |
paul@123 | 2 | * DMA support for the JZ4730. |
paul@123 | 3 | * |
paul@123 | 4 | * Copyright (C) 2021 Paul Boddie <paul@boddie.org.uk> |
paul@123 | 5 | * |
paul@123 | 6 | * This program is free software; you can redistribute it and/or |
paul@123 | 7 | * modify it under the terms of the GNU General Public License as |
paul@123 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@123 | 9 | * the License, or (at your option) any later version. |
paul@123 | 10 | * |
paul@123 | 11 | * This program is distributed in the hope that it will be useful, |
paul@123 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@123 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@123 | 14 | * GNU General Public License for more details. |
paul@123 | 15 | * |
paul@123 | 16 | * You should have received a copy of the GNU General Public License |
paul@123 | 17 | * along with this program; if not, write to the Free Software |
paul@123 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@123 | 19 | * Boston, MA 02110-1301, USA |
paul@123 | 20 | */ |
paul@123 | 21 | |
paul@123 | 22 | #include <l4/devices/dma-jz4730.h> |
paul@123 | 23 | #include <l4/devices/hw_mmio_register_block.h> |
paul@123 | 24 | |
paul@123 | 25 | #include <l4/sys/icu.h> |
paul@123 | 26 | #include <l4/sys/ipc.h> |
paul@123 | 27 | #include <l4/sys/irq.h> |
paul@123 | 28 | #include <l4/util/util.h> |
paul@123 | 29 | |
paul@123 | 30 | #include <cstdio> |
paul@123 | 31 | |
paul@123 | 32 | enum Global_regs |
paul@123 | 33 | { |
paul@123 | 34 | Dma_irq_pending = 0xf8, // IRQP |
paul@123 | 35 | Dma_control = 0xfc, // DMAC |
paul@123 | 36 | }; |
paul@123 | 37 | |
paul@123 | 38 | enum Channel_regs |
paul@123 | 39 | { |
paul@123 | 40 | Dma_source = 0x00, // DSA |
paul@123 | 41 | Dma_destination = 0x04, // DDA |
paul@123 | 42 | Dma_transfer_count = 0x08, // DTC |
paul@123 | 43 | Dma_request_source = 0x0c, // DRT |
paul@123 | 44 | Dma_control_status = 0x10, // DCS |
paul@123 | 45 | }; |
paul@123 | 46 | |
paul@123 | 47 | enum Dma_irq_pending_shifts : unsigned |
paul@123 | 48 | { |
paul@123 | 49 | Dma_irq_pending_ch0 = 15, |
paul@123 | 50 | Dma_irq_pending_ch1 = 14, |
paul@123 | 51 | Dma_irq_pending_ch2 = 13, |
paul@123 | 52 | Dma_irq_pending_ch3 = 12, |
paul@123 | 53 | Dma_irq_pending_ch4 = 11, |
paul@123 | 54 | Dma_irq_pending_ch5 = 10, |
paul@123 | 55 | }; |
paul@123 | 56 | |
paul@123 | 57 | enum Dma_control_bits : unsigned |
paul@123 | 58 | { |
paul@123 | 59 | Dma_control_priority_mode = 0x100, // PM |
paul@123 | 60 | Dma_control_halt_occurred = 0x008, // HLT |
paul@123 | 61 | Dma_control_address_error = 0x004, // AR |
paul@123 | 62 | Dma_control_enable = 0x001, // DMAE |
paul@123 | 63 | }; |
paul@123 | 64 | |
paul@123 | 65 | enum Dma_control_priority_modes : unsigned |
paul@123 | 66 | { |
paul@123 | 67 | Dma_priority_mode_01234567 = 0, |
paul@123 | 68 | Dma_priority_mode_02314675 = 1, |
paul@123 | 69 | Dma_priority_mode_20136457 = 2, |
paul@123 | 70 | Dma_priority_mode_round_robin = 3, |
paul@123 | 71 | }; |
paul@123 | 72 | |
paul@123 | 73 | enum Dma_transfer_count_bits : unsigned |
paul@123 | 74 | { |
paul@123 | 75 | Dma_transfer_count_mask = 0x00ffffff, |
paul@123 | 76 | }; |
paul@123 | 77 | |
paul@123 | 78 | enum Dma_request_source_bits : unsigned |
paul@123 | 79 | { |
paul@123 | 80 | Dma_request_type_mask = 0x0000001f, |
paul@123 | 81 | }; |
paul@123 | 82 | |
paul@123 | 83 | enum Dma_control_status_shifts : unsigned |
paul@123 | 84 | { |
paul@123 | 85 | Dma_ext_output_polarity = 31, |
paul@123 | 86 | Dma_ext_output_mode_cycle = 30, |
paul@123 | 87 | Dma_ext_req_detect_mode = 28, |
paul@123 | 88 | Dma_ext_end_of_process_mode = 27, |
paul@123 | 89 | Dma_req_detect_int_length = 16, |
paul@123 | 90 | Dma_source_port_width = 14, |
paul@123 | 91 | Dma_dest_port_width = 12, |
paul@123 | 92 | Dma_trans_unit_size = 8, |
paul@123 | 93 | Dma_trans_mode = 7, |
paul@123 | 94 | }; |
paul@123 | 95 | |
paul@123 | 96 | enum Dma_control_status_bits : unsigned |
paul@123 | 97 | { |
paul@123 | 98 | Dma_source_address_incr = 0x00800000, |
paul@123 | 99 | Dma_dest_address_incr = 0x00400000, |
paul@123 | 100 | Dma_address_error = 0x00000010, |
paul@123 | 101 | Dma_trans_completed = 0x00000008, |
paul@123 | 102 | Dma_trans_halted = 0x00000004, |
paul@123 | 103 | Dma_channel_irq_enable = 0x00000002, |
paul@123 | 104 | Dma_channel_enable = 0x00000001, |
paul@123 | 105 | }; |
paul@123 | 106 | |
paul@123 | 107 | enum Dma_port_width_values : unsigned |
paul@123 | 108 | { |
paul@123 | 109 | Dma_port_width_32_bit = 0, |
paul@123 | 110 | Dma_port_width_8_bit = 1, |
paul@123 | 111 | Dma_port_width_16_bit = 2, |
paul@123 | 112 | }; |
paul@123 | 113 | |
paul@123 | 114 | enum Dma_trans_mode_values : unsigned |
paul@123 | 115 | { |
paul@123 | 116 | Dma_trans_mode_single = 0, |
paul@123 | 117 | Dma_trans_mode_block = 1, |
paul@123 | 118 | }; |
paul@123 | 119 | |
paul@123 | 120 | |
paul@123 | 121 | |
paul@123 | 122 | // Initialise a channel. |
paul@123 | 123 | |
paul@123 | 124 | Dma_jz4730_channel::Dma_jz4730_channel(Dma_jz4730_chip *chip, uint8_t channel, |
paul@123 | 125 | l4_addr_t start, l4_cap_idx_t irq) |
paul@123 | 126 | : _chip(chip), _channel(channel), _irq(irq) |
paul@123 | 127 | { |
paul@123 | 128 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@123 | 129 | } |
paul@123 | 130 | |
paul@123 | 131 | // Encode flags for an external transfer. |
paul@123 | 132 | |
paul@123 | 133 | uint32_t |
paul@123 | 134 | Dma_jz4730_channel::encode_external_transfer(enum Dma_jz4730_request_type type) |
paul@123 | 135 | { |
paul@123 | 136 | int external = (type == Dma_request_external) ? 1 : 0; |
paul@123 | 137 | |
paul@123 | 138 | return |
paul@123 | 139 | ((external ? (int) _ext_output_polarity : 0) << Dma_ext_output_polarity) | |
paul@123 | 140 | ((external ? (int) _ext_output_mode_cycle : 0) << Dma_ext_output_mode_cycle) | |
paul@123 | 141 | ((external ? (int) _ext_req_detect_mode : 0) << Dma_ext_req_detect_mode) | |
paul@123 | 142 | ((external ? (int) _ext_end_of_process_mode : 0) << Dma_ext_end_of_process_mode); |
paul@123 | 143 | } |
paul@123 | 144 | |
paul@123 | 145 | // Encode the appropriate source address increment for the given request type. |
paul@123 | 146 | // Here, memory-to-memory transfers and transfers to peripherals involve an |
paul@123 | 147 | // incrementing source address. Transfers from peripherals involve a static |
paul@123 | 148 | // source address. |
paul@123 | 149 | |
paul@123 | 150 | uint32_t |
paul@123 | 151 | Dma_jz4730_channel::encode_source_address_increment(enum Dma_jz4730_request_type type) |
paul@123 | 152 | { |
paul@123 | 153 | switch (type) |
paul@123 | 154 | { |
paul@123 | 155 | case Dma_request_auto: |
paul@123 | 156 | case Dma_request_pcmcia_out: |
paul@123 | 157 | case Dma_request_des_out: |
paul@123 | 158 | case Dma_request_uart3_out: |
paul@123 | 159 | case Dma_request_uart2_out: |
paul@123 | 160 | case Dma_request_uart1_out: |
paul@123 | 161 | case Dma_request_uart0_out: |
paul@123 | 162 | case Dma_request_ssi_send_empty: |
paul@123 | 163 | case Dma_request_aic_send_empty: |
paul@123 | 164 | case Dma_request_msc_send_empty: |
paul@123 | 165 | case Dma_request_ost2_underflow: |
paul@123 | 166 | return Dma_source_address_incr; |
paul@123 | 167 | |
paul@123 | 168 | default: |
paul@123 | 169 | return 0; |
paul@123 | 170 | } |
paul@123 | 171 | } |
paul@123 | 172 | |
paul@123 | 173 | // Encode the appropriate destination address increment for the given request |
paul@123 | 174 | // type. Here, memory-to-memory transfers and transfers from peripherals involve |
paul@123 | 175 | // an incrementing destination address. Transfers to peripherals involve a static |
paul@123 | 176 | // destination address. |
paul@123 | 177 | |
paul@123 | 178 | uint32_t |
paul@123 | 179 | Dma_jz4730_channel::encode_destination_address_increment(enum Dma_jz4730_request_type type) |
paul@123 | 180 | { |
paul@123 | 181 | switch (type) |
paul@123 | 182 | { |
paul@123 | 183 | case Dma_request_auto: |
paul@123 | 184 | case Dma_request_pcmcia_in: |
paul@123 | 185 | case Dma_request_des_in: |
paul@123 | 186 | case Dma_request_uart3_in: |
paul@123 | 187 | case Dma_request_uart2_in: |
paul@123 | 188 | case Dma_request_uart1_in: |
paul@123 | 189 | case Dma_request_uart0_in: |
paul@123 | 190 | case Dma_request_ssi_recv_full: |
paul@123 | 191 | case Dma_request_aic_recv_full: |
paul@123 | 192 | case Dma_request_msc_recv_full: |
paul@123 | 193 | case Dma_request_ost2_underflow: |
paul@123 | 194 | return Dma_dest_address_incr; |
paul@123 | 195 | |
paul@123 | 196 | default: |
paul@123 | 197 | return 0; |
paul@123 | 198 | } |
paul@123 | 199 | } |
paul@123 | 200 | |
paul@123 | 201 | // Return the closest interval length greater than or equal to the number of |
paul@123 | 202 | // units given encoded in the request detection interval length field of the |
paul@123 | 203 | // control/status register. |
paul@123 | 204 | |
paul@123 | 205 | uint32_t |
paul@123 | 206 | Dma_jz4730_channel::encode_req_detect_int_length(uint8_t units) |
paul@123 | 207 | { |
paul@123 | 208 | static uint8_t lengths[] = {0, 2, 4, 8, 12, 16, 20, 24, 28, 32, 48, 60, 64, 124, 128, 200}; |
paul@123 | 209 | int i; |
paul@123 | 210 | |
paul@123 | 211 | if (!units) |
paul@123 | 212 | return 0; |
paul@123 | 213 | |
paul@123 | 214 | for (i = 0; i < 15; i++) |
paul@123 | 215 | { |
paul@123 | 216 | if (lengths[i++] >= units) |
paul@123 | 217 | break; |
paul@123 | 218 | } |
paul@123 | 219 | |
paul@123 | 220 | return lengths[i] << Dma_req_detect_int_length; |
paul@123 | 221 | } |
paul@123 | 222 | |
paul@123 | 223 | // Encode the appropriate source port width for the given request type. |
paul@123 | 224 | |
paul@123 | 225 | uint32_t |
paul@123 | 226 | Dma_jz4730_channel::encode_source_port_width(enum Dma_jz4730_request_type type) |
paul@123 | 227 | { |
paul@123 | 228 | switch (type) |
paul@123 | 229 | { |
paul@123 | 230 | case Dma_request_uart3_in: |
paul@123 | 231 | case Dma_request_uart2_in: |
paul@123 | 232 | case Dma_request_uart1_in: |
paul@123 | 233 | case Dma_request_uart0_in: |
paul@123 | 234 | return Dma_port_width_8_bit << Dma_source_port_width; |
paul@123 | 235 | |
paul@123 | 236 | default: |
paul@123 | 237 | return Dma_port_width_32_bit << Dma_source_port_width; |
paul@123 | 238 | } |
paul@123 | 239 | } |
paul@123 | 240 | |
paul@123 | 241 | // Encode the appropriate destination port width for the given request type. |
paul@123 | 242 | |
paul@123 | 243 | uint32_t |
paul@123 | 244 | Dma_jz4730_channel::encode_destination_port_width(enum Dma_jz4730_request_type type) |
paul@123 | 245 | { |
paul@123 | 246 | switch (type) |
paul@123 | 247 | { |
paul@123 | 248 | case Dma_request_uart3_out: |
paul@123 | 249 | case Dma_request_uart2_out: |
paul@123 | 250 | case Dma_request_uart1_out: |
paul@123 | 251 | case Dma_request_uart0_out: |
paul@123 | 252 | return Dma_port_width_8_bit << Dma_dest_port_width; |
paul@123 | 253 | |
paul@123 | 254 | default: |
paul@123 | 255 | return Dma_port_width_32_bit << Dma_dest_port_width; |
paul@123 | 256 | } |
paul@123 | 257 | } |
paul@123 | 258 | |
paul@123 | 259 | // Transfer data between memory locations. |
paul@123 | 260 | |
paul@123 | 261 | unsigned int |
paul@123 | 262 | Dma_jz4730_channel::transfer(uint32_t source, uint32_t destination, |
paul@123 | 263 | unsigned int count, |
paul@123 | 264 | enum Dma_jz4730_trans_unit_size size, |
paul@123 | 265 | enum Dma_jz4730_request_type type) |
paul@123 | 266 | { |
paul@123 | 267 | // Ensure an absence of address error and halt conditions globally and in this channel. |
paul@123 | 268 | |
paul@123 | 269 | if (error() || halted()) |
paul@123 | 270 | return 0; |
paul@123 | 271 | |
paul@123 | 272 | // Ensure an absence of transaction completed and zero transfer count for this channel. |
paul@123 | 273 | |
paul@123 | 274 | if (completed() || _regs[Dma_transfer_count]) |
paul@123 | 275 | return 0; |
paul@123 | 276 | |
paul@123 | 277 | // Disable the channel. |
paul@123 | 278 | |
paul@123 | 279 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_channel_enable; |
paul@123 | 280 | |
paul@123 | 281 | // Set addresses. |
paul@123 | 282 | |
paul@123 | 283 | _regs[Dma_source] = source; |
paul@123 | 284 | _regs[Dma_destination] = destination; |
paul@123 | 285 | |
paul@123 | 286 | // Set transfer count to the number of units. |
paul@123 | 287 | |
paul@123 | 288 | _regs[Dma_transfer_count] = count; |
paul@123 | 289 | |
paul@123 | 290 | // Set auto-request for memory-to-memory transfers. Otherwise, set the |
paul@123 | 291 | // indicated request type. |
paul@123 | 292 | |
paul@123 | 293 | _regs[Dma_request_source] = type; |
paul@123 | 294 | |
paul@123 | 295 | // Set control/status fields. |
paul@123 | 296 | // Enable the channel (and peripheral). |
paul@123 | 297 | |
paul@123 | 298 | /* NOTE: To be considered... |
paul@123 | 299 | * request detection interval length (currently left as 0) |
paul@123 | 300 | * increments and port widths for external transfers |
paul@123 | 301 | * port width overriding (for AIC...) |
paul@123 | 302 | * transfer mode (currently left as single) |
paul@123 | 303 | */ |
paul@123 | 304 | |
paul@123 | 305 | _regs[Dma_control_status] = encode_external_transfer(type) | |
paul@123 | 306 | encode_source_address_increment(type) | |
paul@123 | 307 | encode_destination_address_increment(type) | |
paul@123 | 308 | encode_source_port_width(type) | |
paul@123 | 309 | encode_destination_port_width(type) | |
paul@123 | 310 | (size << Dma_trans_unit_size) | |
paul@123 | 311 | (Dma_trans_mode_single << Dma_trans_mode) | |
paul@123 | 312 | Dma_channel_irq_enable | |
paul@123 | 313 | Dma_channel_enable; |
paul@123 | 314 | |
paul@123 | 315 | // An interrupt will occur upon completion, the completion flag will be set |
paul@123 | 316 | // and the transfer count will be zero. |
paul@123 | 317 | |
paul@123 | 318 | unsigned int remaining = count; |
paul@123 | 319 | |
paul@123 | 320 | do |
paul@123 | 321 | { |
paul@123 | 322 | if (!wait_for_irq(1000000)) |
paul@123 | 323 | printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); |
paul@123 | 324 | |
paul@123 | 325 | // Clearing the completion flag will clear the interrupt condition. |
paul@123 | 326 | // Any remaining units must be read before clearing the condition. |
paul@123 | 327 | |
paul@123 | 328 | else |
paul@123 | 329 | { |
paul@123 | 330 | remaining = _regs[Dma_transfer_count]; |
paul@123 | 331 | ack_irq(); |
paul@123 | 332 | break; |
paul@123 | 333 | } |
paul@123 | 334 | } |
paul@123 | 335 | while (!error() && !halted() && !completed()); |
paul@123 | 336 | |
paul@123 | 337 | // Return the number of transferred units. |
paul@123 | 338 | |
paul@123 | 339 | return count - remaining; |
paul@123 | 340 | } |
paul@123 | 341 | |
paul@123 | 342 | // Wait indefinitely for an interrupt request, returning true if one was delivered. |
paul@123 | 343 | |
paul@123 | 344 | bool |
paul@123 | 345 | Dma_jz4730_channel::wait_for_irq() |
paul@123 | 346 | { |
paul@123 | 347 | return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && _chip->have_interrupt(_channel); |
paul@123 | 348 | } |
paul@123 | 349 | |
paul@123 | 350 | // Wait up to the given timeout (in microseconds) for an interrupt request, |
paul@123 | 351 | // returning true if one was delivered. |
paul@123 | 352 | |
paul@123 | 353 | bool |
paul@123 | 354 | Dma_jz4730_channel::wait_for_irq(unsigned int timeout) |
paul@123 | 355 | { |
paul@123 | 356 | return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && _chip->have_interrupt(_channel); |
paul@123 | 357 | } |
paul@123 | 358 | |
paul@123 | 359 | // Acknowledge an interrupt condition. |
paul@123 | 360 | |
paul@123 | 361 | void |
paul@123 | 362 | Dma_jz4730_channel::ack_irq() |
paul@123 | 363 | { |
paul@123 | 364 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_trans_completed; |
paul@123 | 365 | } |
paul@123 | 366 | |
paul@123 | 367 | // Return whether a transfer has completed. |
paul@123 | 368 | |
paul@123 | 369 | bool |
paul@123 | 370 | Dma_jz4730_channel::completed() |
paul@123 | 371 | { |
paul@123 | 372 | return _regs[Dma_control_status] & Dma_trans_completed ? true : false; |
paul@123 | 373 | } |
paul@123 | 374 | |
paul@123 | 375 | // Return whether an address error condition has arisen. |
paul@123 | 376 | |
paul@123 | 377 | bool |
paul@123 | 378 | Dma_jz4730_channel::error() |
paul@123 | 379 | { |
paul@123 | 380 | return _regs[Dma_control_status] & Dma_address_error ? true : false; |
paul@123 | 381 | } |
paul@123 | 382 | |
paul@123 | 383 | // Return whether a transfer has halted. |
paul@123 | 384 | |
paul@123 | 385 | bool |
paul@123 | 386 | Dma_jz4730_channel::halted() |
paul@123 | 387 | { |
paul@123 | 388 | return _regs[Dma_control_status] & Dma_trans_halted ? true : false; |
paul@123 | 389 | } |
paul@123 | 390 | |
paul@123 | 391 | |
paul@123 | 392 | |
paul@123 | 393 | // Initialise the I2C controller. |
paul@123 | 394 | |
paul@123 | 395 | Dma_jz4730_chip::Dma_jz4730_chip(l4_addr_t start, l4_addr_t end, |
paul@123 | 396 | Cpm_jz4730_chip *cpm) |
paul@123 | 397 | : _start(start), _end(end), _cpm(cpm) |
paul@123 | 398 | { |
paul@123 | 399 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@123 | 400 | } |
paul@123 | 401 | |
paul@123 | 402 | // Enable the peripheral. |
paul@123 | 403 | |
paul@123 | 404 | void |
paul@123 | 405 | Dma_jz4730_chip::enable() |
paul@123 | 406 | { |
paul@123 | 407 | // Make sure that the DMA clock is available. |
paul@123 | 408 | |
paul@128 | 409 | _cpm->start_clock(Clock_dma); |
paul@123 | 410 | |
paul@123 | 411 | // Enable the channel. |
paul@123 | 412 | // NOTE: No configuration is done for channel priority mode. |
paul@123 | 413 | |
paul@123 | 414 | _regs[Dma_control] = Dma_control_enable; |
paul@123 | 415 | while (!(_regs[Dma_control] & Dma_control_enable)); |
paul@123 | 416 | } |
paul@123 | 417 | |
paul@123 | 418 | // Disable the channel. |
paul@123 | 419 | |
paul@123 | 420 | void |
paul@123 | 421 | Dma_jz4730_chip::disable() |
paul@123 | 422 | { |
paul@123 | 423 | _regs[Dma_control] = 0; |
paul@123 | 424 | while (_regs[Dma_control] & Dma_control_enable); |
paul@123 | 425 | } |
paul@123 | 426 | |
paul@123 | 427 | // Obtain a channel object. Only one channel is supported. |
paul@123 | 428 | |
paul@123 | 429 | Dma_jz4730_channel * |
paul@123 | 430 | Dma_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) |
paul@123 | 431 | { |
paul@123 | 432 | if (channel < 6) |
paul@123 | 433 | return new Dma_jz4730_channel(this, channel, _start + 0x20 * channel, irq); |
paul@123 | 434 | else |
paul@123 | 435 | throw -L4_EINVAL; |
paul@123 | 436 | } |
paul@123 | 437 | |
paul@123 | 438 | // Return whether an interrupt is pending on the given channel. |
paul@123 | 439 | |
paul@123 | 440 | bool |
paul@123 | 441 | Dma_jz4730_chip::have_interrupt(uint8_t channel) |
paul@123 | 442 | { |
paul@123 | 443 | return _regs[Dma_irq_pending] & (1 << (Dma_irq_pending_ch0 - channel)) ? true : false; |
paul@123 | 444 | } |
paul@123 | 445 | |
paul@123 | 446 | |
paul@123 | 447 | |
paul@123 | 448 | // C language interface functions. |
paul@123 | 449 | |
paul@123 | 450 | void *jz4730_dma_init(l4_addr_t start, l4_addr_t end, void *cpm) |
paul@123 | 451 | { |
paul@123 | 452 | return (void *) new Dma_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm)); |
paul@123 | 453 | } |
paul@123 | 454 | |
paul@123 | 455 | void jz4730_dma_disable(void *dma_chip) |
paul@123 | 456 | { |
paul@123 | 457 | static_cast<Dma_jz4730_chip *>(dma_chip)->disable(); |
paul@123 | 458 | } |
paul@123 | 459 | |
paul@123 | 460 | void jz4730_dma_enable(void *dma_chip) |
paul@123 | 461 | { |
paul@123 | 462 | static_cast<Dma_jz4730_chip *>(dma_chip)->enable(); |
paul@123 | 463 | } |
paul@123 | 464 | |
paul@123 | 465 | void *jz4730_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq) |
paul@123 | 466 | { |
paul@123 | 467 | return static_cast<Dma_jz4730_chip *>(dma)->get_channel(channel, irq); |
paul@123 | 468 | } |
paul@123 | 469 | |
paul@123 | 470 | void jz4730_dma_set_output_polarity(void *dma_channel, enum Dma_jz4730_ext_level polarity) |
paul@123 | 471 | { |
paul@123 | 472 | static_cast<Dma_jz4730_channel *>(dma_channel)->set_output_polarity(polarity); |
paul@123 | 473 | } |
paul@123 | 474 | |
paul@123 | 475 | void jz4730_dma_set_end_of_process_mode(void *dma_channel, enum Dma_jz4730_ext_level mode) |
paul@123 | 476 | { |
paul@123 | 477 | static_cast<Dma_jz4730_channel *>(dma_channel)->set_end_of_process_mode(mode); |
paul@123 | 478 | } |
paul@123 | 479 | |
paul@123 | 480 | void jz4730_dma_set_output_mode_cycle(void *dma_channel, enum Dma_jz4730_ext_output_mode_cycle cycle) |
paul@123 | 481 | { |
paul@123 | 482 | static_cast<Dma_jz4730_channel *>(dma_channel)->set_output_mode_cycle(cycle); |
paul@123 | 483 | } |
paul@123 | 484 | |
paul@123 | 485 | void jz4730_dma_set_req_detect_mode(void *dma_channel, enum Dma_jz4730_ext_req_detect_mode mode) |
paul@123 | 486 | { |
paul@123 | 487 | static_cast<Dma_jz4730_channel *>(dma_channel)->set_req_detect_mode(mode); |
paul@123 | 488 | } |
paul@123 | 489 | |
paul@123 | 490 | unsigned int jz4730_dma_transfer(void *dma_channel, uint32_t source, |
paul@123 | 491 | uint32_t destination, unsigned int count, |
paul@123 | 492 | enum Dma_jz4730_trans_unit_size size, |
paul@123 | 493 | enum Dma_jz4730_request_type type) |
paul@123 | 494 | { |
paul@123 | 495 | return static_cast<Dma_jz4730_channel *>(dma_channel)->transfer(source, destination, count, size, type); |
paul@123 | 496 | } |