paul@173 | 1 | /* |
paul@173 | 2 | * Common clock functionality. |
paul@173 | 3 | * |
paul@173 | 4 | * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> |
paul@173 | 5 | * |
paul@173 | 6 | * This program is free software; you can redistribute it and/or |
paul@173 | 7 | * modify it under the terms of the GNU General Public License as |
paul@173 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@173 | 9 | * the License, or (at your option) any later version. |
paul@173 | 10 | * |
paul@173 | 11 | * This program is distributed in the hope that it will be useful, |
paul@173 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@173 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@173 | 14 | * GNU General Public License for more details. |
paul@173 | 15 | * |
paul@173 | 16 | * You should have received a copy of the GNU General Public License |
paul@173 | 17 | * along with this program; if not, write to the Free Software |
paul@173 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@173 | 19 | * Boston, MA 02110-1301, USA |
paul@173 | 20 | */ |
paul@173 | 21 | |
paul@173 | 22 | #include <l4/devices/hw_mmio_register_block.h> |
paul@173 | 23 | |
paul@173 | 24 | #include "cpm-common.h" |
paul@173 | 25 | #include <math.h> |
paul@185 | 26 | #include <stdio.h> |
paul@173 | 27 | |
paul@173 | 28 | |
paul@173 | 29 | |
paul@173 | 30 | // Register access. |
paul@173 | 31 | |
paul@211 | 32 | Cpm_regs::Cpm_regs(l4_addr_t addr, Clock_base *clocks[]) |
paul@211 | 33 | : _clocks(clocks) |
paul@173 | 34 | { |
paul@173 | 35 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@173 | 36 | } |
paul@173 | 37 | |
paul@173 | 38 | // Utility methods. |
paul@173 | 39 | |
paul@173 | 40 | uint32_t |
paul@173 | 41 | Cpm_regs::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@173 | 42 | { |
paul@173 | 43 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@173 | 44 | } |
paul@173 | 45 | |
paul@173 | 46 | void |
paul@173 | 47 | Cpm_regs::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@173 | 48 | { |
paul@173 | 49 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@173 | 50 | } |
paul@173 | 51 | |
paul@173 | 52 | Clock_base * |
paul@173 | 53 | Cpm_regs::get_clock(int num) |
paul@173 | 54 | { |
paul@173 | 55 | return _clocks[num]; |
paul@173 | 56 | } |
paul@173 | 57 | |
paul@173 | 58 | |
paul@173 | 59 | |
paul@173 | 60 | // Field methods. |
paul@173 | 61 | |
paul@173 | 62 | uint32_t |
paul@173 | 63 | Field::get_field(Cpm_regs ®s) |
paul@173 | 64 | { |
paul@173 | 65 | if (defined) |
paul@247 | 66 | return regs.get_field(reg, mask, bit) + adjustment; |
paul@173 | 67 | else |
paul@173 | 68 | return 0; |
paul@173 | 69 | } |
paul@173 | 70 | |
paul@173 | 71 | void |
paul@173 | 72 | Field::set_field(Cpm_regs ®s, uint32_t value) |
paul@173 | 73 | { |
paul@173 | 74 | if (defined) |
paul@247 | 75 | regs.set_field(reg, mask, bit, value >= adjustment ? value - adjustment : 0); |
paul@173 | 76 | } |
paul@173 | 77 | |
paul@173 | 78 | // Undefined field. |
paul@173 | 79 | |
paul@173 | 80 | Field Field::undefined; |
paul@173 | 81 | |
paul@173 | 82 | |
paul@173 | 83 | |
paul@173 | 84 | // Clock sources. |
paul@173 | 85 | |
paul@173 | 86 | enum Clock_identifiers |
paul@173 | 87 | Mux::get_input(int num) |
paul@173 | 88 | { |
paul@173 | 89 | if (num < _num_inputs) |
paul@173 | 90 | return _inputs[num]; |
paul@173 | 91 | else |
paul@243 | 92 | return Clock_none; |
paul@173 | 93 | } |
paul@173 | 94 | |
paul@243 | 95 | |
paul@243 | 96 | |
paul@173 | 97 | // Clock sources. |
paul@173 | 98 | |
paul@173 | 99 | uint8_t |
paul@173 | 100 | Source::get_source(Cpm_regs ®s) |
paul@173 | 101 | { |
paul@173 | 102 | if (_source.is_defined()) |
paul@173 | 103 | return _source.get_field(regs); |
paul@173 | 104 | else |
paul@173 | 105 | return 0; |
paul@173 | 106 | } |
paul@173 | 107 | |
paul@173 | 108 | void |
paul@173 | 109 | Source::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 110 | { |
paul@173 | 111 | if (!_source.is_defined()) |
paul@173 | 112 | return; |
paul@173 | 113 | |
paul@173 | 114 | _source.set_field(regs, source); |
paul@173 | 115 | } |
paul@173 | 116 | |
paul@185 | 117 | enum Clock_identifiers |
paul@185 | 118 | Source::get_source_clock(Cpm_regs ®s) |
paul@185 | 119 | { |
paul@185 | 120 | return get_input(get_number() == 1 ? 0 : get_source(regs)); |
paul@185 | 121 | } |
paul@185 | 122 | |
paul@185 | 123 | void |
paul@185 | 124 | Source::set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock) |
paul@185 | 125 | { |
paul@185 | 126 | for (int source = 0; source < _inputs.get_number(); source++) |
paul@185 | 127 | if (get_input(source) == clock) |
paul@185 | 128 | _source.set_field(regs, source); |
paul@185 | 129 | } |
paul@185 | 130 | |
paul@173 | 131 | // Clock source frequencies. |
paul@173 | 132 | |
paul@213 | 133 | uint64_t |
paul@173 | 134 | Source::get_frequency(Cpm_regs ®s) |
paul@173 | 135 | { |
paul@185 | 136 | enum Clock_identifiers input = get_source_clock(regs); |
paul@173 | 137 | |
paul@243 | 138 | if (input != Clock_none) |
paul@173 | 139 | return regs.get_clock(input)->get_frequency(regs); |
paul@173 | 140 | else |
paul@173 | 141 | return 0; |
paul@173 | 142 | } |
paul@173 | 143 | |
paul@173 | 144 | |
paul@173 | 145 | |
paul@175 | 146 | // Clock control. |
paul@175 | 147 | |
paul@175 | 148 | Control_base::~Control_base() |
paul@175 | 149 | { |
paul@175 | 150 | } |
paul@175 | 151 | |
paul@175 | 152 | void |
paul@175 | 153 | Control_base::change_disable(Cpm_regs ®s) |
paul@175 | 154 | { |
paul@175 | 155 | (void) regs; |
paul@175 | 156 | } |
paul@175 | 157 | |
paul@175 | 158 | void |
paul@175 | 159 | Control_base::change_enable(Cpm_regs ®s) |
paul@175 | 160 | { |
paul@175 | 161 | (void) regs; |
paul@175 | 162 | } |
paul@175 | 163 | |
paul@175 | 164 | int |
paul@175 | 165 | Control::have_clock(Cpm_regs ®s) |
paul@175 | 166 | { |
paul@175 | 167 | if (_gate.is_defined()) |
paul@201 | 168 | return _gate.get_field(regs) == _gate.get_asserted(); |
paul@175 | 169 | else |
paul@175 | 170 | return true; |
paul@175 | 171 | } |
paul@175 | 172 | |
paul@175 | 173 | void |
paul@175 | 174 | Control::start_clock(Cpm_regs ®s) |
paul@175 | 175 | { |
paul@175 | 176 | if (_gate.is_defined()) |
paul@201 | 177 | _gate.set_field(regs, _gate.get_asserted()); |
paul@175 | 178 | } |
paul@175 | 179 | |
paul@175 | 180 | void |
paul@175 | 181 | Control::stop_clock(Cpm_regs ®s) |
paul@175 | 182 | { |
paul@175 | 183 | if (_gate.is_defined()) |
paul@201 | 184 | _gate.set_field(regs, _gate.get_deasserted()); |
paul@175 | 185 | } |
paul@175 | 186 | |
paul@175 | 187 | void |
paul@175 | 188 | Control::wait_busy(Cpm_regs ®s) |
paul@175 | 189 | { |
paul@175 | 190 | if (_busy.is_defined()) |
paul@175 | 191 | while (_busy.get_field(regs)); |
paul@175 | 192 | } |
paul@175 | 193 | |
paul@175 | 194 | void |
paul@175 | 195 | Control::change_disable(Cpm_regs ®s) |
paul@175 | 196 | { |
paul@175 | 197 | if (_change_enable.is_defined()) |
paul@175 | 198 | _change_enable.set_field(regs, 0); |
paul@175 | 199 | } |
paul@175 | 200 | |
paul@175 | 201 | void |
paul@175 | 202 | Control::change_enable(Cpm_regs ®s) |
paul@175 | 203 | { |
paul@175 | 204 | if (_change_enable.is_defined()) |
paul@175 | 205 | _change_enable.set_field(regs, 1); |
paul@175 | 206 | } |
paul@175 | 207 | |
paul@211 | 208 | // Undefined control. |
paul@211 | 209 | |
paul@211 | 210 | Control Control::undefined; |
paul@211 | 211 | |
paul@175 | 212 | |
paul@175 | 213 | |
paul@175 | 214 | // PLL-specific control. |
paul@175 | 215 | |
paul@175 | 216 | int |
paul@175 | 217 | Control_pll::have_pll(Cpm_regs ®s) |
paul@175 | 218 | { |
paul@175 | 219 | return _stable.get_field(regs); |
paul@175 | 220 | } |
paul@175 | 221 | |
paul@175 | 222 | int |
paul@175 | 223 | Control_pll::pll_enabled(Cpm_regs ®s) |
paul@175 | 224 | { |
paul@175 | 225 | return _enable.get_field(regs); |
paul@175 | 226 | } |
paul@175 | 227 | |
paul@175 | 228 | int |
paul@175 | 229 | Control_pll::pll_bypassed(Cpm_regs ®s) |
paul@175 | 230 | { |
paul@175 | 231 | return _bypass.get_field(regs); |
paul@175 | 232 | } |
paul@175 | 233 | |
paul@187 | 234 | void |
paul@187 | 235 | Control_pll::pll_bypass(Cpm_regs ®s) |
paul@187 | 236 | { |
paul@187 | 237 | _bypass.set_field(regs, 1); |
paul@187 | 238 | } |
paul@187 | 239 | |
paul@187 | 240 | void |
paul@187 | 241 | Control_pll::pll_engage(Cpm_regs ®s) |
paul@187 | 242 | { |
paul@187 | 243 | _bypass.set_field(regs, 0); |
paul@187 | 244 | } |
paul@187 | 245 | |
paul@175 | 246 | // Clock control. |
paul@175 | 247 | |
paul@175 | 248 | int |
paul@175 | 249 | Control_pll::have_clock(Cpm_regs ®s) |
paul@175 | 250 | { |
paul@175 | 251 | return have_pll(regs) && pll_enabled(regs); |
paul@175 | 252 | } |
paul@175 | 253 | |
paul@175 | 254 | void |
paul@175 | 255 | Control_pll::start_clock(Cpm_regs ®s) |
paul@175 | 256 | { |
paul@175 | 257 | _enable.set_field(regs, 1); |
paul@175 | 258 | while (!have_pll(regs)); |
paul@175 | 259 | } |
paul@175 | 260 | |
paul@175 | 261 | void |
paul@175 | 262 | Control_pll::stop_clock(Cpm_regs ®s) |
paul@175 | 263 | { |
paul@175 | 264 | _enable.set_field(regs, 0); |
paul@175 | 265 | while (have_pll(regs)); |
paul@175 | 266 | } |
paul@175 | 267 | |
paul@175 | 268 | void |
paul@175 | 269 | Control_pll::wait_busy(Cpm_regs ®s) |
paul@175 | 270 | { |
paul@213 | 271 | // NOTE: Could wait for some kind of stable or "lock" signal, but the chips |
paul@213 | 272 | // provide all sorts of differing signals. |
paul@213 | 273 | |
paul@213 | 274 | (void) regs; |
paul@213 | 275 | } |
paul@213 | 276 | |
paul@213 | 277 | void |
paul@213 | 278 | Control_pll::change_disable(Cpm_regs ®s) |
paul@213 | 279 | { |
paul@213 | 280 | if (_enabled) |
paul@213 | 281 | start_clock(regs); |
paul@213 | 282 | } |
paul@213 | 283 | |
paul@213 | 284 | void |
paul@213 | 285 | Control_pll::change_enable(Cpm_regs ®s) |
paul@213 | 286 | { |
paul@213 | 287 | // NOTE: Since the X1600 manual warns of changing the frequency while enabled, |
paul@213 | 288 | // it is easier to just stop and then start the PLL again. |
paul@213 | 289 | |
paul@213 | 290 | _enabled = have_clock(regs); |
paul@213 | 291 | |
paul@213 | 292 | if (_enabled) |
paul@213 | 293 | stop_clock(regs); |
paul@175 | 294 | } |
paul@175 | 295 | |
paul@175 | 296 | |
paul@175 | 297 | |
paul@174 | 298 | // Clock dividers. |
paul@174 | 299 | |
paul@175 | 300 | Divider_base::~Divider_base() |
paul@175 | 301 | { |
paul@175 | 302 | } |
paul@175 | 303 | |
paul@175 | 304 | |
paul@175 | 305 | |
paul@239 | 306 | // Fixed divider. |
paul@239 | 307 | |
paul@239 | 308 | uint64_t |
paul@239 | 309 | Divider_fixed::get_frequency(Cpm_regs ®s, uint64_t source_frequency) |
paul@239 | 310 | { |
paul@239 | 311 | (void) regs; |
paul@239 | 312 | return source_frequency / _value; |
paul@239 | 313 | } |
paul@239 | 314 | |
paul@239 | 315 | int |
paul@239 | 316 | Divider_fixed::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) |
paul@239 | 317 | { |
paul@239 | 318 | (void) regs; (void) source_frequency; (void) frequency; |
paul@239 | 319 | return 0; |
paul@239 | 320 | } |
paul@239 | 321 | |
paul@239 | 322 | int |
paul@239 | 323 | Divider_fixed::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@239 | 324 | { |
paul@239 | 325 | (void) regs; |
paul@239 | 326 | parameters[0] = _value; |
paul@239 | 327 | return 1; |
paul@239 | 328 | } |
paul@239 | 329 | |
paul@239 | 330 | int |
paul@239 | 331 | Divider_fixed::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@239 | 332 | { |
paul@239 | 333 | (void) regs; (void) num_parameters; (void) parameters; |
paul@239 | 334 | return 0; |
paul@239 | 335 | } |
paul@239 | 336 | |
paul@239 | 337 | |
paul@239 | 338 | |
paul@239 | 339 | // Simple divider for regular clocks. |
paul@239 | 340 | |
paul@174 | 341 | uint32_t |
paul@174 | 342 | Divider::get_divider(Cpm_regs ®s) |
paul@174 | 343 | { |
paul@174 | 344 | if (_divider.is_defined()) |
paul@244 | 345 | return _scale * (_divider.get_field(regs) + 1); |
paul@174 | 346 | else |
paul@174 | 347 | return 1; |
paul@174 | 348 | } |
paul@174 | 349 | |
paul@174 | 350 | void |
paul@175 | 351 | Divider::set_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 352 | { |
paul@174 | 353 | if (_divider.is_defined()) |
paul@244 | 354 | _divider.set_field(regs, divider / _scale - 1); |
paul@174 | 355 | } |
paul@174 | 356 | |
paul@174 | 357 | // Output clock frequencies. |
paul@174 | 358 | |
paul@213 | 359 | uint64_t |
paul@213 | 360 | Divider::get_frequency(Cpm_regs ®s, uint64_t source_frequency) |
paul@174 | 361 | { |
paul@174 | 362 | return source_frequency / get_divider(regs); |
paul@174 | 363 | } |
paul@174 | 364 | |
paul@178 | 365 | int |
paul@213 | 366 | Divider::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) |
paul@187 | 367 | { |
paul@187 | 368 | set_divider(regs, (uint32_t) round((double) source_frequency / (double) frequency)); |
paul@187 | 369 | return 1; |
paul@187 | 370 | } |
paul@187 | 371 | |
paul@187 | 372 | int |
paul@178 | 373 | Divider::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 374 | { |
paul@178 | 375 | parameters[0] = get_divider(regs); |
paul@178 | 376 | return 1; |
paul@178 | 377 | } |
paul@178 | 378 | |
paul@185 | 379 | int |
paul@185 | 380 | Divider::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@178 | 381 | { |
paul@185 | 382 | if (num_parameters) |
paul@185 | 383 | { |
paul@185 | 384 | set_divider(regs, parameters[0]); |
paul@185 | 385 | return 1; |
paul@185 | 386 | } |
paul@185 | 387 | |
paul@185 | 388 | return 0; |
paul@178 | 389 | } |
paul@178 | 390 | |
paul@174 | 391 | |
paul@174 | 392 | |
paul@187 | 393 | // Common divider functionality. |
paul@187 | 394 | |
paul@187 | 395 | static int is_integer(double x) |
paul@187 | 396 | { |
paul@187 | 397 | double target = round(x) * 1000; |
paul@187 | 398 | double rounded = floor(x * 1000); |
paul@187 | 399 | |
paul@187 | 400 | return (target - 100 < rounded) && (rounded < target + 100); |
paul@187 | 401 | } |
paul@187 | 402 | |
paul@187 | 403 | static double getscale_part(double x) |
paul@187 | 404 | { |
paul@187 | 405 | double part = x - floor(x); |
paul@187 | 406 | |
paul@187 | 407 | if (part > 0.5) |
paul@187 | 408 | return 1 / (1 - part); |
paul@187 | 409 | else if (part > 0) |
paul@187 | 410 | return 1 / part; |
paul@187 | 411 | else |
paul@187 | 412 | return 1; |
paul@187 | 413 | } |
paul@187 | 414 | |
paul@187 | 415 | static double getscale(double x) |
paul@187 | 416 | { |
paul@187 | 417 | double scale = getscale_part(x); |
paul@187 | 418 | |
paul@187 | 419 | if (is_integer(scale)) |
paul@187 | 420 | return scale; |
paul@187 | 421 | else |
paul@187 | 422 | return scale * getscale(scale); |
paul@187 | 423 | } |
paul@187 | 424 | |
paul@187 | 425 | static void get_divider_operands(double frequency, double source_frequency, |
paul@187 | 426 | double *multiplier, double *divider) |
paul@187 | 427 | { |
paul@187 | 428 | double ratio = frequency / source_frequency; |
paul@187 | 429 | double scale = getscale(ratio); |
paul@187 | 430 | |
paul@187 | 431 | *multiplier = scale * ratio; |
paul@187 | 432 | *divider = scale; |
paul@187 | 433 | } |
paul@187 | 434 | |
paul@187 | 435 | static void reduce_divider_operands(uint32_t *m, uint32_t *n, uint32_t m_limit, |
paul@187 | 436 | uint32_t n_limit) |
paul@187 | 437 | { |
paul@187 | 438 | while ((*m > m_limit) && (*n > n_limit) && (*m > 1) && (*n > 1)) |
paul@187 | 439 | { |
paul@187 | 440 | *m >>= 1; |
paul@187 | 441 | *n >>= 1; |
paul@187 | 442 | } |
paul@187 | 443 | } |
paul@187 | 444 | |
paul@187 | 445 | |
paul@187 | 446 | |
paul@219 | 447 | #define zero_as_one(X) ((X) ? (X) : 1) |
paul@187 | 448 | |
paul@187 | 449 | // Feedback multiplier. |
paul@174 | 450 | |
paul@175 | 451 | uint32_t |
paul@174 | 452 | Divider_pll::get_multiplier(Cpm_regs ®s) |
paul@174 | 453 | { |
paul@247 | 454 | return zero_as_one(_multiplier.get_field(regs)); |
paul@174 | 455 | } |
paul@174 | 456 | |
paul@174 | 457 | void |
paul@175 | 458 | Divider_pll::set_multiplier(Cpm_regs ®s, uint32_t multiplier) |
paul@174 | 459 | { |
paul@247 | 460 | _multiplier.set_field(regs, multiplier); |
paul@174 | 461 | } |
paul@174 | 462 | |
paul@187 | 463 | // Input divider. |
paul@174 | 464 | |
paul@175 | 465 | uint32_t |
paul@175 | 466 | Divider_pll::get_input_divider(Cpm_regs ®s) |
paul@174 | 467 | { |
paul@247 | 468 | return zero_as_one(_input_divider.get_field(regs)); |
paul@174 | 469 | } |
paul@174 | 470 | |
paul@174 | 471 | void |
paul@175 | 472 | Divider_pll::set_input_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 473 | { |
paul@247 | 474 | _input_divider.set_field(regs, divider); |
paul@174 | 475 | } |
paul@174 | 476 | |
paul@187 | 477 | // Output dividers. |
paul@174 | 478 | |
paul@175 | 479 | uint32_t |
paul@175 | 480 | Divider_pll::get_output_divider(Cpm_regs ®s) |
paul@174 | 481 | { |
paul@219 | 482 | uint32_t d0, d1; |
paul@219 | 483 | |
paul@247 | 484 | d0 = zero_as_one(_output_divider0.get_field(regs)); |
paul@247 | 485 | d1 = _output_divider1.is_defined() ? |
paul@247 | 486 | zero_as_one(_output_divider1.get_field(regs)) : 1; |
paul@174 | 487 | |
paul@174 | 488 | return d0 * d1; |
paul@174 | 489 | } |
paul@174 | 490 | |
paul@174 | 491 | void |
paul@175 | 492 | Divider_pll::set_output_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 493 | { |
paul@211 | 494 | uint32_t d0, d1; |
paul@211 | 495 | |
paul@174 | 496 | // Assert 1 as a minimum. |
paul@187 | 497 | |
paul@187 | 498 | if (!divider) |
paul@187 | 499 | divider = 1; |
paul@187 | 500 | |
paul@211 | 501 | // Attempt to set any single divider. |
paul@211 | 502 | |
paul@211 | 503 | if (!_output_divider1.is_defined()) |
paul@211 | 504 | { |
paul@247 | 505 | _output_divider0.set_field(regs, divider); |
paul@211 | 506 | return; |
paul@211 | 507 | } |
paul@211 | 508 | |
paul@211 | 509 | // For two-divider implementations such as the X1600, divider 0 must be less |
paul@211 | 510 | // than or equal to divider 1. |
paul@211 | 511 | |
paul@187 | 512 | if (divider < _output_divider1.get_limit()) |
paul@187 | 513 | { |
paul@187 | 514 | d0 = 1; |
paul@187 | 515 | d1 = divider; |
paul@187 | 516 | } |
paul@187 | 517 | else |
paul@187 | 518 | { |
paul@187 | 519 | d0 = (uint32_t) floor(sqrt(divider)); |
paul@187 | 520 | d1 = divider / d0; |
paul@187 | 521 | } |
paul@174 | 522 | |
paul@247 | 523 | _output_divider0.set_field(regs, d0); |
paul@247 | 524 | _output_divider1.set_field(regs, d1); |
paul@174 | 525 | } |
paul@174 | 526 | |
paul@213 | 527 | uint64_t |
paul@213 | 528 | Divider_pll::get_frequency(Cpm_regs ®s, uint64_t source_frequency) |
paul@174 | 529 | { |
paul@174 | 530 | return (source_frequency * get_multiplier(regs)) / |
paul@175 | 531 | (get_input_divider(regs) * get_output_divider(regs)); |
paul@174 | 532 | } |
paul@174 | 533 | |
paul@178 | 534 | int |
paul@213 | 535 | Divider_pll::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) |
paul@187 | 536 | { |
paul@187 | 537 | double intermediate_multiplier, intermediate_input_divider; |
paul@187 | 538 | uint32_t output_min, output_max, output0, output1; |
paul@187 | 539 | uint32_t multiplier, input_divider, output_divider; |
paul@187 | 540 | |
paul@211 | 541 | // Define the range for the output dividers using the intermediate frequency |
paul@211 | 542 | // range applying to each chip, this being the result of the multiplier and |
paul@211 | 543 | // input divider. |
paul@187 | 544 | |
paul@211 | 545 | output_min = (uint32_t) ceil(_intermediate_min / frequency); |
paul@211 | 546 | output_max = (uint32_t) floor(_intermediate_max / frequency); |
paul@211 | 547 | |
paul@211 | 548 | // Distribute the divider across the input and output dividers. |
paul@187 | 549 | |
paul@187 | 550 | output_divider = output_min; |
paul@187 | 551 | |
paul@187 | 552 | while (output_divider <= output_max) |
paul@187 | 553 | { |
paul@211 | 554 | bool usable_divider; |
paul@211 | 555 | |
paul@187 | 556 | // Test divider constraints. |
paul@187 | 557 | |
paul@211 | 558 | if (_output_divider1.is_defined()) |
paul@211 | 559 | { |
paul@211 | 560 | output0 = (uint32_t) floor(sqrt(output_divider)); |
paul@211 | 561 | output1 = (uint32_t) floor(output_divider / output0); |
paul@187 | 562 | |
paul@211 | 563 | usable_divider = ((output0 * output1 == output_divider) && |
paul@187 | 564 | (output0 <= _output_divider0.get_limit()) && |
paul@211 | 565 | (output1 <= _output_divider1.get_limit())); |
paul@211 | 566 | } |
paul@211 | 567 | else |
paul@211 | 568 | usable_divider = output_divider <= _output_divider0.get_limit(); |
paul@211 | 569 | |
paul@211 | 570 | // Apply any usable divider. |
paul@211 | 571 | |
paul@211 | 572 | if (usable_divider) |
paul@187 | 573 | { |
paul@211 | 574 | // Calculate the other parameters. Start by working back from the desired |
paul@211 | 575 | // output frequency to obtain an intermediate frequency using the proposed |
paul@211 | 576 | // divider. |
paul@187 | 577 | |
paul@213 | 578 | double intermediate_frequency = frequency * output_divider; |
paul@187 | 579 | |
paul@211 | 580 | // Calculate the required multiplier and divider. |
paul@211 | 581 | |
paul@187 | 582 | get_divider_operands(intermediate_frequency, source_frequency, |
paul@187 | 583 | &intermediate_multiplier, &intermediate_input_divider); |
paul@187 | 584 | |
paul@187 | 585 | multiplier = (uint32_t) round(intermediate_multiplier); |
paul@187 | 586 | input_divider = (uint32_t) round(intermediate_input_divider); |
paul@187 | 587 | |
paul@211 | 588 | // Attempt to reduce the multiplier and divider to usable values. |
paul@211 | 589 | |
paul@187 | 590 | uint32_t multiplier_limit = _multiplier.get_limit(); |
paul@187 | 591 | uint32_t input_divider_limit = _input_divider.get_limit(); |
paul@187 | 592 | |
paul@187 | 593 | reduce_divider_operands(&multiplier, &input_divider, |
paul@187 | 594 | multiplier_limit, input_divider_limit); |
paul@187 | 595 | |
paul@187 | 596 | if ((multiplier <= multiplier_limit) && (input_divider <= input_divider_limit)) |
paul@187 | 597 | { |
paul@187 | 598 | set_multiplier(regs, multiplier); |
paul@187 | 599 | set_input_divider(regs, input_divider); |
paul@187 | 600 | set_output_divider(regs, output_divider); |
paul@187 | 601 | |
paul@187 | 602 | return 1; |
paul@187 | 603 | } |
paul@187 | 604 | } |
paul@187 | 605 | |
paul@187 | 606 | output_divider++; |
paul@187 | 607 | } |
paul@187 | 608 | |
paul@187 | 609 | return 0; |
paul@187 | 610 | } |
paul@187 | 611 | |
paul@187 | 612 | int |
paul@178 | 613 | Divider_pll::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@174 | 614 | { |
paul@178 | 615 | parameters[0] = get_multiplier(regs); |
paul@178 | 616 | parameters[1] = get_input_divider(regs); |
paul@178 | 617 | parameters[2] = get_output_divider(regs); |
paul@178 | 618 | return 3; |
paul@178 | 619 | } |
paul@178 | 620 | |
paul@185 | 621 | int |
paul@185 | 622 | Divider_pll::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@178 | 623 | { |
paul@185 | 624 | if (num_parameters > 2) |
paul@185 | 625 | { |
paul@185 | 626 | set_multiplier(regs, parameters[0]); |
paul@185 | 627 | set_input_divider(regs, parameters[1]); |
paul@185 | 628 | set_output_divider(regs, parameters[2]); |
paul@185 | 629 | |
paul@185 | 630 | return 3; |
paul@185 | 631 | } |
paul@185 | 632 | |
paul@185 | 633 | return 0; |
paul@174 | 634 | } |
paul@174 | 635 | |
paul@174 | 636 | |
paul@174 | 637 | |
paul@175 | 638 | // I2S clock divider. |
paul@175 | 639 | |
paul@175 | 640 | uint32_t |
paul@175 | 641 | Divider_i2s::get_multiplier(Cpm_regs ®s) |
paul@175 | 642 | { |
paul@175 | 643 | return _multiplier.get_field(regs); |
paul@175 | 644 | } |
paul@175 | 645 | |
paul@175 | 646 | uint32_t |
paul@178 | 647 | Divider_i2s::get_divider_N(Cpm_regs ®s) |
paul@178 | 648 | { |
paul@178 | 649 | return _divider_N.get_field(regs); |
paul@178 | 650 | } |
paul@178 | 651 | |
paul@178 | 652 | uint32_t |
paul@175 | 653 | Divider_i2s::get_divider_D(Cpm_regs ®s) |
paul@175 | 654 | { |
paul@175 | 655 | return _divider_D.get_field(regs); |
paul@175 | 656 | } |
paul@175 | 657 | |
paul@213 | 658 | uint64_t |
paul@213 | 659 | Divider_i2s::get_frequency(Cpm_regs ®s, uint64_t source_frequency) |
paul@175 | 660 | { |
paul@187 | 661 | /* NOTE: Assuming that this is the formula, given that the manual does not |
paul@187 | 662 | really describe how D is used. */ |
paul@187 | 663 | |
paul@175 | 664 | return (source_frequency * get_multiplier(regs)) / |
paul@175 | 665 | (get_divider_N(regs) * get_divider_D(regs)); |
paul@175 | 666 | } |
paul@175 | 667 | |
paul@178 | 668 | int |
paul@213 | 669 | Divider_i2s::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) |
paul@187 | 670 | { |
paul@187 | 671 | double m, n; |
paul@187 | 672 | |
paul@187 | 673 | get_divider_operands(frequency, source_frequency, &m, &n); |
paul@187 | 674 | |
paul@187 | 675 | uint32_t multiplier = (uint32_t) round(m); |
paul@187 | 676 | uint32_t divider = (uint32_t) round(n); |
paul@187 | 677 | |
paul@187 | 678 | reduce_divider_operands(&multiplier, ÷r, |
paul@187 | 679 | _multiplier.get_limit(), |
paul@187 | 680 | _divider_N.get_limit()); |
paul@187 | 681 | |
paul@187 | 682 | // Test for operand within limits and the N >= 2M constraint. |
paul@187 | 683 | |
paul@187 | 684 | if ((multiplier <= _multiplier.get_limit()) && (divider <= _divider_N.get_limit()) && |
paul@187 | 685 | (divider >= 2 * multiplier)) |
paul@187 | 686 | { |
paul@187 | 687 | /* NOTE: Setting D to 1. Even though it seems that D might also be used, |
paul@187 | 688 | it does not seem necessary in practice, and the documentation is |
paul@187 | 689 | unclear about its use. */ |
paul@187 | 690 | |
paul@187 | 691 | uint32_t parameters[] = {multiplier, divider, 1}; |
paul@187 | 692 | |
paul@187 | 693 | set_parameters(regs, 3, parameters); |
paul@187 | 694 | return 1; |
paul@187 | 695 | } |
paul@187 | 696 | |
paul@187 | 697 | return 0; |
paul@187 | 698 | } |
paul@187 | 699 | |
paul@187 | 700 | int |
paul@178 | 701 | Divider_i2s::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 702 | { |
paul@178 | 703 | parameters[0] = get_multiplier(regs); |
paul@178 | 704 | parameters[1] = get_divider_N(regs); |
paul@178 | 705 | parameters[2] = get_divider_D(regs); |
paul@178 | 706 | return 3; |
paul@178 | 707 | } |
paul@178 | 708 | |
paul@185 | 709 | int |
paul@185 | 710 | Divider_i2s::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@175 | 711 | { |
paul@185 | 712 | if (num_parameters == 1) |
paul@185 | 713 | { |
paul@185 | 714 | // Set automatic N and D value calculation if only one parameter is given. |
paul@185 | 715 | |
paul@185 | 716 | _auto_N.set_field(regs, 0); |
paul@185 | 717 | _auto_D.set_field(regs, 0); |
paul@185 | 718 | _multiplier.set_field(regs, parameters[0]); |
paul@185 | 719 | |
paul@185 | 720 | return 1; |
paul@185 | 721 | } |
paul@185 | 722 | else if (num_parameters > 1) |
paul@185 | 723 | { |
paul@187 | 724 | // Require N >= 2M, returning otherwise. |
paul@178 | 725 | |
paul@185 | 726 | if (parameters[1] < 2 * parameters[0]) |
paul@185 | 727 | return 0; |
paul@185 | 728 | |
paul@185 | 729 | // Set automatic D value calculation if only two parameters are given. |
paul@185 | 730 | |
paul@185 | 731 | _auto_N.set_field(regs, 1); |
paul@185 | 732 | _auto_D.set_field(regs, (num_parameters == 2) ? 0 : 1); |
paul@175 | 733 | |
paul@185 | 734 | _multiplier.set_field(regs, parameters[0]); |
paul@185 | 735 | _divider_N.set_field(regs, parameters[1]); |
paul@185 | 736 | |
paul@185 | 737 | // Set D explicitly if given. |
paul@185 | 738 | |
paul@185 | 739 | if (num_parameters > 2) |
paul@185 | 740 | _divider_D.set_field(regs, parameters[2]); |
paul@185 | 741 | |
paul@185 | 742 | return num_parameters; |
paul@185 | 743 | } |
paul@185 | 744 | |
paul@185 | 745 | return 0; |
paul@175 | 746 | } |
paul@175 | 747 | |
paul@175 | 748 | |
paul@175 | 749 | |
paul@175 | 750 | // Clock interface. |
paul@175 | 751 | |
paul@175 | 752 | Clock_base::~Clock_base() |
paul@175 | 753 | { |
paul@175 | 754 | } |
paul@175 | 755 | |
paul@175 | 756 | |
paul@175 | 757 | |
paul@175 | 758 | // Null clock. |
paul@173 | 759 | |
paul@173 | 760 | int |
paul@175 | 761 | Clock_null::have_clock(Cpm_regs ®s) |
paul@175 | 762 | { |
paul@175 | 763 | (void) regs; |
paul@175 | 764 | return false; |
paul@175 | 765 | } |
paul@175 | 766 | |
paul@175 | 767 | void |
paul@175 | 768 | Clock_null::start_clock(Cpm_regs ®s) |
paul@175 | 769 | { |
paul@175 | 770 | (void) regs; |
paul@175 | 771 | } |
paul@175 | 772 | |
paul@175 | 773 | void |
paul@175 | 774 | Clock_null::stop_clock(Cpm_regs ®s) |
paul@175 | 775 | { |
paul@175 | 776 | (void) regs; |
paul@175 | 777 | } |
paul@175 | 778 | |
paul@175 | 779 | // Output clock frequencies. |
paul@175 | 780 | |
paul@213 | 781 | uint64_t |
paul@175 | 782 | Clock_null::get_frequency(Cpm_regs ®s) |
paul@175 | 783 | { |
paul@175 | 784 | (void) regs; |
paul@175 | 785 | return 0; |
paul@175 | 786 | } |
paul@175 | 787 | |
paul@175 | 788 | |
paul@175 | 789 | |
paul@175 | 790 | // Passive clock. |
paul@175 | 791 | |
paul@175 | 792 | int |
paul@175 | 793 | Clock_passive::have_clock(Cpm_regs ®s) |
paul@173 | 794 | { |
paul@173 | 795 | (void) regs; |
paul@173 | 796 | return true; |
paul@173 | 797 | } |
paul@173 | 798 | |
paul@173 | 799 | void |
paul@175 | 800 | Clock_passive::start_clock(Cpm_regs ®s) |
paul@173 | 801 | { |
paul@173 | 802 | (void) regs; |
paul@173 | 803 | } |
paul@173 | 804 | |
paul@173 | 805 | void |
paul@175 | 806 | Clock_passive::stop_clock(Cpm_regs ®s) |
paul@173 | 807 | { |
paul@173 | 808 | (void) regs; |
paul@173 | 809 | } |
paul@173 | 810 | |
paul@175 | 811 | // Output clock frequencies. |
paul@173 | 812 | |
paul@213 | 813 | uint64_t |
paul@175 | 814 | Clock_passive::get_frequency(Cpm_regs ®s) |
paul@173 | 815 | { |
paul@211 | 816 | (void) regs; |
paul@211 | 817 | return _frequency; |
paul@175 | 818 | } |
paul@175 | 819 | |
paul@175 | 820 | |
paul@175 | 821 | |
paul@175 | 822 | // Clock control. |
paul@175 | 823 | |
paul@175 | 824 | int |
paul@179 | 825 | Clock_controlled::have_clock(Cpm_regs ®s) |
paul@175 | 826 | { |
paul@175 | 827 | return _get_control().have_clock(regs); |
paul@173 | 828 | } |
paul@173 | 829 | |
paul@173 | 830 | void |
paul@179 | 831 | Clock_controlled::start_clock(Cpm_regs ®s) |
paul@173 | 832 | { |
paul@175 | 833 | _get_control().start_clock(regs); |
paul@175 | 834 | } |
paul@175 | 835 | |
paul@175 | 836 | void |
paul@179 | 837 | Clock_controlled::stop_clock(Cpm_regs ®s) |
paul@175 | 838 | { |
paul@175 | 839 | _get_control().stop_clock(regs); |
paul@173 | 840 | } |
paul@173 | 841 | |
paul@179 | 842 | |
paul@179 | 843 | |
paul@179 | 844 | // Active clock interface. |
paul@179 | 845 | |
paul@179 | 846 | Clock_active::~Clock_active() |
paul@179 | 847 | { |
paul@179 | 848 | } |
paul@179 | 849 | |
paul@173 | 850 | // Clock sources. |
paul@173 | 851 | |
paul@173 | 852 | uint8_t |
paul@175 | 853 | Clock_active::get_source(Cpm_regs ®s) |
paul@173 | 854 | { |
paul@173 | 855 | return _source.get_source(regs); |
paul@173 | 856 | } |
paul@173 | 857 | |
paul@173 | 858 | void |
paul@175 | 859 | Clock_active::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 860 | { |
paul@175 | 861 | _get_control().change_enable(regs); |
paul@173 | 862 | _source.set_source(regs, source); |
paul@175 | 863 | _get_control().wait_busy(regs); |
paul@175 | 864 | _get_control().change_disable(regs); |
paul@173 | 865 | } |
paul@173 | 866 | |
paul@185 | 867 | enum Clock_identifiers |
paul@185 | 868 | Clock_active::get_source_clock(Cpm_regs ®s) |
paul@185 | 869 | { |
paul@185 | 870 | return _source.get_source_clock(regs); |
paul@185 | 871 | } |
paul@185 | 872 | |
paul@185 | 873 | void |
paul@185 | 874 | Clock_active::set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock) |
paul@185 | 875 | { |
paul@185 | 876 | _source.set_source_clock(regs, clock); |
paul@185 | 877 | } |
paul@185 | 878 | |
paul@173 | 879 | // Clock source frequencies. |
paul@173 | 880 | |
paul@213 | 881 | uint64_t |
paul@175 | 882 | Clock_active::get_source_frequency(Cpm_regs ®s) |
paul@173 | 883 | { |
paul@173 | 884 | return _source.get_frequency(regs); |
paul@173 | 885 | } |
paul@173 | 886 | |
paul@173 | 887 | // Output clock frequencies. |
paul@173 | 888 | |
paul@213 | 889 | uint64_t |
paul@175 | 890 | Clock_active::get_frequency(Cpm_regs ®s) |
paul@173 | 891 | { |
paul@174 | 892 | return get_source_frequency(regs); |
paul@173 | 893 | } |
paul@173 | 894 | |
paul@173 | 895 | |
paul@173 | 896 | |
paul@175 | 897 | // Divided clock interface. |
paul@173 | 898 | |
paul@183 | 899 | Clock_divided_base::~Clock_divided_base() |
paul@173 | 900 | { |
paul@173 | 901 | } |
paul@173 | 902 | |
paul@175 | 903 | // Output clock frequencies. |
paul@173 | 904 | |
paul@213 | 905 | uint64_t |
paul@183 | 906 | Clock_divided_base::get_frequency(Cpm_regs ®s) |
paul@173 | 907 | { |
paul@175 | 908 | return _get_divider().get_frequency(regs, get_source_frequency(regs)); |
paul@173 | 909 | } |
paul@173 | 910 | |
paul@178 | 911 | int |
paul@213 | 912 | Clock_divided_base::set_frequency(Cpm_regs ®s, uint64_t frequency) |
paul@187 | 913 | { |
paul@187 | 914 | _get_control().change_enable(regs); |
paul@187 | 915 | int result = _get_divider().set_frequency(regs, get_source_frequency(regs), frequency); |
paul@187 | 916 | _get_control().wait_busy(regs); |
paul@187 | 917 | _get_control().change_disable(regs); |
paul@187 | 918 | |
paul@187 | 919 | return result; |
paul@187 | 920 | } |
paul@187 | 921 | |
paul@187 | 922 | int |
paul@183 | 923 | Clock_divided_base::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 924 | { |
paul@178 | 925 | return _get_divider().get_parameters(regs, parameters); |
paul@178 | 926 | } |
paul@178 | 927 | |
paul@185 | 928 | int |
paul@185 | 929 | Clock_divided_base::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@178 | 930 | { |
paul@181 | 931 | _get_control().change_enable(regs); |
paul@185 | 932 | int n = _get_divider().set_parameters(regs, num_parameters, parameters); |
paul@178 | 933 | _get_control().wait_busy(regs); |
paul@181 | 934 | _get_control().change_disable(regs); |
paul@185 | 935 | |
paul@185 | 936 | return n; |
paul@178 | 937 | } |
paul@178 | 938 | |
paul@175 | 939 | |
paul@175 | 940 | |
paul@180 | 941 | // PLL functionality. |
paul@175 | 942 | |
paul@175 | 943 | Pll::~Pll() |
paul@173 | 944 | { |
paul@173 | 945 | } |
paul@173 | 946 | |
paul@213 | 947 | uint64_t |
paul@173 | 948 | Pll::get_frequency(Cpm_regs ®s) |
paul@173 | 949 | { |
paul@185 | 950 | if (!_control.pll_bypassed(regs)) |
paul@185 | 951 | return _divider.get_frequency(regs, get_source_frequency(regs)); |
paul@173 | 952 | else |
paul@185 | 953 | return get_source_frequency(regs); |
paul@173 | 954 | } |
paul@187 | 955 | |
paul@187 | 956 | int |
paul@213 | 957 | Pll::set_frequency(Cpm_regs ®s, uint64_t frequency) |
paul@187 | 958 | { |
paul@187 | 959 | int result = Clock_divided_base::set_frequency(regs, frequency); |
paul@187 | 960 | _control.pll_engage(regs); |
paul@187 | 961 | |
paul@187 | 962 | return result; |
paul@187 | 963 | } |