paul@0 | 1 | /* |
paul@0 | 2 | * Clock and power management. This exposes the combined functionality |
paul@0 | 3 | * provided by the jz4730. The power management functionality could be exposed |
paul@0 | 4 | * using a separate driver. |
paul@0 | 5 | * |
paul@150 | 6 | * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 7 | * |
paul@0 | 8 | * This program is free software; you can redistribute it and/or |
paul@0 | 9 | * modify it under the terms of the GNU General Public License as |
paul@0 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 11 | * the License, or (at your option) any later version. |
paul@0 | 12 | * |
paul@0 | 13 | * This program is distributed in the hope that it will be useful, |
paul@0 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 16 | * GNU General Public License for more details. |
paul@0 | 17 | * |
paul@0 | 18 | * You should have received a copy of the GNU General Public License |
paul@0 | 19 | * along with this program; if not, write to the Free Software |
paul@0 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 21 | * Boston, MA 02110-1301, USA |
paul@0 | 22 | */ |
paul@0 | 23 | |
paul@0 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@0 | 25 | #include "cpm-jz4730.h" |
paul@0 | 26 | |
paul@0 | 27 | |
paul@0 | 28 | |
paul@0 | 29 | enum Regs : unsigned |
paul@0 | 30 | { |
paul@0 | 31 | Clock_control = 0x000, // CFCR (CPCCR in JZ4740) |
paul@0 | 32 | Pll_control = 0x010, // PLCR1 (CPPCR in JZ4740) |
paul@0 | 33 | Clock_gate = 0x020, // MSCR (CLKGR in JZ4740) |
paul@0 | 34 | Sleep_control = 0x024, // SCR |
paul@0 | 35 | Lcd_divider = 0x060, // CFCR2 |
paul@0 | 36 | }; |
paul@0 | 37 | |
paul@0 | 38 | enum Clock_bits : unsigned |
paul@0 | 39 | { |
paul@0 | 40 | Clock_enable = 20, // UPE |
paul@0 | 41 | Clock_memory_divider = 16, // MFR |
paul@0 | 42 | Clock_lcd_divider = 12, // LFR |
paul@0 | 43 | Clock_pclock_divider = 8, // PFR (slow APB peripherals) |
paul@0 | 44 | Clock_hclock_divider = 4, // SFR (fast AHB peripherals) |
paul@0 | 45 | Clock_cpu_divider = 0, // IFR |
paul@0 | 46 | }; |
paul@0 | 47 | |
paul@0 | 48 | enum Pll_bits : unsigned |
paul@0 | 49 | { |
paul@0 | 50 | Pll_multiplier = 23, // PLL1FD |
paul@0 | 51 | Pll_input_division = 18, // PLL1RD |
paul@0 | 52 | Pll_output_division = 16, // PLL1OD |
paul@0 | 53 | Pll_stable = 10, // PLL1S |
paul@0 | 54 | Pll_bypassed = 9, // PLL1BP |
paul@0 | 55 | Pll_enabled = 8, // PLL1EN |
paul@0 | 56 | }; |
paul@0 | 57 | |
paul@0 | 58 | enum Clock_gate_bits : unsigned |
paul@0 | 59 | { |
paul@114 | 60 | Clock_gate_uprt = 25, |
paul@114 | 61 | Clock_gate_udc = 24, |
paul@114 | 62 | Clock_gate_cim = 23, |
paul@114 | 63 | Clock_gate_kbc = 22, |
paul@114 | 64 | Clock_gate_emac = 21, |
paul@114 | 65 | Clock_gate_uart3 = 20, |
paul@114 | 66 | Clock_gate_aic_bitclk = 18, |
paul@114 | 67 | Clock_gate_scc = 14, |
paul@114 | 68 | Clock_gate_msc = 13, |
paul@114 | 69 | Clock_gate_ssi = 12, |
paul@114 | 70 | Clock_gate_pwm1 = 11, |
paul@114 | 71 | Clock_gate_pmw0 = 10, |
paul@114 | 72 | Clock_gate_aic_pclk = 9, |
paul@114 | 73 | Clock_gate_i2c = 8, |
paul@114 | 74 | Clock_gate_lcd = 7, |
paul@114 | 75 | Clock_gate_uhc = 6, |
paul@114 | 76 | Clock_gate_dmac = 5, |
paul@114 | 77 | Clock_gate_timer = 3, |
paul@114 | 78 | Clock_gate_uart2 = 2, |
paul@114 | 79 | Clock_gate_uart1 = 1, |
paul@114 | 80 | Clock_gate_uart0 = 0, |
paul@0 | 81 | }; |
paul@0 | 82 | |
paul@0 | 83 | enum Lcd_divider_bits : unsigned |
paul@0 | 84 | { |
paul@0 | 85 | Lcd_divider_value = 0, // PIXFR (in CFCR2) |
paul@0 | 86 | }; |
paul@0 | 87 | |
paul@0 | 88 | |
paul@0 | 89 | |
paul@0 | 90 | // If implemented as a Hw::Device, various properties would be |
paul@0 | 91 | // initialised in the constructor and obtained from the device tree |
paul@0 | 92 | // definitions. |
paul@0 | 93 | |
paul@0 | 94 | Cpm_jz4730_chip::Cpm_jz4730_chip(l4_addr_t addr, uint32_t exclk_freq) |
paul@0 | 95 | : _exclk_freq(exclk_freq) |
paul@0 | 96 | { |
paul@0 | 97 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@0 | 98 | |
paul@0 | 99 | // add_cid("cpm"); |
paul@0 | 100 | // add_cid("cpm-jz4730"); |
paul@0 | 101 | // register_property("exclk_freq", &_exclk_freq); |
paul@0 | 102 | } |
paul@0 | 103 | |
paul@0 | 104 | // Clock/timer control. |
paul@0 | 105 | |
paul@128 | 106 | uint32_t |
paul@128 | 107 | Cpm_jz4730_chip::get_clock_gate_value(enum Clock_identifiers clock) |
paul@128 | 108 | { |
paul@128 | 109 | switch (clock) |
paul@128 | 110 | { |
paul@128 | 111 | case Clock_uprt: return (1 << Clock_gate_uprt); |
paul@128 | 112 | case Clock_udc: return (1 << Clock_gate_udc); |
paul@128 | 113 | case Clock_cim: return (1 << Clock_gate_cim); |
paul@128 | 114 | case Clock_kbc: return (1 << Clock_gate_kbc); |
paul@128 | 115 | case Clock_emac: return (1 << Clock_gate_emac); |
paul@128 | 116 | case Clock_uart3: return (1 << Clock_gate_uart3); |
paul@128 | 117 | case Clock_aic_bitclk: return (1 << Clock_gate_aic_bitclk); |
paul@128 | 118 | case Clock_scc: return (1 << Clock_gate_scc); |
paul@128 | 119 | case Clock_msc: return (1 << Clock_gate_msc); |
paul@128 | 120 | case Clock_ssi: return (1 << Clock_gate_ssi); |
paul@128 | 121 | case Clock_pwm1: return (1 << Clock_gate_pwm1); |
paul@128 | 122 | case Clock_pmw0: return (1 << Clock_gate_pmw0); |
paul@128 | 123 | case Clock_aic_pclk: return (1 << Clock_gate_aic_pclk); |
paul@128 | 124 | case Clock_i2c: return (1 << Clock_gate_i2c); |
paul@128 | 125 | case Clock_lcd: return (1 << Clock_gate_lcd); |
paul@128 | 126 | case Clock_uhc: return (1 << Clock_gate_uhc); |
paul@128 | 127 | case Clock_dma: return (1 << Clock_gate_dmac); |
paul@128 | 128 | case Clock_timer: return (1 << Clock_gate_timer); |
paul@128 | 129 | case Clock_uart2: return (1 << Clock_gate_uart2); |
paul@128 | 130 | case Clock_uart1: return (1 << Clock_gate_uart1); |
paul@128 | 131 | case Clock_uart0: return (1 << Clock_gate_uart0); |
paul@128 | 132 | default: return 0; |
paul@128 | 133 | } |
paul@128 | 134 | } |
paul@128 | 135 | |
paul@0 | 136 | int |
paul@128 | 137 | Cpm_jz4730_chip::have_clock(enum Clock_identifiers clock) |
paul@0 | 138 | { |
paul@128 | 139 | return !(_regs[Clock_gate] & get_clock_gate_value(clock)); |
paul@0 | 140 | } |
paul@0 | 141 | |
paul@0 | 142 | void |
paul@128 | 143 | Cpm_jz4730_chip::start_clock(enum Clock_identifiers clock) |
paul@0 | 144 | { |
paul@128 | 145 | _regs[Clock_gate] = _regs[Clock_gate] & ~get_clock_gate_value(clock); |
paul@128 | 146 | } |
paul@128 | 147 | |
paul@128 | 148 | void |
paul@128 | 149 | Cpm_jz4730_chip::stop_clock(enum Clock_identifiers clock) |
paul@128 | 150 | { |
paul@128 | 151 | _regs[Clock_gate] = _regs[Clock_gate] | get_clock_gate_value(clock); |
paul@0 | 152 | } |
paul@0 | 153 | |
paul@0 | 154 | // PLL control. |
paul@0 | 155 | |
paul@0 | 156 | // Return whether the PLL is stable. |
paul@0 | 157 | |
paul@0 | 158 | int |
paul@0 | 159 | Cpm_jz4730_chip::have_pll() |
paul@0 | 160 | { |
paul@0 | 161 | return _regs[Pll_control] & (1 << Pll_stable); |
paul@0 | 162 | } |
paul@0 | 163 | |
paul@0 | 164 | int |
paul@0 | 165 | Cpm_jz4730_chip::pll_enabled() |
paul@0 | 166 | { |
paul@0 | 167 | return _regs[Pll_control] & (1 << Pll_enabled); |
paul@0 | 168 | } |
paul@0 | 169 | |
paul@0 | 170 | int |
paul@0 | 171 | Cpm_jz4730_chip::pll_bypassed() |
paul@0 | 172 | { |
paul@0 | 173 | return _regs[Pll_control] & (1 << Pll_bypassed); |
paul@0 | 174 | } |
paul@0 | 175 | |
paul@0 | 176 | // Feedback (9-bit) multiplier. |
paul@0 | 177 | |
paul@0 | 178 | uint16_t |
paul@0 | 179 | Cpm_jz4730_chip::get_multiplier() |
paul@0 | 180 | { |
paul@0 | 181 | return ((_regs[Pll_control] & (0x1ff << Pll_multiplier)) >> Pll_multiplier) + 2; |
paul@0 | 182 | } |
paul@0 | 183 | |
paul@0 | 184 | // Input (5-bit) divider. |
paul@0 | 185 | |
paul@0 | 186 | uint8_t |
paul@0 | 187 | Cpm_jz4730_chip::get_input_division() |
paul@0 | 188 | { |
paul@0 | 189 | return ((_regs[Pll_control] & (0x1f << Pll_input_division)) >> Pll_input_division) + 2; |
paul@0 | 190 | } |
paul@0 | 191 | |
paul@0 | 192 | // Output divider. |
paul@0 | 193 | |
paul@0 | 194 | static uint8_t od[4] = {1, 2, 2, 4}; |
paul@0 | 195 | |
paul@0 | 196 | uint8_t |
paul@0 | 197 | Cpm_jz4730_chip::get_output_division() |
paul@0 | 198 | { |
paul@0 | 199 | return od[(_regs[Pll_control] & (0x03 << Pll_output_division)) >> Pll_output_division]; |
paul@0 | 200 | } |
paul@0 | 201 | |
paul@0 | 202 | // General clock divider. |
paul@0 | 203 | |
paul@0 | 204 | static uint8_t cd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@0 | 205 | |
paul@0 | 206 | uint8_t |
paul@0 | 207 | Cpm_jz4730_chip::_get_divider(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@0 | 208 | { |
paul@0 | 209 | uint8_t d = (_regs[reg] & mask) >> shift; |
paul@0 | 210 | return (d < 10) ? cd[d] : 1; |
paul@0 | 211 | } |
paul@0 | 212 | |
paul@0 | 213 | // CPU clock (CCLK) divider. |
paul@0 | 214 | |
paul@0 | 215 | uint8_t |
paul@0 | 216 | Cpm_jz4730_chip::get_cpu_divider() |
paul@0 | 217 | { |
paul@0 | 218 | return _get_divider(Clock_control, 0xf << Clock_cpu_divider, Clock_cpu_divider); |
paul@0 | 219 | } |
paul@0 | 220 | |
paul@0 | 221 | // Fast peripheral clock (HCLK) divider. |
paul@0 | 222 | |
paul@0 | 223 | uint8_t |
paul@0 | 224 | Cpm_jz4730_chip::get_hclock_divider() |
paul@0 | 225 | { |
paul@0 | 226 | return _get_divider(Clock_control, 0xf << Clock_hclock_divider, Clock_hclock_divider); |
paul@0 | 227 | } |
paul@0 | 228 | |
paul@0 | 229 | // Slow peripheral clock (PCLK) divider. |
paul@0 | 230 | |
paul@0 | 231 | uint8_t |
paul@0 | 232 | Cpm_jz4730_chip::get_pclock_divider() |
paul@0 | 233 | { |
paul@0 | 234 | return _get_divider(Clock_control, 0xf << Clock_pclock_divider, Clock_pclock_divider); |
paul@0 | 235 | } |
paul@0 | 236 | |
paul@0 | 237 | // Memory clock (MCLK) divider. |
paul@0 | 238 | |
paul@0 | 239 | uint8_t |
paul@0 | 240 | Cpm_jz4730_chip::get_memory_divider() |
paul@0 | 241 | { |
paul@0 | 242 | return _get_divider(Clock_control, 0xf << Clock_memory_divider, Clock_memory_divider); |
paul@0 | 243 | } |
paul@0 | 244 | |
paul@0 | 245 | // Clock source divider for MSC, I2S, LCD and USB. |
paul@0 | 246 | |
paul@0 | 247 | uint8_t |
paul@0 | 248 | Cpm_jz4730_chip::get_source_divider() |
paul@0 | 249 | { |
paul@0 | 250 | return 1; |
paul@0 | 251 | } |
paul@0 | 252 | |
paul@0 | 253 | // LCD device clock divider. |
paul@0 | 254 | |
paul@0 | 255 | void |
paul@0 | 256 | Cpm_jz4730_chip::set_lcd_device_divider(uint8_t division) |
paul@0 | 257 | { |
paul@0 | 258 | if (division == 0) |
paul@0 | 259 | division = 1; |
paul@0 | 260 | |
paul@0 | 261 | // NOTE: The vendor code (clock.c) bounds the divider at 16, but maybe this is |
paul@0 | 262 | // NOTE: confused with the width of the bitfield which actually contains an |
paul@0 | 263 | // NOTE: index for the clock divider value array (cd). |
paul@0 | 264 | |
paul@0 | 265 | else if (division > 16) |
paul@0 | 266 | division = 16; |
paul@0 | 267 | |
paul@0 | 268 | // Obtain the divider or closest higher divider. |
paul@0 | 269 | |
paul@0 | 270 | int i; |
paul@0 | 271 | |
paul@0 | 272 | for (i = 0; i < 10; i++) |
paul@0 | 273 | if (cd[i] >= division) break; |
paul@0 | 274 | |
paul@0 | 275 | _regs[Clock_control] = (_regs[Clock_control] & ~(0xf << Clock_lcd_divider)) | |
paul@0 | 276 | (cd[i] << Clock_lcd_divider); |
paul@0 | 277 | } |
paul@0 | 278 | |
paul@0 | 279 | // LCD pixel clock divider. |
paul@0 | 280 | |
paul@0 | 281 | uint16_t |
paul@0 | 282 | Cpm_jz4730_chip::get_lcd_pixel_divider() |
paul@0 | 283 | { |
paul@0 | 284 | return (_regs[Lcd_divider] >> Lcd_divider_value) + 1; |
paul@0 | 285 | } |
paul@0 | 286 | |
paul@0 | 287 | void |
paul@0 | 288 | Cpm_jz4730_chip::set_lcd_pixel_divider(uint16_t division) |
paul@0 | 289 | { |
paul@0 | 290 | if (division == 0) |
paul@0 | 291 | division = 1; |
paul@0 | 292 | else if (division > 512) |
paul@0 | 293 | division = 512; |
paul@0 | 294 | |
paul@0 | 295 | _regs[Lcd_divider] = (_regs[Lcd_divider] & ~(0x1ff << Lcd_divider_value)) | |
paul@0 | 296 | ((division - 1) << Lcd_divider_value); |
paul@0 | 297 | } |
paul@0 | 298 | |
paul@0 | 299 | |
paul@0 | 300 | |
paul@0 | 301 | uint32_t |
paul@133 | 302 | Cpm_jz4730_chip::get_frequency(enum Clock_frequency_identifiers clock) |
paul@0 | 303 | { |
paul@133 | 304 | if (clock == Clock_frequency_lcd_pixel) |
paul@133 | 305 | return get_output_frequency() / get_lcd_pixel_divider(); |
paul@0 | 306 | |
paul@133 | 307 | // NOTE: Consider a better error result. |
paul@133 | 308 | return 0; |
paul@143 | 309 | } |
paul@143 | 310 | |
paul@143 | 311 | void |
paul@133 | 312 | Cpm_jz4730_chip::set_frequency(enum Clock_frequency_identifiers clock, uint32_t frequency) |
paul@114 | 313 | { |
paul@133 | 314 | uint32_t out = get_output_frequency(); |
paul@114 | 315 | |
paul@133 | 316 | switch (clock) |
paul@133 | 317 | { |
paul@133 | 318 | // Limit the device frequency to 150MHz. |
paul@0 | 319 | |
paul@133 | 320 | case Clock_frequency_lcd: |
paul@133 | 321 | if (frequency > 150000000) |
paul@133 | 322 | frequency = 150000000; |
paul@133 | 323 | set_lcd_device_divider(out / frequency); |
paul@133 | 324 | break; |
paul@0 | 325 | |
paul@133 | 326 | case Clock_frequency_lcd_pixel: |
paul@133 | 327 | set_lcd_pixel_divider(out / frequency); |
paul@133 | 328 | break; |
paul@0 | 329 | |
paul@133 | 330 | default: |
paul@133 | 331 | break; |
paul@133 | 332 | } |
paul@0 | 333 | } |
paul@0 | 334 | |
paul@0 | 335 | |
paul@0 | 336 | |
paul@0 | 337 | uint32_t |
paul@0 | 338 | Cpm_jz4730_chip::get_pll_frequency() |
paul@0 | 339 | { |
paul@0 | 340 | // Test for PLL enable and not PLL bypass. |
paul@0 | 341 | |
paul@0 | 342 | if (pll_enabled() && !pll_bypassed()) |
paul@0 | 343 | return (_exclk_freq * get_multiplier()) / |
paul@0 | 344 | (get_input_division() * get_output_division()); |
paul@0 | 345 | else |
paul@0 | 346 | return _exclk_freq; |
paul@0 | 347 | } |
paul@0 | 348 | |
paul@0 | 349 | // Clock frequency for MSC, I2S, LCD and USB. |
paul@0 | 350 | |
paul@0 | 351 | uint32_t |
paul@0 | 352 | Cpm_jz4730_chip::get_output_frequency() |
paul@0 | 353 | { |
paul@0 | 354 | return get_pll_frequency() / get_source_divider(); |
paul@0 | 355 | } |
paul@0 | 356 | |
paul@0 | 357 | void |
paul@0 | 358 | Cpm_jz4730_chip::update_output_frequency() |
paul@0 | 359 | { |
paul@0 | 360 | _regs[Clock_control] = _regs[Clock_control] | (1 << Clock_enable); |
paul@0 | 361 | } |
paul@0 | 362 | |
paul@0 | 363 | // Clock frequency for the CPU. |
paul@0 | 364 | |
paul@0 | 365 | uint32_t Cpm_jz4730_chip::get_cpu_frequency() |
paul@0 | 366 | { |
paul@0 | 367 | if (pll_enabled()) |
paul@0 | 368 | return get_pll_frequency() / get_cpu_divider(); |
paul@0 | 369 | else |
paul@0 | 370 | return _exclk_freq; |
paul@0 | 371 | } |
paul@0 | 372 | |
paul@0 | 373 | // Clock frequency for fast peripherals. |
paul@0 | 374 | |
paul@0 | 375 | uint32_t |
paul@0 | 376 | Cpm_jz4730_chip::get_hclock_frequency() |
paul@0 | 377 | { |
paul@0 | 378 | if (pll_enabled()) |
paul@0 | 379 | return get_pll_frequency() / get_hclock_divider(); |
paul@0 | 380 | else |
paul@0 | 381 | return _exclk_freq; |
paul@0 | 382 | } |
paul@0 | 383 | |
paul@0 | 384 | // Clock frequency for slow peripherals. |
paul@0 | 385 | |
paul@0 | 386 | uint32_t |
paul@0 | 387 | Cpm_jz4730_chip::get_pclock_frequency() |
paul@0 | 388 | { |
paul@0 | 389 | if (pll_enabled()) |
paul@0 | 390 | return get_pll_frequency() / get_pclock_divider(); |
paul@0 | 391 | else |
paul@0 | 392 | return _exclk_freq; |
paul@0 | 393 | } |
paul@0 | 394 | |
paul@0 | 395 | // Clock frequency for the memory. |
paul@0 | 396 | |
paul@0 | 397 | uint32_t |
paul@0 | 398 | Cpm_jz4730_chip::get_memory_frequency() |
paul@0 | 399 | { |
paul@0 | 400 | if (pll_enabled()) |
paul@0 | 401 | return get_pll_frequency() / get_memory_divider(); |
paul@0 | 402 | else |
paul@0 | 403 | return _exclk_freq; |
paul@0 | 404 | } |
paul@0 | 405 | |
paul@0 | 406 | |
paul@0 | 407 | |
paul@0 | 408 | // C language interface functions. |
paul@0 | 409 | |
paul@0 | 410 | void |
paul@0 | 411 | *jz4730_cpm_init(l4_addr_t cpm_base) |
paul@0 | 412 | { |
paul@0 | 413 | /* Initialise the clock and power management peripheral with the |
paul@0 | 414 | register memory region and a 3.6864 MHz EXCLK frequency. */ |
paul@0 | 415 | |
paul@0 | 416 | return (void *) new Cpm_jz4730_chip(cpm_base, 3686400); |
paul@0 | 417 | } |
paul@0 | 418 | |
paul@0 | 419 | int |
paul@128 | 420 | jz4730_cpm_have_clock(void *cpm, enum Clock_identifiers clock) |
paul@0 | 421 | { |
paul@128 | 422 | return static_cast<Cpm_jz4730_chip *>(cpm)->have_clock(clock); |
paul@0 | 423 | } |
paul@0 | 424 | |
paul@0 | 425 | void |
paul@128 | 426 | jz4730_cpm_start_clock(void *cpm, enum Clock_identifiers clock) |
paul@114 | 427 | { |
paul@128 | 428 | static_cast<Cpm_jz4730_chip *>(cpm)->start_clock(clock); |
paul@114 | 429 | } |
paul@114 | 430 | |
paul@114 | 431 | void |
paul@128 | 432 | jz4730_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) |
paul@0 | 433 | { |
paul@128 | 434 | static_cast<Cpm_jz4730_chip *>(cpm)->stop_clock(clock); |
paul@0 | 435 | } |
paul@0 | 436 | |
paul@0 | 437 | uint32_t |
paul@0 | 438 | jz4730_cpm_get_cpu_frequency(void *cpm) |
paul@0 | 439 | { |
paul@0 | 440 | return static_cast<Cpm_jz4730_chip *>(cpm)->get_cpu_frequency(); |
paul@0 | 441 | } |
paul@0 | 442 | |
paul@0 | 443 | uint32_t |
paul@0 | 444 | jz4730_cpm_get_hclock_frequency(void *cpm) |
paul@0 | 445 | { |
paul@0 | 446 | return static_cast<Cpm_jz4730_chip *>(cpm)->get_hclock_frequency(); |
paul@0 | 447 | } |
paul@0 | 448 | |
paul@0 | 449 | uint32_t |
paul@0 | 450 | jz4730_cpm_get_output_frequency(void *cpm) |
paul@0 | 451 | { |
paul@0 | 452 | return static_cast<Cpm_jz4730_chip *>(cpm)->get_output_frequency(); |
paul@0 | 453 | } |
paul@0 | 454 | |
paul@0 | 455 | uint32_t |
paul@0 | 456 | jz4730_cpm_get_pclock_frequency(void *cpm) |
paul@0 | 457 | { |
paul@0 | 458 | return static_cast<Cpm_jz4730_chip *>(cpm)->get_pclock_frequency(); |
paul@0 | 459 | } |
paul@0 | 460 | |
paul@0 | 461 | uint32_t |
paul@0 | 462 | jz4730_cpm_get_memory_frequency(void *cpm) |
paul@0 | 463 | { |
paul@0 | 464 | return static_cast<Cpm_jz4730_chip *>(cpm)->get_memory_frequency(); |
paul@0 | 465 | } |
paul@0 | 466 | |
paul@0 | 467 | uint16_t |
paul@0 | 468 | jz4730_cpm_get_lcd_pixel_divider(void *cpm) |
paul@0 | 469 | { |
paul@0 | 470 | return static_cast<Cpm_jz4730_chip *>(cpm)->get_lcd_pixel_divider(); |
paul@0 | 471 | } |
paul@0 | 472 | |
paul@0 | 473 | uint32_t |
paul@133 | 474 | jz4730_cpm_get_frequency(void *cpm, enum Clock_frequency_identifiers clock) |
paul@0 | 475 | { |
paul@133 | 476 | return static_cast<Cpm_jz4730_chip *>(cpm)->get_frequency(clock); |
paul@0 | 477 | } |
paul@0 | 478 | |
paul@0 | 479 | void |
paul@133 | 480 | jz4730_cpm_set_frequency(void *cpm, enum Clock_frequency_identifiers clock, uint32_t frequency) |
paul@0 | 481 | { |
paul@133 | 482 | static_cast<Cpm_jz4730_chip *>(cpm)->set_frequency(clock, frequency); |
paul@0 | 483 | } |
paul@0 | 484 | |
paul@0 | 485 | void |
paul@0 | 486 | jz4730_cpm_update_output_frequency(void *cpm) |
paul@0 | 487 | { |
paul@0 | 488 | static_cast<Cpm_jz4730_chip *>(cpm)->update_output_frequency(); |
paul@0 | 489 | } |