paul@0 | 1 | /* |
paul@128 | 2 | * CPM (clock and power management) support for the JZ4780. |
paul@128 | 3 | * |
paul@128 | 4 | * Copyright (C) 2017, 2018, 2020, 2021 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software; you can redistribute it and/or |
paul@0 | 7 | * modify it under the terms of the GNU General Public License as |
paul@0 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 9 | * the License, or (at your option) any later version. |
paul@0 | 10 | * |
paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 14 | * GNU General Public License for more details. |
paul@0 | 15 | * |
paul@0 | 16 | * You should have received a copy of the GNU General Public License |
paul@0 | 17 | * along with this program; if not, write to the Free Software |
paul@0 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 19 | * Boston, MA 02110-1301, USA |
paul@0 | 20 | */ |
paul@0 | 21 | |
paul@0 | 22 | #pragma once |
paul@0 | 23 | |
paul@133 | 24 | #include <l4/devices/cpm.h> |
paul@0 | 25 | |
paul@0 | 26 | #include <l4/sys/types.h> |
paul@0 | 27 | #include <stdint.h> |
paul@0 | 28 | |
paul@0 | 29 | |
paul@0 | 30 | |
paul@0 | 31 | #ifdef __cplusplus |
paul@0 | 32 | |
paul@0 | 33 | #include <l4/devices/hw_register_block.h> |
paul@0 | 34 | |
paul@0 | 35 | /* A simple abstraction for accessing the CPM registers. |
paul@0 | 36 | * A proper device could inherit from Hw::Device and use an |
paul@0 | 37 | * Int_property for _exclk_freq and _rtclk_freq. */ |
paul@0 | 38 | |
paul@0 | 39 | class Cpm_jz4780_chip : public Cpm_chip |
paul@0 | 40 | { |
paul@0 | 41 | private: |
paul@0 | 42 | Hw::Register_block<32> _regs; |
paul@0 | 43 | uint32_t _exclk_freq, _rtclk_freq; |
paul@0 | 44 | |
paul@0 | 45 | // Utility methods. |
paul@0 | 46 | |
paul@0 | 47 | uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift); |
paul@0 | 48 | void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value); |
paul@0 | 49 | uint8_t _get_divider(uint32_t reg, uint32_t mask, uint8_t shift); |
paul@0 | 50 | |
paul@0 | 51 | // PLL control. |
paul@0 | 52 | |
paul@0 | 53 | int have_pll(uint32_t pll_reg); |
paul@0 | 54 | int pll_enabled(uint32_t pll_reg); |
paul@0 | 55 | int pll_bypassed(uint32_t pll_reg); |
paul@67 | 56 | void pll_disable(uint32_t pll_reg); |
paul@67 | 57 | void pll_enable(uint32_t pll_reg); |
paul@0 | 58 | |
paul@0 | 59 | // General frequency modifiers. |
paul@0 | 60 | |
paul@0 | 61 | uint16_t get_multiplier(uint32_t pll_reg); |
paul@0 | 62 | void set_multiplier(uint32_t pll_reg, uint16_t multiplier); |
paul@0 | 63 | uint8_t get_input_division(uint32_t pll_reg); |
paul@0 | 64 | void set_input_division(uint32_t pll_reg, uint8_t divider); |
paul@0 | 65 | uint8_t get_output_division(uint32_t pll_reg); |
paul@0 | 66 | void set_output_division(uint32_t pll_reg, uint8_t divider); |
paul@0 | 67 | |
paul@0 | 68 | // Clock dividers. |
paul@0 | 69 | |
paul@62 | 70 | void set_hdmi_divider(uint16_t division); |
paul@67 | 71 | void set_lcd_pixel_divider(uint8_t controller, uint16_t division); |
paul@0 | 72 | |
paul@0 | 73 | // Input frequencies. |
paul@0 | 74 | |
paul@0 | 75 | uint32_t get_pll_frequency(uint32_t pll_reg); |
paul@0 | 76 | |
paul@0 | 77 | // Clock sources. |
paul@0 | 78 | |
paul@0 | 79 | void set_hclock2_source(uint8_t source); |
paul@62 | 80 | void set_hdmi_source(uint8_t source); |
paul@67 | 81 | void set_lcd_source(uint8_t controller, uint8_t source); |
paul@0 | 82 | |
paul@128 | 83 | // Clock control. |
paul@128 | 84 | |
paul@128 | 85 | uint32_t get_clock_gate_register(enum Clock_identifiers clock); |
paul@128 | 86 | uint32_t get_clock_gate_value(enum Clock_identifiers clock); |
paul@128 | 87 | |
paul@0 | 88 | public: |
paul@0 | 89 | void set_pclock_source(uint8_t source); |
paul@0 | 90 | Cpm_jz4780_chip(l4_addr_t addr, uint32_t exclk_freq, uint32_t rtclk_freq); |
paul@0 | 91 | |
paul@128 | 92 | int have_clock(enum Clock_identifiers clock); |
paul@128 | 93 | void start_clock(enum Clock_identifiers clock); |
paul@128 | 94 | void stop_clock(enum Clock_identifiers clock); |
paul@0 | 95 | |
paul@0 | 96 | // Clock divider values. |
paul@0 | 97 | |
paul@0 | 98 | uint8_t get_cpu_divider(); |
paul@0 | 99 | uint8_t get_hclock0_divider(); |
paul@0 | 100 | uint8_t get_hclock2_divider(); |
paul@0 | 101 | uint8_t get_pclock_divider(); |
paul@62 | 102 | uint8_t get_hdmi_divider(); |
paul@67 | 103 | uint8_t get_lcd_pixel_divider(uint8_t controller = 0); |
paul@0 | 104 | uint8_t get_memory_divider(); |
paul@0 | 105 | |
paul@0 | 106 | // Input frequencies. |
paul@0 | 107 | |
paul@0 | 108 | uint8_t get_main_source(); |
paul@0 | 109 | uint32_t get_main_frequency(); |
paul@0 | 110 | |
paul@0 | 111 | // Clock sources, providing the input frequency. |
paul@0 | 112 | |
paul@0 | 113 | uint8_t get_cpu_source(); |
paul@0 | 114 | uint8_t get_hclock0_source(); |
paul@0 | 115 | uint8_t get_hclock2_source(); |
paul@62 | 116 | uint8_t get_hdmi_source(); |
paul@82 | 117 | uint8_t get_lcd_source(uint8_t controller); |
paul@82 | 118 | uint8_t get_lcd_source() { return get_lcd_source(0); } |
paul@0 | 119 | uint8_t get_memory_source(); |
paul@0 | 120 | uint8_t get_pclock_source(); |
paul@0 | 121 | |
paul@0 | 122 | uint32_t get_cpu_source_frequency(); |
paul@0 | 123 | uint32_t get_hclock0_source_frequency(); |
paul@0 | 124 | uint32_t get_hclock2_source_frequency(); |
paul@62 | 125 | uint32_t get_hdmi_source_frequency(); |
paul@82 | 126 | uint32_t get_lcd_source_frequency(uint8_t controller); |
paul@82 | 127 | uint32_t get_lcd_source_frequency() { return get_lcd_source_frequency(0); } |
paul@0 | 128 | uint32_t get_memory_source_frequency(); |
paul@0 | 129 | uint32_t get_pclock_source_frequency(); |
paul@0 | 130 | |
paul@0 | 131 | // Final, calculated frequencies. |
paul@0 | 132 | |
paul@0 | 133 | uint32_t get_cpu_frequency(); |
paul@0 | 134 | uint32_t get_hclock0_frequency(); |
paul@0 | 135 | uint32_t get_hclock2_frequency(); |
paul@0 | 136 | uint32_t get_memory_frequency(); |
paul@0 | 137 | uint32_t get_pclock_frequency(); |
paul@0 | 138 | |
paul@0 | 139 | uint32_t get_apll_frequency(); |
paul@0 | 140 | uint32_t get_epll_frequency(); |
paul@0 | 141 | uint32_t get_mpll_frequency(); |
paul@0 | 142 | uint32_t get_vpll_frequency(); |
paul@0 | 143 | |
paul@0 | 144 | void set_pll_parameters(uint32_t pll_reg, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider); |
paul@0 | 145 | |
paul@133 | 146 | uint32_t get_frequency(enum Clock_frequency_identifiers clock); |
paul@133 | 147 | void set_frequency(enum Clock_frequency_identifiers clock, uint32_t frequency); |
paul@133 | 148 | |
paul@0 | 149 | void update_output_frequency(); |
paul@0 | 150 | }; |
paul@0 | 151 | |
paul@0 | 152 | #endif /* __cplusplus */ |
paul@0 | 153 | |
paul@0 | 154 | |
paul@0 | 155 | |
paul@0 | 156 | /* C language interface. */ |
paul@0 | 157 | |
paul@0 | 158 | EXTERN_C_BEGIN |
paul@0 | 159 | |
paul@0 | 160 | void *jz4780_cpm_init(l4_addr_t cpm_base); |
paul@0 | 161 | |
paul@128 | 162 | int jz4780_cpm_have_clock(void *cpm, enum Clock_identifiers clock); |
paul@128 | 163 | void jz4780_cpm_start_clock(void *cpm, enum Clock_identifiers clock); |
paul@128 | 164 | void jz4780_cpm_stop_clock(void *cpm, enum Clock_identifiers clock); |
paul@0 | 165 | |
paul@0 | 166 | uint8_t jz4780_cpm_get_cpu_divider(void *cpm); |
paul@0 | 167 | uint8_t jz4780_cpm_get_hclock0_divider(void *cpm); |
paul@0 | 168 | uint8_t jz4780_cpm_get_hclock2_divider(void *cpm); |
paul@62 | 169 | uint8_t jz4780_cpm_get_hdmi_divider(void *cpm); |
paul@0 | 170 | uint8_t jz4780_cpm_get_lcd_pixel_divider(void *cpm); |
paul@0 | 171 | uint8_t jz4780_cpm_get_memory_divider(void *cpm); |
paul@0 | 172 | uint8_t jz4780_cpm_get_pclock_divider(void *cpm); |
paul@0 | 173 | |
paul@0 | 174 | uint8_t jz4780_cpm_get_hclock0_source(void *cpm); |
paul@0 | 175 | uint8_t jz4780_cpm_get_hclock2_source(void *cpm); |
paul@62 | 176 | uint8_t jz4780_cpm_get_hdmi_source(void *cpm); |
paul@0 | 177 | uint8_t jz4780_cpm_get_lcd_source(void *cpm); |
paul@0 | 178 | uint8_t jz4780_cpm_get_memory_source(void *cpm); |
paul@0 | 179 | uint8_t jz4780_cpm_get_pclock_source(void *cpm); |
paul@0 | 180 | |
paul@0 | 181 | uint32_t jz4780_cpm_get_hclock0_source_frequency(void *cpm); |
paul@0 | 182 | uint32_t jz4780_cpm_get_hclock2_source_frequency(void *cpm); |
paul@62 | 183 | uint32_t jz4780_cpm_get_hdmi_source_frequency(void *cpm); |
paul@0 | 184 | uint32_t jz4780_cpm_get_lcd_source_frequency(void *cpm); |
paul@0 | 185 | uint32_t jz4780_cpm_get_memory_source_frequency(void *cpm); |
paul@0 | 186 | uint32_t jz4780_cpm_get_pclock_source_frequency(void *cpm); |
paul@0 | 187 | |
paul@0 | 188 | void jz4780_cpm_set_pclock_source(void *cpm, uint8_t source); |
paul@0 | 189 | |
paul@0 | 190 | uint8_t jz4780_cpm_get_main_source(void *cpm); |
paul@0 | 191 | uint32_t jz4780_cpm_get_main_frequency(void *cpm); |
paul@0 | 192 | |
paul@0 | 193 | uint32_t jz4780_cpm_get_cpu_frequency(void *cpm); |
paul@0 | 194 | uint32_t jz4780_cpm_get_hclock0_frequency(void *cpm); |
paul@0 | 195 | uint32_t jz4780_cpm_get_hclock2_frequency(void *cpm); |
paul@0 | 196 | uint32_t jz4780_cpm_get_memory_frequency(void *cpm); |
paul@0 | 197 | uint32_t jz4780_cpm_get_pclock_frequency(void *cpm); |
paul@0 | 198 | |
paul@0 | 199 | uint32_t jz4780_cpm_get_apll_frequency(void *cpm); |
paul@0 | 200 | uint32_t jz4780_cpm_get_epll_frequency(void *cpm); |
paul@0 | 201 | uint32_t jz4780_cpm_get_mpll_frequency(void *cpm); |
paul@0 | 202 | uint32_t jz4780_cpm_get_vpll_frequency(void *cpm); |
paul@0 | 203 | |
paul@133 | 204 | uint32_t jz4780_cpm_get_frequency(void *cpm, enum Clock_frequency_identifiers clock); |
paul@133 | 205 | void jz4780_cpm_set_frequency(void *cpm, enum Clock_frequency_identifiers clock, uint32_t frequency); |
paul@133 | 206 | |
paul@0 | 207 | void jz4780_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider); |
paul@0 | 208 | |
paul@0 | 209 | EXTERN_C_END |