paul@173 | 1 | /* |
paul@173 | 2 | * Common clock functionality. |
paul@173 | 3 | * |
paul@173 | 4 | * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> |
paul@173 | 5 | * |
paul@173 | 6 | * This program is free software; you can redistribute it and/or |
paul@173 | 7 | * modify it under the terms of the GNU General Public License as |
paul@173 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@173 | 9 | * the License, or (at your option) any later version. |
paul@173 | 10 | * |
paul@173 | 11 | * This program is distributed in the hope that it will be useful, |
paul@173 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@173 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@173 | 14 | * GNU General Public License for more details. |
paul@173 | 15 | * |
paul@173 | 16 | * You should have received a copy of the GNU General Public License |
paul@173 | 17 | * along with this program; if not, write to the Free Software |
paul@173 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@173 | 19 | * Boston, MA 02110-1301, USA |
paul@173 | 20 | */ |
paul@173 | 21 | |
paul@173 | 22 | #pragma once |
paul@173 | 23 | |
paul@173 | 24 | #ifdef __cplusplus |
paul@173 | 25 | |
paul@211 | 26 | #include <l4/devices/clocks.h> |
paul@173 | 27 | #include <l4/devices/hw_register_block.h> |
paul@173 | 28 | #include <l4/sys/types.h> |
paul@173 | 29 | #include <stdint.h> |
paul@173 | 30 | |
paul@173 | 31 | /* Forward declaration. */ |
paul@173 | 32 | |
paul@173 | 33 | class Clock_base; |
paul@173 | 34 | |
paul@173 | 35 | |
paul@173 | 36 | |
paul@173 | 37 | /* Register access type. */ |
paul@173 | 38 | |
paul@173 | 39 | class Cpm_regs |
paul@173 | 40 | { |
paul@211 | 41 | protected: |
paul@173 | 42 | Hw::Register_block<32> _regs; |
paul@173 | 43 | Clock_base **_clocks; |
paul@173 | 44 | |
paul@173 | 45 | public: |
paul@211 | 46 | explicit Cpm_regs(l4_addr_t addr, Clock_base *clocks[]); |
paul@173 | 47 | |
paul@173 | 48 | // Utility methods. |
paul@173 | 49 | |
paul@173 | 50 | uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift); |
paul@173 | 51 | void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value); |
paul@173 | 52 | |
paul@173 | 53 | Clock_base *get_clock(int num); |
paul@173 | 54 | }; |
paul@173 | 55 | |
paul@173 | 56 | |
paul@173 | 57 | |
paul@173 | 58 | // Register field abstraction. |
paul@173 | 59 | |
paul@173 | 60 | class Field |
paul@173 | 61 | { |
paul@173 | 62 | uint32_t reg; |
paul@173 | 63 | uint32_t mask; |
paul@173 | 64 | uint8_t bit; |
paul@173 | 65 | bool defined; |
paul@201 | 66 | uint32_t _asserted = 0, _deasserted = 0; |
paul@173 | 67 | |
paul@173 | 68 | public: |
paul@173 | 69 | explicit Field() |
paul@173 | 70 | : defined(false) |
paul@173 | 71 | { |
paul@173 | 72 | } |
paul@173 | 73 | |
paul@201 | 74 | explicit Field(uint32_t reg, uint32_t mask, uint32_t bit, |
paul@201 | 75 | bool inverted = false) |
paul@173 | 76 | : reg(reg), mask(mask), bit(bit), defined(true) |
paul@173 | 77 | { |
paul@201 | 78 | if (inverted) |
paul@201 | 79 | _deasserted = mask; |
paul@201 | 80 | else |
paul@201 | 81 | _asserted = mask; |
paul@173 | 82 | } |
paul@173 | 83 | |
paul@173 | 84 | uint32_t get_field(Cpm_regs ®s); |
paul@173 | 85 | void set_field(Cpm_regs ®s, uint32_t value); |
paul@187 | 86 | |
paul@201 | 87 | uint32_t get_asserted() { return _asserted; } |
paul@201 | 88 | uint32_t get_deasserted() { return _deasserted; } |
paul@201 | 89 | |
paul@173 | 90 | bool is_defined() { return defined; } |
paul@187 | 91 | uint32_t get_limit() { return mask; } |
paul@173 | 92 | |
paul@173 | 93 | // Undefined field object. |
paul@173 | 94 | |
paul@173 | 95 | static Field undefined; |
paul@173 | 96 | }; |
paul@173 | 97 | |
paul@173 | 98 | |
paul@173 | 99 | |
paul@173 | 100 | // Clock sources. |
paul@173 | 101 | |
paul@173 | 102 | class Mux |
paul@173 | 103 | { |
paul@173 | 104 | int _num_inputs; |
paul@173 | 105 | enum Clock_identifiers *_inputs, _input; |
paul@173 | 106 | |
paul@173 | 107 | public: |
paul@173 | 108 | explicit Mux(int num_inputs, enum Clock_identifiers inputs[]) |
paul@173 | 109 | : _num_inputs(num_inputs), _inputs(inputs) |
paul@173 | 110 | { |
paul@173 | 111 | } |
paul@173 | 112 | |
paul@173 | 113 | explicit Mux(enum Clock_identifiers input) |
paul@173 | 114 | : _num_inputs(1), _inputs(&_input) |
paul@173 | 115 | { |
paul@173 | 116 | _input = input; |
paul@173 | 117 | } |
paul@173 | 118 | |
paul@173 | 119 | explicit Mux() |
paul@173 | 120 | : _num_inputs(0), _inputs(NULL) |
paul@173 | 121 | { |
paul@173 | 122 | } |
paul@173 | 123 | |
paul@173 | 124 | int get_number() { return _num_inputs; } |
paul@173 | 125 | enum Clock_identifiers get_input(int num); |
paul@173 | 126 | }; |
paul@173 | 127 | |
paul@174 | 128 | |
paul@174 | 129 | |
paul@175 | 130 | // Controllable clock source. |
paul@175 | 131 | |
paul@173 | 132 | class Source |
paul@173 | 133 | { |
paul@173 | 134 | Mux _inputs; |
paul@173 | 135 | Field _source; |
paul@173 | 136 | |
paul@173 | 137 | public: |
paul@173 | 138 | explicit Source(Mux inputs, Field source) |
paul@173 | 139 | : _inputs(inputs), _source(source) |
paul@173 | 140 | { |
paul@173 | 141 | } |
paul@173 | 142 | |
paul@173 | 143 | explicit Source(Mux inputs) |
paul@173 | 144 | : _inputs(inputs) |
paul@173 | 145 | { |
paul@173 | 146 | } |
paul@173 | 147 | |
paul@173 | 148 | explicit Source() |
paul@173 | 149 | { |
paul@173 | 150 | } |
paul@173 | 151 | |
paul@173 | 152 | int get_number() { return _inputs.get_number(); } |
paul@173 | 153 | enum Clock_identifiers get_input(int num) { return _inputs.get_input(num); } |
paul@173 | 154 | |
paul@173 | 155 | // Clock source. |
paul@173 | 156 | |
paul@173 | 157 | uint8_t get_source(Cpm_regs ®s); |
paul@173 | 158 | void set_source(Cpm_regs ®s, uint8_t source); |
paul@185 | 159 | enum Clock_identifiers get_source_clock(Cpm_regs ®s); |
paul@185 | 160 | void set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock); |
paul@173 | 161 | |
paul@173 | 162 | // Clock source frequency. |
paul@173 | 163 | |
paul@173 | 164 | uint32_t get_frequency(Cpm_regs ®s); |
paul@173 | 165 | }; |
paul@173 | 166 | |
paul@173 | 167 | |
paul@173 | 168 | |
paul@175 | 169 | // Common clock control. |
paul@175 | 170 | |
paul@175 | 171 | class Control_base |
paul@175 | 172 | { |
paul@175 | 173 | public: |
paul@175 | 174 | virtual ~Control_base(); |
paul@175 | 175 | |
paul@175 | 176 | virtual void change_disable(Cpm_regs ®s); |
paul@175 | 177 | virtual void change_enable(Cpm_regs ®s); |
paul@175 | 178 | |
paul@175 | 179 | virtual void wait_busy(Cpm_regs ®s) = 0; |
paul@175 | 180 | virtual int have_clock(Cpm_regs ®s) = 0; |
paul@175 | 181 | virtual void start_clock(Cpm_regs ®s) = 0; |
paul@175 | 182 | virtual void stop_clock(Cpm_regs ®s) = 0; |
paul@175 | 183 | }; |
paul@175 | 184 | |
paul@175 | 185 | |
paul@175 | 186 | |
paul@175 | 187 | // Clock control. |
paul@175 | 188 | |
paul@175 | 189 | class Control : public Control_base |
paul@175 | 190 | { |
paul@175 | 191 | Field _gate, _change_enable, _busy; |
paul@175 | 192 | |
paul@175 | 193 | public: |
paul@175 | 194 | explicit Control(Field gate, |
paul@175 | 195 | Field change_enable = Field::undefined, |
paul@175 | 196 | Field busy = Field::undefined) |
paul@175 | 197 | : _gate(gate), _change_enable(change_enable), _busy(busy) |
paul@175 | 198 | { |
paul@175 | 199 | } |
paul@175 | 200 | |
paul@175 | 201 | explicit Control() |
paul@175 | 202 | : _gate(Field::undefined), _change_enable(Field::undefined), |
paul@175 | 203 | _busy(Field::undefined) |
paul@175 | 204 | { |
paul@175 | 205 | } |
paul@175 | 206 | |
paul@175 | 207 | // Clock control. |
paul@175 | 208 | |
paul@175 | 209 | void change_disable(Cpm_regs ®s); |
paul@175 | 210 | void change_enable(Cpm_regs ®s); |
paul@175 | 211 | |
paul@175 | 212 | void wait_busy(Cpm_regs ®s); |
paul@175 | 213 | int have_clock(Cpm_regs ®s); |
paul@175 | 214 | void start_clock(Cpm_regs ®s); |
paul@175 | 215 | void stop_clock(Cpm_regs ®s); |
paul@211 | 216 | |
paul@211 | 217 | // Undefined control object. |
paul@211 | 218 | |
paul@211 | 219 | static Control undefined; |
paul@175 | 220 | }; |
paul@175 | 221 | |
paul@175 | 222 | |
paul@175 | 223 | |
paul@175 | 224 | // PLL control. |
paul@175 | 225 | |
paul@175 | 226 | class Control_pll : public Control_base |
paul@175 | 227 | { |
paul@175 | 228 | Field _enable, _stable, _bypass; |
paul@175 | 229 | |
paul@175 | 230 | // PLL_specific control. |
paul@175 | 231 | |
paul@175 | 232 | int have_pll(Cpm_regs ®s); |
paul@175 | 233 | int pll_enabled(Cpm_regs ®s); |
paul@175 | 234 | |
paul@175 | 235 | public: |
paul@175 | 236 | explicit Control_pll(Field enable, Field stable, Field bypass) |
paul@175 | 237 | : _enable(enable), _stable(stable), _bypass(bypass) |
paul@175 | 238 | { |
paul@175 | 239 | } |
paul@175 | 240 | |
paul@175 | 241 | // Clock control. |
paul@175 | 242 | |
paul@175 | 243 | int pll_bypassed(Cpm_regs ®s); |
paul@175 | 244 | |
paul@187 | 245 | void pll_bypass(Cpm_regs ®s); |
paul@187 | 246 | void pll_engage(Cpm_regs ®s); |
paul@187 | 247 | |
paul@175 | 248 | void wait_busy(Cpm_regs ®s); |
paul@175 | 249 | int have_clock(Cpm_regs ®s); |
paul@175 | 250 | void start_clock(Cpm_regs ®s); |
paul@175 | 251 | void stop_clock(Cpm_regs ®s); |
paul@175 | 252 | }; |
paul@175 | 253 | |
paul@175 | 254 | |
paul@175 | 255 | |
paul@174 | 256 | // Frequency transformation. |
paul@174 | 257 | |
paul@175 | 258 | class Divider_base |
paul@174 | 259 | { |
paul@174 | 260 | public: |
paul@175 | 261 | virtual ~Divider_base(); |
paul@174 | 262 | |
paul@174 | 263 | // Output frequency. |
paul@174 | 264 | |
paul@174 | 265 | virtual uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency) = 0; |
paul@187 | 266 | virtual int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) = 0; |
paul@178 | 267 | |
paul@178 | 268 | // Other operations. |
paul@178 | 269 | |
paul@178 | 270 | virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]) = 0; |
paul@178 | 271 | |
paul@185 | 272 | virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) = 0; |
paul@174 | 273 | }; |
paul@174 | 274 | |
paul@174 | 275 | |
paul@174 | 276 | |
paul@175 | 277 | // Simple divider for regular clocks. |
paul@175 | 278 | |
paul@175 | 279 | class Divider : public Divider_base |
paul@174 | 280 | { |
paul@174 | 281 | Field _divider; |
paul@174 | 282 | |
paul@174 | 283 | public: |
paul@174 | 284 | explicit Divider(Field divider) |
paul@174 | 285 | : _divider(divider) |
paul@174 | 286 | { |
paul@174 | 287 | } |
paul@174 | 288 | |
paul@174 | 289 | explicit Divider() |
paul@174 | 290 | : _divider(Field::undefined) |
paul@174 | 291 | { |
paul@174 | 292 | } |
paul@174 | 293 | |
paul@174 | 294 | // Clock divider. |
paul@174 | 295 | |
paul@174 | 296 | uint32_t get_divider(Cpm_regs ®s); |
paul@175 | 297 | void set_divider(Cpm_regs ®s, uint32_t divider); |
paul@174 | 298 | |
paul@174 | 299 | // Output frequency. |
paul@174 | 300 | |
paul@174 | 301 | uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); |
paul@187 | 302 | int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); |
paul@174 | 303 | |
paul@178 | 304 | // Other operations. |
paul@178 | 305 | |
paul@178 | 306 | int get_parameters(Cpm_regs ®s, uint32_t parameters[]); |
paul@185 | 307 | int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); |
paul@174 | 308 | }; |
paul@174 | 309 | |
paul@174 | 310 | |
paul@174 | 311 | |
paul@175 | 312 | // Divider for PLLs. |
paul@175 | 313 | |
paul@175 | 314 | class Divider_pll : public Divider_base |
paul@174 | 315 | { |
paul@175 | 316 | Field _multiplier, _input_divider, _output_divider0, _output_divider1; |
paul@211 | 317 | double _intermediate_min, _intermediate_max; |
paul@174 | 318 | |
paul@174 | 319 | // General frequency modifiers. |
paul@174 | 320 | |
paul@175 | 321 | uint32_t get_multiplier(Cpm_regs ®s); |
paul@175 | 322 | void set_multiplier(Cpm_regs ®s, uint32_t multiplier); |
paul@175 | 323 | uint32_t get_input_divider(Cpm_regs ®s); |
paul@175 | 324 | void set_input_divider(Cpm_regs ®s, uint32_t divider); |
paul@175 | 325 | uint32_t get_output_divider(Cpm_regs ®s); |
paul@175 | 326 | void set_output_divider(Cpm_regs ®s, uint32_t divider); |
paul@174 | 327 | |
paul@182 | 328 | public: |
paul@211 | 329 | |
paul@211 | 330 | // Double output divider constructor. |
paul@211 | 331 | |
paul@182 | 332 | explicit Divider_pll(Field multiplier, Field input_divider, |
paul@211 | 333 | Field output_divider0, Field output_divider1, |
paul@211 | 334 | double intermediate_min, double intermediate_max) |
paul@182 | 335 | : _multiplier(multiplier), _input_divider(input_divider), |
paul@211 | 336 | _output_divider0(output_divider0), _output_divider1(output_divider1), |
paul@211 | 337 | _intermediate_min(intermediate_min), _intermediate_max(intermediate_max) |
paul@211 | 338 | { |
paul@211 | 339 | } |
paul@211 | 340 | |
paul@211 | 341 | // Single output divider constructor. |
paul@211 | 342 | |
paul@211 | 343 | explicit Divider_pll(Field multiplier, Field input_divider, |
paul@211 | 344 | Field output_divider, |
paul@211 | 345 | double intermediate_min, double intermediate_max) |
paul@211 | 346 | : _multiplier(multiplier), _input_divider(input_divider), |
paul@211 | 347 | _output_divider0(output_divider), _output_divider1(Field::undefined), |
paul@211 | 348 | _intermediate_min(intermediate_min), _intermediate_max(intermediate_max) |
paul@182 | 349 | { |
paul@182 | 350 | } |
paul@182 | 351 | |
paul@174 | 352 | // Output frequency. |
paul@174 | 353 | |
paul@174 | 354 | uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); |
paul@187 | 355 | int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); |
paul@174 | 356 | |
paul@174 | 357 | // Other operations. |
paul@174 | 358 | |
paul@178 | 359 | int get_parameters(Cpm_regs ®s, uint32_t parameters[]); |
paul@185 | 360 | int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); |
paul@175 | 361 | }; |
paul@175 | 362 | |
paul@175 | 363 | |
paul@175 | 364 | |
paul@175 | 365 | // Divider for I2S clocks. |
paul@175 | 366 | |
paul@175 | 367 | class Divider_i2s : public Divider_base |
paul@175 | 368 | { |
paul@185 | 369 | Field _multiplier, _divider_N, _divider_D, _auto_N, _auto_D; |
paul@175 | 370 | |
paul@182 | 371 | // General frequency modifiers. |
paul@182 | 372 | |
paul@182 | 373 | uint32_t get_multiplier(Cpm_regs ®s); |
paul@182 | 374 | uint32_t get_divider_N(Cpm_regs ®s); |
paul@182 | 375 | uint32_t get_divider_D(Cpm_regs ®s); |
paul@182 | 376 | |
paul@175 | 377 | public: |
paul@185 | 378 | explicit Divider_i2s(Field multiplier, Field divider_N, Field divider_D, |
paul@185 | 379 | Field auto_N, Field auto_D) |
paul@185 | 380 | : _multiplier(multiplier), _divider_N(divider_N), _divider_D(divider_D), |
paul@185 | 381 | _auto_N(auto_N), _auto_D(auto_D) |
paul@175 | 382 | { |
paul@175 | 383 | } |
paul@175 | 384 | |
paul@175 | 385 | // Output frequency. |
paul@175 | 386 | |
paul@175 | 387 | uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); |
paul@187 | 388 | int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); |
paul@175 | 389 | |
paul@175 | 390 | // Other operations. |
paul@175 | 391 | |
paul@178 | 392 | int get_parameters(Cpm_regs ®s, uint32_t parameters[]); |
paul@178 | 393 | |
paul@185 | 394 | int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); |
paul@174 | 395 | }; |
paul@174 | 396 | |
paul@174 | 397 | |
paul@174 | 398 | |
paul@173 | 399 | // Common clock abstraction. |
paul@173 | 400 | |
paul@173 | 401 | class Clock_base |
paul@173 | 402 | { |
paul@173 | 403 | public: |
paul@175 | 404 | virtual ~Clock_base(); |
paul@175 | 405 | |
paul@176 | 406 | virtual const char *clock_type() { return "unset"; } |
paul@176 | 407 | |
paul@175 | 408 | // Clock control. |
paul@175 | 409 | |
paul@175 | 410 | virtual int have_clock(Cpm_regs ®s) = 0; |
paul@175 | 411 | virtual void start_clock(Cpm_regs ®s) = 0; |
paul@175 | 412 | virtual void stop_clock(Cpm_regs ®s) = 0; |
paul@175 | 413 | |
paul@175 | 414 | // Output frequency. |
paul@175 | 415 | |
paul@175 | 416 | virtual uint32_t get_frequency(Cpm_regs ®s) = 0; |
paul@175 | 417 | }; |
paul@175 | 418 | |
paul@175 | 419 | |
paul@175 | 420 | |
paul@175 | 421 | // Null (absent or undefined) clock abstraction. |
paul@175 | 422 | |
paul@175 | 423 | class Clock_null : public Clock_base |
paul@175 | 424 | { |
paul@175 | 425 | public: |
paul@176 | 426 | const char *clock_type() { return "null"; } |
paul@175 | 427 | |
paul@175 | 428 | // Clock control. |
paul@175 | 429 | |
paul@175 | 430 | int have_clock(Cpm_regs ®s); |
paul@175 | 431 | void start_clock(Cpm_regs ®s); |
paul@175 | 432 | void stop_clock(Cpm_regs ®s); |
paul@175 | 433 | |
paul@175 | 434 | // Output frequency. |
paul@175 | 435 | |
paul@175 | 436 | uint32_t get_frequency(Cpm_regs ®s); |
paul@175 | 437 | }; |
paul@175 | 438 | |
paul@175 | 439 | |
paul@175 | 440 | |
paul@175 | 441 | // Passive (root or input) clock without any source of its own. |
paul@175 | 442 | |
paul@175 | 443 | class Clock_passive : public Clock_base |
paul@175 | 444 | { |
paul@211 | 445 | protected: |
paul@211 | 446 | uint32_t _frequency; |
paul@211 | 447 | |
paul@175 | 448 | public: |
paul@211 | 449 | explicit Clock_passive(uint32_t frequency) |
paul@211 | 450 | : _frequency(frequency) |
paul@211 | 451 | { |
paul@211 | 452 | } |
paul@211 | 453 | |
paul@176 | 454 | const char *clock_type() { return "passive"; } |
paul@173 | 455 | |
paul@173 | 456 | // Clock control. |
paul@173 | 457 | |
paul@173 | 458 | virtual int have_clock(Cpm_regs ®s); |
paul@173 | 459 | virtual void start_clock(Cpm_regs ®s); |
paul@173 | 460 | virtual void stop_clock(Cpm_regs ®s); |
paul@173 | 461 | |
paul@175 | 462 | // Output frequency. |
paul@175 | 463 | |
paul@175 | 464 | uint32_t get_frequency(Cpm_regs ®s); |
paul@175 | 465 | }; |
paul@175 | 466 | |
paul@175 | 467 | |
paul@175 | 468 | |
paul@179 | 469 | class Clock_controlled : public Clock_base |
paul@179 | 470 | { |
paul@179 | 471 | protected: |
paul@179 | 472 | virtual Control_base &_get_control() = 0; |
paul@179 | 473 | |
paul@179 | 474 | public: |
paul@179 | 475 | |
paul@179 | 476 | // Clock control. |
paul@179 | 477 | |
paul@179 | 478 | virtual int have_clock(Cpm_regs ®s); |
paul@179 | 479 | virtual void start_clock(Cpm_regs ®s); |
paul@179 | 480 | virtual void stop_clock(Cpm_regs ®s); |
paul@179 | 481 | }; |
paul@179 | 482 | |
paul@179 | 483 | |
paul@179 | 484 | |
paul@175 | 485 | // An actively managed clock with source. |
paul@175 | 486 | |
paul@179 | 487 | class Clock_active : public Clock_controlled |
paul@175 | 488 | { |
paul@175 | 489 | protected: |
paul@175 | 490 | Source _source; |
paul@175 | 491 | |
paul@175 | 492 | public: |
paul@175 | 493 | explicit Clock_active(Source source) |
paul@175 | 494 | : _source(source) |
paul@175 | 495 | { |
paul@175 | 496 | } |
paul@175 | 497 | |
paul@175 | 498 | virtual ~Clock_active(); |
paul@175 | 499 | |
paul@173 | 500 | // Clock source. |
paul@173 | 501 | |
paul@173 | 502 | virtual uint8_t get_source(Cpm_regs ®s); |
paul@173 | 503 | virtual void set_source(Cpm_regs ®s, uint8_t source); |
paul@185 | 504 | enum Clock_identifiers get_source_clock(Cpm_regs ®s); |
paul@185 | 505 | void set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock); |
paul@173 | 506 | |
paul@173 | 507 | // Clock source frequency. |
paul@173 | 508 | |
paul@173 | 509 | virtual uint32_t get_source_frequency(Cpm_regs ®s); |
paul@173 | 510 | |
paul@173 | 511 | // Output frequency. |
paul@173 | 512 | |
paul@173 | 513 | virtual uint32_t get_frequency(Cpm_regs ®s); |
paul@173 | 514 | }; |
paul@173 | 515 | |
paul@173 | 516 | |
paul@173 | 517 | |
paul@175 | 518 | // Divided clock interface. |
paul@173 | 519 | |
paul@183 | 520 | class Clock_divided_base : public Clock_active |
paul@173 | 521 | { |
paul@175 | 522 | protected: |
paul@175 | 523 | virtual Divider_base &_get_divider() = 0; |
paul@173 | 524 | |
paul@173 | 525 | public: |
paul@183 | 526 | explicit Clock_divided_base(Source source) |
paul@175 | 527 | : Clock_active(source) |
paul@173 | 528 | { |
paul@173 | 529 | } |
paul@173 | 530 | |
paul@183 | 531 | virtual ~Clock_divided_base(); |
paul@174 | 532 | |
paul@178 | 533 | virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]); |
paul@185 | 534 | virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); |
paul@178 | 535 | |
paul@174 | 536 | // Output frequency. |
paul@174 | 537 | |
paul@174 | 538 | uint32_t get_frequency(Cpm_regs ®s); |
paul@187 | 539 | virtual int set_frequency(Cpm_regs ®s, uint32_t frequency); |
paul@173 | 540 | }; |
paul@173 | 541 | |
paul@175 | 542 | |
paul@175 | 543 | |
paul@175 | 544 | // PLL description. |
paul@175 | 545 | |
paul@183 | 546 | class Pll : public Clock_divided_base |
paul@175 | 547 | { |
paul@175 | 548 | Control_pll _control; |
paul@175 | 549 | Divider_pll _divider; |
paul@175 | 550 | |
paul@175 | 551 | virtual Control_base &_get_control() { return _control; } |
paul@175 | 552 | virtual Divider_base &_get_divider() { return _divider; } |
paul@175 | 553 | |
paul@175 | 554 | public: |
paul@175 | 555 | explicit Pll(Source source, Control_pll control, Divider_pll divider) |
paul@183 | 556 | : Clock_divided_base(source), _control(control), _divider(divider) |
paul@175 | 557 | { |
paul@175 | 558 | } |
paul@175 | 559 | |
paul@175 | 560 | virtual ~Pll(); |
paul@175 | 561 | |
paul@176 | 562 | const char *clock_type() { return "pll"; } |
paul@176 | 563 | |
paul@175 | 564 | // Output frequency. |
paul@175 | 565 | |
paul@175 | 566 | uint32_t get_frequency(Cpm_regs ®s); |
paul@187 | 567 | int set_frequency(Cpm_regs ®s, uint32_t frequency); |
paul@175 | 568 | }; |
paul@175 | 569 | |
paul@175 | 570 | |
paul@175 | 571 | |
paul@183 | 572 | // Plain clock description. |
paul@183 | 573 | |
paul@183 | 574 | class Clock : public Clock_active |
paul@183 | 575 | { |
paul@183 | 576 | Control _control; |
paul@183 | 577 | |
paul@183 | 578 | virtual Control_base &_get_control() { return _control; } |
paul@183 | 579 | |
paul@183 | 580 | public: |
paul@183 | 581 | explicit Clock(Source source, Control control) |
paul@183 | 582 | : Clock_active(source), _control(control) |
paul@183 | 583 | { |
paul@183 | 584 | } |
paul@175 | 585 | |
paul@183 | 586 | explicit Clock(Source source) |
paul@183 | 587 | : Clock_active(source) |
paul@183 | 588 | { |
paul@183 | 589 | } |
paul@183 | 590 | |
paul@183 | 591 | const char *clock_type() { return "clock"; } |
paul@183 | 592 | }; |
paul@183 | 593 | |
paul@183 | 594 | |
paul@183 | 595 | |
paul@183 | 596 | // Divided clock description. |
paul@183 | 597 | |
paul@183 | 598 | class Clock_divided : public Clock_divided_base |
paul@175 | 599 | { |
paul@175 | 600 | Control _control; |
paul@175 | 601 | Divider _divider; |
paul@175 | 602 | |
paul@175 | 603 | virtual Control_base &_get_control() { return _control; } |
paul@175 | 604 | virtual Divider_base &_get_divider() { return _divider; } |
paul@175 | 605 | |
paul@175 | 606 | public: |
paul@183 | 607 | explicit Clock_divided(Source source, Control control, Divider divider) |
paul@183 | 608 | : Clock_divided_base(source), _control(control), _divider(divider) |
paul@175 | 609 | { |
paul@175 | 610 | } |
paul@175 | 611 | |
paul@211 | 612 | explicit Clock_divided(Source source, Divider divider) |
paul@211 | 613 | : Clock_divided_base(source), _control(Control::undefined), _divider(divider) |
paul@211 | 614 | { |
paul@211 | 615 | } |
paul@211 | 616 | |
paul@176 | 617 | const char *clock_type() { return "divided"; } |
paul@175 | 618 | }; |
paul@175 | 619 | |
paul@175 | 620 | |
paul@175 | 621 | |
paul@175 | 622 | // I2S clock description. |
paul@175 | 623 | |
paul@183 | 624 | class Clock_divided_i2s : public Clock_divided_base |
paul@175 | 625 | { |
paul@175 | 626 | Control _control; |
paul@175 | 627 | Divider_i2s _divider; |
paul@175 | 628 | |
paul@175 | 629 | virtual Control_base &_get_control() { return _control; } |
paul@175 | 630 | virtual Divider_base &_get_divider() { return _divider; } |
paul@175 | 631 | |
paul@175 | 632 | public: |
paul@175 | 633 | explicit Clock_divided_i2s(Source source, Control control, Divider_i2s divider) |
paul@183 | 634 | : Clock_divided_base(source), _control(control), _divider(divider) |
paul@175 | 635 | { |
paul@175 | 636 | } |
paul@176 | 637 | |
paul@176 | 638 | const char *clock_type() { return "i2s"; } |
paul@175 | 639 | }; |
paul@175 | 640 | |
paul@173 | 641 | #endif /* __cplusplus */ |