paul@173 | 1 | /* |
paul@173 | 2 | * Common clock functionality. |
paul@173 | 3 | * |
paul@173 | 4 | * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> |
paul@173 | 5 | * |
paul@173 | 6 | * This program is free software; you can redistribute it and/or |
paul@173 | 7 | * modify it under the terms of the GNU General Public License as |
paul@173 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@173 | 9 | * the License, or (at your option) any later version. |
paul@173 | 10 | * |
paul@173 | 11 | * This program is distributed in the hope that it will be useful, |
paul@173 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@173 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@173 | 14 | * GNU General Public License for more details. |
paul@173 | 15 | * |
paul@173 | 16 | * You should have received a copy of the GNU General Public License |
paul@173 | 17 | * along with this program; if not, write to the Free Software |
paul@173 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@173 | 19 | * Boston, MA 02110-1301, USA |
paul@173 | 20 | */ |
paul@173 | 21 | |
paul@173 | 22 | #pragma once |
paul@173 | 23 | |
paul@173 | 24 | #ifdef __cplusplus |
paul@173 | 25 | |
paul@173 | 26 | #include <l4/devices/hw_register_block.h> |
paul@173 | 27 | #include <l4/devices/cpm.h> |
paul@173 | 28 | #include <l4/sys/types.h> |
paul@173 | 29 | #include <stdint.h> |
paul@173 | 30 | |
paul@173 | 31 | /* Forward declaration. */ |
paul@173 | 32 | |
paul@173 | 33 | class Clock_base; |
paul@173 | 34 | |
paul@173 | 35 | |
paul@173 | 36 | |
paul@173 | 37 | /* Register access type. */ |
paul@173 | 38 | |
paul@173 | 39 | class Cpm_regs |
paul@173 | 40 | { |
paul@173 | 41 | Hw::Register_block<32> _regs; |
paul@173 | 42 | |
paul@173 | 43 | protected: |
paul@173 | 44 | Clock_base **_clocks; |
paul@173 | 45 | |
paul@173 | 46 | public: |
paul@173 | 47 | uint32_t exclk_freq; |
paul@173 | 48 | |
paul@173 | 49 | explicit Cpm_regs(l4_addr_t addr, Clock_base *clocks[], |
paul@173 | 50 | uint32_t exclk_freq); |
paul@173 | 51 | |
paul@173 | 52 | // Utility methods. |
paul@173 | 53 | |
paul@173 | 54 | uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift); |
paul@173 | 55 | void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value); |
paul@173 | 56 | |
paul@173 | 57 | Clock_base *get_clock(int num); |
paul@173 | 58 | }; |
paul@173 | 59 | |
paul@173 | 60 | |
paul@173 | 61 | |
paul@173 | 62 | // Register field abstraction. |
paul@173 | 63 | |
paul@173 | 64 | class Field |
paul@173 | 65 | { |
paul@173 | 66 | uint32_t reg; |
paul@173 | 67 | uint32_t mask; |
paul@173 | 68 | uint8_t bit; |
paul@173 | 69 | bool defined; |
paul@201 | 70 | uint32_t _asserted = 0, _deasserted = 0; |
paul@173 | 71 | |
paul@173 | 72 | public: |
paul@173 | 73 | explicit Field() |
paul@173 | 74 | : defined(false) |
paul@173 | 75 | { |
paul@173 | 76 | } |
paul@173 | 77 | |
paul@201 | 78 | explicit Field(uint32_t reg, uint32_t mask, uint32_t bit, |
paul@201 | 79 | bool inverted = false) |
paul@173 | 80 | : reg(reg), mask(mask), bit(bit), defined(true) |
paul@173 | 81 | { |
paul@201 | 82 | if (inverted) |
paul@201 | 83 | _deasserted = mask; |
paul@201 | 84 | else |
paul@201 | 85 | _asserted = mask; |
paul@173 | 86 | } |
paul@173 | 87 | |
paul@173 | 88 | uint32_t get_field(Cpm_regs ®s); |
paul@173 | 89 | void set_field(Cpm_regs ®s, uint32_t value); |
paul@187 | 90 | |
paul@201 | 91 | uint32_t get_asserted() { return _asserted; } |
paul@201 | 92 | uint32_t get_deasserted() { return _deasserted; } |
paul@201 | 93 | |
paul@173 | 94 | bool is_defined() { return defined; } |
paul@187 | 95 | uint32_t get_limit() { return mask; } |
paul@173 | 96 | |
paul@173 | 97 | // Undefined field object. |
paul@173 | 98 | |
paul@173 | 99 | static Field undefined; |
paul@173 | 100 | }; |
paul@173 | 101 | |
paul@173 | 102 | |
paul@173 | 103 | |
paul@173 | 104 | // Clock sources. |
paul@173 | 105 | |
paul@173 | 106 | class Mux |
paul@173 | 107 | { |
paul@173 | 108 | int _num_inputs; |
paul@173 | 109 | enum Clock_identifiers *_inputs, _input; |
paul@173 | 110 | |
paul@173 | 111 | public: |
paul@173 | 112 | explicit Mux(int num_inputs, enum Clock_identifiers inputs[]) |
paul@173 | 113 | : _num_inputs(num_inputs), _inputs(inputs) |
paul@173 | 114 | { |
paul@173 | 115 | } |
paul@173 | 116 | |
paul@173 | 117 | explicit Mux(enum Clock_identifiers input) |
paul@173 | 118 | : _num_inputs(1), _inputs(&_input) |
paul@173 | 119 | { |
paul@173 | 120 | _input = input; |
paul@173 | 121 | } |
paul@173 | 122 | |
paul@173 | 123 | explicit Mux() |
paul@173 | 124 | : _num_inputs(0), _inputs(NULL) |
paul@173 | 125 | { |
paul@173 | 126 | } |
paul@173 | 127 | |
paul@173 | 128 | int get_number() { return _num_inputs; } |
paul@173 | 129 | enum Clock_identifiers get_input(int num); |
paul@173 | 130 | }; |
paul@173 | 131 | |
paul@174 | 132 | |
paul@174 | 133 | |
paul@175 | 134 | // Controllable clock source. |
paul@175 | 135 | |
paul@173 | 136 | class Source |
paul@173 | 137 | { |
paul@173 | 138 | Mux _inputs; |
paul@173 | 139 | Field _source; |
paul@173 | 140 | |
paul@173 | 141 | public: |
paul@173 | 142 | explicit Source(Mux inputs, Field source) |
paul@173 | 143 | : _inputs(inputs), _source(source) |
paul@173 | 144 | { |
paul@173 | 145 | } |
paul@173 | 146 | |
paul@173 | 147 | explicit Source(Mux inputs) |
paul@173 | 148 | : _inputs(inputs) |
paul@173 | 149 | { |
paul@173 | 150 | } |
paul@173 | 151 | |
paul@173 | 152 | explicit Source() |
paul@173 | 153 | { |
paul@173 | 154 | } |
paul@173 | 155 | |
paul@173 | 156 | int get_number() { return _inputs.get_number(); } |
paul@173 | 157 | enum Clock_identifiers get_input(int num) { return _inputs.get_input(num); } |
paul@173 | 158 | |
paul@173 | 159 | // Clock source. |
paul@173 | 160 | |
paul@173 | 161 | uint8_t get_source(Cpm_regs ®s); |
paul@173 | 162 | void set_source(Cpm_regs ®s, uint8_t source); |
paul@185 | 163 | enum Clock_identifiers get_source_clock(Cpm_regs ®s); |
paul@185 | 164 | void set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock); |
paul@173 | 165 | |
paul@173 | 166 | // Clock source frequency. |
paul@173 | 167 | |
paul@173 | 168 | uint32_t get_frequency(Cpm_regs ®s); |
paul@173 | 169 | }; |
paul@173 | 170 | |
paul@173 | 171 | |
paul@173 | 172 | |
paul@175 | 173 | // Common clock control. |
paul@175 | 174 | |
paul@175 | 175 | class Control_base |
paul@175 | 176 | { |
paul@175 | 177 | public: |
paul@175 | 178 | virtual ~Control_base(); |
paul@175 | 179 | |
paul@175 | 180 | virtual void change_disable(Cpm_regs ®s); |
paul@175 | 181 | virtual void change_enable(Cpm_regs ®s); |
paul@175 | 182 | |
paul@175 | 183 | virtual void wait_busy(Cpm_regs ®s) = 0; |
paul@175 | 184 | virtual int have_clock(Cpm_regs ®s) = 0; |
paul@175 | 185 | virtual void start_clock(Cpm_regs ®s) = 0; |
paul@175 | 186 | virtual void stop_clock(Cpm_regs ®s) = 0; |
paul@175 | 187 | }; |
paul@175 | 188 | |
paul@175 | 189 | |
paul@175 | 190 | |
paul@175 | 191 | // Clock control. |
paul@175 | 192 | |
paul@175 | 193 | class Control : public Control_base |
paul@175 | 194 | { |
paul@175 | 195 | Field _gate, _change_enable, _busy; |
paul@175 | 196 | |
paul@175 | 197 | public: |
paul@175 | 198 | explicit Control(Field gate, |
paul@175 | 199 | Field change_enable = Field::undefined, |
paul@175 | 200 | Field busy = Field::undefined) |
paul@175 | 201 | : _gate(gate), _change_enable(change_enable), _busy(busy) |
paul@175 | 202 | { |
paul@175 | 203 | } |
paul@175 | 204 | |
paul@175 | 205 | explicit Control() |
paul@175 | 206 | : _gate(Field::undefined), _change_enable(Field::undefined), |
paul@175 | 207 | _busy(Field::undefined) |
paul@175 | 208 | { |
paul@175 | 209 | } |
paul@175 | 210 | |
paul@175 | 211 | // Clock control. |
paul@175 | 212 | |
paul@175 | 213 | void change_disable(Cpm_regs ®s); |
paul@175 | 214 | void change_enable(Cpm_regs ®s); |
paul@175 | 215 | |
paul@175 | 216 | void wait_busy(Cpm_regs ®s); |
paul@175 | 217 | int have_clock(Cpm_regs ®s); |
paul@175 | 218 | void start_clock(Cpm_regs ®s); |
paul@175 | 219 | void stop_clock(Cpm_regs ®s); |
paul@175 | 220 | }; |
paul@175 | 221 | |
paul@175 | 222 | |
paul@175 | 223 | |
paul@175 | 224 | // PLL control. |
paul@175 | 225 | |
paul@175 | 226 | class Control_pll : public Control_base |
paul@175 | 227 | { |
paul@175 | 228 | Field _enable, _stable, _bypass; |
paul@175 | 229 | |
paul@175 | 230 | // PLL_specific control. |
paul@175 | 231 | |
paul@175 | 232 | int have_pll(Cpm_regs ®s); |
paul@175 | 233 | int pll_enabled(Cpm_regs ®s); |
paul@175 | 234 | |
paul@175 | 235 | public: |
paul@175 | 236 | explicit Control_pll(Field enable, Field stable, Field bypass) |
paul@175 | 237 | : _enable(enable), _stable(stable), _bypass(bypass) |
paul@175 | 238 | { |
paul@175 | 239 | } |
paul@175 | 240 | |
paul@175 | 241 | // Clock control. |
paul@175 | 242 | |
paul@175 | 243 | int pll_bypassed(Cpm_regs ®s); |
paul@175 | 244 | |
paul@187 | 245 | void pll_bypass(Cpm_regs ®s); |
paul@187 | 246 | void pll_engage(Cpm_regs ®s); |
paul@187 | 247 | |
paul@175 | 248 | void wait_busy(Cpm_regs ®s); |
paul@175 | 249 | int have_clock(Cpm_regs ®s); |
paul@175 | 250 | void start_clock(Cpm_regs ®s); |
paul@175 | 251 | void stop_clock(Cpm_regs ®s); |
paul@175 | 252 | }; |
paul@175 | 253 | |
paul@175 | 254 | |
paul@175 | 255 | |
paul@174 | 256 | // Frequency transformation. |
paul@174 | 257 | |
paul@175 | 258 | class Divider_base |
paul@174 | 259 | { |
paul@174 | 260 | public: |
paul@175 | 261 | virtual ~Divider_base(); |
paul@174 | 262 | |
paul@174 | 263 | // Output frequency. |
paul@174 | 264 | |
paul@174 | 265 | virtual uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency) = 0; |
paul@187 | 266 | virtual int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) = 0; |
paul@178 | 267 | |
paul@178 | 268 | // Other operations. |
paul@178 | 269 | |
paul@178 | 270 | virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]) = 0; |
paul@178 | 271 | |
paul@185 | 272 | virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) = 0; |
paul@174 | 273 | }; |
paul@174 | 274 | |
paul@174 | 275 | |
paul@174 | 276 | |
paul@175 | 277 | // Simple divider for regular clocks. |
paul@175 | 278 | |
paul@175 | 279 | class Divider : public Divider_base |
paul@174 | 280 | { |
paul@174 | 281 | Field _divider; |
paul@174 | 282 | |
paul@174 | 283 | public: |
paul@174 | 284 | explicit Divider(Field divider) |
paul@174 | 285 | : _divider(divider) |
paul@174 | 286 | { |
paul@174 | 287 | } |
paul@174 | 288 | |
paul@174 | 289 | explicit Divider() |
paul@174 | 290 | : _divider(Field::undefined) |
paul@174 | 291 | { |
paul@174 | 292 | } |
paul@174 | 293 | |
paul@174 | 294 | // Clock divider. |
paul@174 | 295 | |
paul@174 | 296 | uint32_t get_divider(Cpm_regs ®s); |
paul@175 | 297 | void set_divider(Cpm_regs ®s, uint32_t divider); |
paul@174 | 298 | |
paul@174 | 299 | // Output frequency. |
paul@174 | 300 | |
paul@174 | 301 | uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); |
paul@187 | 302 | int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); |
paul@174 | 303 | |
paul@178 | 304 | // Other operations. |
paul@178 | 305 | |
paul@178 | 306 | int get_parameters(Cpm_regs ®s, uint32_t parameters[]); |
paul@185 | 307 | int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); |
paul@174 | 308 | }; |
paul@174 | 309 | |
paul@174 | 310 | |
paul@174 | 311 | |
paul@175 | 312 | // Divider for PLLs. |
paul@175 | 313 | |
paul@175 | 314 | class Divider_pll : public Divider_base |
paul@174 | 315 | { |
paul@175 | 316 | Field _multiplier, _input_divider, _output_divider0, _output_divider1; |
paul@174 | 317 | |
paul@174 | 318 | // General frequency modifiers. |
paul@174 | 319 | |
paul@175 | 320 | uint32_t get_multiplier(Cpm_regs ®s); |
paul@175 | 321 | void set_multiplier(Cpm_regs ®s, uint32_t multiplier); |
paul@175 | 322 | uint32_t get_input_divider(Cpm_regs ®s); |
paul@175 | 323 | void set_input_divider(Cpm_regs ®s, uint32_t divider); |
paul@175 | 324 | uint32_t get_output_divider(Cpm_regs ®s); |
paul@175 | 325 | void set_output_divider(Cpm_regs ®s, uint32_t divider); |
paul@174 | 326 | |
paul@182 | 327 | public: |
paul@182 | 328 | explicit Divider_pll(Field multiplier, Field input_divider, |
paul@182 | 329 | Field output_divider0, Field output_divider1) |
paul@182 | 330 | : _multiplier(multiplier), _input_divider(input_divider), |
paul@182 | 331 | _output_divider0(output_divider0), _output_divider1(output_divider1) |
paul@182 | 332 | { |
paul@182 | 333 | } |
paul@182 | 334 | |
paul@174 | 335 | // Output frequency. |
paul@174 | 336 | |
paul@174 | 337 | uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); |
paul@187 | 338 | int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); |
paul@174 | 339 | |
paul@174 | 340 | // Other operations. |
paul@174 | 341 | |
paul@178 | 342 | int get_parameters(Cpm_regs ®s, uint32_t parameters[]); |
paul@185 | 343 | int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); |
paul@175 | 344 | }; |
paul@175 | 345 | |
paul@175 | 346 | |
paul@175 | 347 | |
paul@175 | 348 | // Divider for I2S clocks. |
paul@175 | 349 | |
paul@175 | 350 | class Divider_i2s : public Divider_base |
paul@175 | 351 | { |
paul@185 | 352 | Field _multiplier, _divider_N, _divider_D, _auto_N, _auto_D; |
paul@175 | 353 | |
paul@182 | 354 | // General frequency modifiers. |
paul@182 | 355 | |
paul@182 | 356 | uint32_t get_multiplier(Cpm_regs ®s); |
paul@182 | 357 | uint32_t get_divider_N(Cpm_regs ®s); |
paul@182 | 358 | uint32_t get_divider_D(Cpm_regs ®s); |
paul@182 | 359 | |
paul@175 | 360 | public: |
paul@185 | 361 | explicit Divider_i2s(Field multiplier, Field divider_N, Field divider_D, |
paul@185 | 362 | Field auto_N, Field auto_D) |
paul@185 | 363 | : _multiplier(multiplier), _divider_N(divider_N), _divider_D(divider_D), |
paul@185 | 364 | _auto_N(auto_N), _auto_D(auto_D) |
paul@175 | 365 | { |
paul@175 | 366 | } |
paul@175 | 367 | |
paul@175 | 368 | // Output frequency. |
paul@175 | 369 | |
paul@175 | 370 | uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); |
paul@187 | 371 | int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); |
paul@175 | 372 | |
paul@175 | 373 | // Other operations. |
paul@175 | 374 | |
paul@178 | 375 | int get_parameters(Cpm_regs ®s, uint32_t parameters[]); |
paul@178 | 376 | |
paul@185 | 377 | int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); |
paul@174 | 378 | }; |
paul@174 | 379 | |
paul@174 | 380 | |
paul@174 | 381 | |
paul@173 | 382 | // Common clock abstraction. |
paul@173 | 383 | |
paul@173 | 384 | class Clock_base |
paul@173 | 385 | { |
paul@173 | 386 | public: |
paul@175 | 387 | virtual ~Clock_base(); |
paul@175 | 388 | |
paul@176 | 389 | virtual const char *clock_type() { return "unset"; } |
paul@176 | 390 | |
paul@175 | 391 | // Clock control. |
paul@175 | 392 | |
paul@175 | 393 | virtual int have_clock(Cpm_regs ®s) = 0; |
paul@175 | 394 | virtual void start_clock(Cpm_regs ®s) = 0; |
paul@175 | 395 | virtual void stop_clock(Cpm_regs ®s) = 0; |
paul@175 | 396 | |
paul@175 | 397 | // Output frequency. |
paul@175 | 398 | |
paul@175 | 399 | virtual uint32_t get_frequency(Cpm_regs ®s) = 0; |
paul@175 | 400 | }; |
paul@175 | 401 | |
paul@175 | 402 | |
paul@175 | 403 | |
paul@175 | 404 | // Null (absent or undefined) clock abstraction. |
paul@175 | 405 | |
paul@175 | 406 | class Clock_null : public Clock_base |
paul@175 | 407 | { |
paul@175 | 408 | public: |
paul@176 | 409 | const char *clock_type() { return "null"; } |
paul@175 | 410 | |
paul@175 | 411 | // Clock control. |
paul@175 | 412 | |
paul@175 | 413 | int have_clock(Cpm_regs ®s); |
paul@175 | 414 | void start_clock(Cpm_regs ®s); |
paul@175 | 415 | void stop_clock(Cpm_regs ®s); |
paul@175 | 416 | |
paul@175 | 417 | // Output frequency. |
paul@175 | 418 | |
paul@175 | 419 | uint32_t get_frequency(Cpm_regs ®s); |
paul@175 | 420 | }; |
paul@175 | 421 | |
paul@175 | 422 | |
paul@175 | 423 | |
paul@175 | 424 | // Passive (root or input) clock without any source of its own. |
paul@175 | 425 | |
paul@175 | 426 | class Clock_passive : public Clock_base |
paul@175 | 427 | { |
paul@175 | 428 | public: |
paul@176 | 429 | const char *clock_type() { return "passive"; } |
paul@173 | 430 | |
paul@173 | 431 | // Clock control. |
paul@173 | 432 | |
paul@173 | 433 | virtual int have_clock(Cpm_regs ®s); |
paul@173 | 434 | virtual void start_clock(Cpm_regs ®s); |
paul@173 | 435 | virtual void stop_clock(Cpm_regs ®s); |
paul@173 | 436 | |
paul@175 | 437 | // Output frequency. |
paul@175 | 438 | |
paul@175 | 439 | uint32_t get_frequency(Cpm_regs ®s); |
paul@175 | 440 | }; |
paul@175 | 441 | |
paul@175 | 442 | |
paul@175 | 443 | |
paul@179 | 444 | class Clock_controlled : public Clock_base |
paul@179 | 445 | { |
paul@179 | 446 | protected: |
paul@179 | 447 | virtual Control_base &_get_control() = 0; |
paul@179 | 448 | |
paul@179 | 449 | public: |
paul@179 | 450 | |
paul@179 | 451 | // Clock control. |
paul@179 | 452 | |
paul@179 | 453 | virtual int have_clock(Cpm_regs ®s); |
paul@179 | 454 | virtual void start_clock(Cpm_regs ®s); |
paul@179 | 455 | virtual void stop_clock(Cpm_regs ®s); |
paul@179 | 456 | }; |
paul@179 | 457 | |
paul@179 | 458 | |
paul@179 | 459 | |
paul@175 | 460 | // An actively managed clock with source. |
paul@175 | 461 | |
paul@179 | 462 | class Clock_active : public Clock_controlled |
paul@175 | 463 | { |
paul@175 | 464 | protected: |
paul@175 | 465 | Source _source; |
paul@175 | 466 | |
paul@175 | 467 | public: |
paul@175 | 468 | explicit Clock_active(Source source) |
paul@175 | 469 | : _source(source) |
paul@175 | 470 | { |
paul@175 | 471 | } |
paul@175 | 472 | |
paul@175 | 473 | virtual ~Clock_active(); |
paul@175 | 474 | |
paul@173 | 475 | // Clock source. |
paul@173 | 476 | |
paul@173 | 477 | virtual uint8_t get_source(Cpm_regs ®s); |
paul@173 | 478 | virtual void set_source(Cpm_regs ®s, uint8_t source); |
paul@185 | 479 | enum Clock_identifiers get_source_clock(Cpm_regs ®s); |
paul@185 | 480 | void set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock); |
paul@173 | 481 | |
paul@173 | 482 | // Clock source frequency. |
paul@173 | 483 | |
paul@173 | 484 | virtual uint32_t get_source_frequency(Cpm_regs ®s); |
paul@173 | 485 | |
paul@173 | 486 | // Output frequency. |
paul@173 | 487 | |
paul@173 | 488 | virtual uint32_t get_frequency(Cpm_regs ®s); |
paul@173 | 489 | }; |
paul@173 | 490 | |
paul@173 | 491 | |
paul@173 | 492 | |
paul@175 | 493 | // Divided clock interface. |
paul@173 | 494 | |
paul@183 | 495 | class Clock_divided_base : public Clock_active |
paul@173 | 496 | { |
paul@175 | 497 | protected: |
paul@175 | 498 | virtual Divider_base &_get_divider() = 0; |
paul@173 | 499 | |
paul@173 | 500 | public: |
paul@183 | 501 | explicit Clock_divided_base(Source source) |
paul@175 | 502 | : Clock_active(source) |
paul@173 | 503 | { |
paul@173 | 504 | } |
paul@173 | 505 | |
paul@183 | 506 | virtual ~Clock_divided_base(); |
paul@174 | 507 | |
paul@178 | 508 | virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]); |
paul@185 | 509 | virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); |
paul@178 | 510 | |
paul@174 | 511 | // Output frequency. |
paul@174 | 512 | |
paul@174 | 513 | uint32_t get_frequency(Cpm_regs ®s); |
paul@187 | 514 | virtual int set_frequency(Cpm_regs ®s, uint32_t frequency); |
paul@173 | 515 | }; |
paul@173 | 516 | |
paul@175 | 517 | |
paul@175 | 518 | |
paul@175 | 519 | // PLL description. |
paul@175 | 520 | |
paul@183 | 521 | class Pll : public Clock_divided_base |
paul@175 | 522 | { |
paul@175 | 523 | Control_pll _control; |
paul@175 | 524 | Divider_pll _divider; |
paul@175 | 525 | |
paul@175 | 526 | virtual Control_base &_get_control() { return _control; } |
paul@175 | 527 | virtual Divider_base &_get_divider() { return _divider; } |
paul@175 | 528 | |
paul@175 | 529 | public: |
paul@175 | 530 | explicit Pll(Source source, Control_pll control, Divider_pll divider) |
paul@183 | 531 | : Clock_divided_base(source), _control(control), _divider(divider) |
paul@175 | 532 | { |
paul@175 | 533 | } |
paul@175 | 534 | |
paul@175 | 535 | virtual ~Pll(); |
paul@175 | 536 | |
paul@176 | 537 | const char *clock_type() { return "pll"; } |
paul@176 | 538 | |
paul@175 | 539 | // Output frequency. |
paul@175 | 540 | |
paul@175 | 541 | uint32_t get_frequency(Cpm_regs ®s); |
paul@187 | 542 | int set_frequency(Cpm_regs ®s, uint32_t frequency); |
paul@175 | 543 | }; |
paul@175 | 544 | |
paul@175 | 545 | |
paul@175 | 546 | |
paul@183 | 547 | // Plain clock description. |
paul@183 | 548 | |
paul@183 | 549 | class Clock : public Clock_active |
paul@183 | 550 | { |
paul@183 | 551 | Control _control; |
paul@183 | 552 | |
paul@183 | 553 | virtual Control_base &_get_control() { return _control; } |
paul@183 | 554 | |
paul@183 | 555 | public: |
paul@183 | 556 | explicit Clock(Source source, Control control) |
paul@183 | 557 | : Clock_active(source), _control(control) |
paul@183 | 558 | { |
paul@183 | 559 | } |
paul@175 | 560 | |
paul@183 | 561 | explicit Clock(Source source) |
paul@183 | 562 | : Clock_active(source) |
paul@183 | 563 | { |
paul@183 | 564 | } |
paul@183 | 565 | |
paul@183 | 566 | const char *clock_type() { return "clock"; } |
paul@183 | 567 | }; |
paul@183 | 568 | |
paul@183 | 569 | |
paul@183 | 570 | |
paul@183 | 571 | // Divided clock description. |
paul@183 | 572 | |
paul@183 | 573 | class Clock_divided : public Clock_divided_base |
paul@175 | 574 | { |
paul@175 | 575 | Control _control; |
paul@175 | 576 | Divider _divider; |
paul@175 | 577 | |
paul@175 | 578 | virtual Control_base &_get_control() { return _control; } |
paul@175 | 579 | virtual Divider_base &_get_divider() { return _divider; } |
paul@175 | 580 | |
paul@175 | 581 | public: |
paul@183 | 582 | explicit Clock_divided(Source source, Control control, Divider divider) |
paul@183 | 583 | : Clock_divided_base(source), _control(control), _divider(divider) |
paul@175 | 584 | { |
paul@175 | 585 | } |
paul@175 | 586 | |
paul@176 | 587 | const char *clock_type() { return "divided"; } |
paul@175 | 588 | }; |
paul@175 | 589 | |
paul@175 | 590 | |
paul@175 | 591 | |
paul@175 | 592 | // I2S clock description. |
paul@175 | 593 | |
paul@183 | 594 | class Clock_divided_i2s : public Clock_divided_base |
paul@175 | 595 | { |
paul@175 | 596 | Control _control; |
paul@175 | 597 | Divider_i2s _divider; |
paul@175 | 598 | |
paul@175 | 599 | virtual Control_base &_get_control() { return _control; } |
paul@175 | 600 | virtual Divider_base &_get_divider() { return _divider; } |
paul@175 | 601 | |
paul@175 | 602 | public: |
paul@175 | 603 | explicit Clock_divided_i2s(Source source, Control control, Divider_i2s divider) |
paul@183 | 604 | : Clock_divided_base(source), _control(control), _divider(divider) |
paul@175 | 605 | { |
paul@175 | 606 | } |
paul@176 | 607 | |
paul@176 | 608 | const char *clock_type() { return "i2s"; } |
paul@175 | 609 | }; |
paul@175 | 610 | |
paul@173 | 611 | #endif /* __cplusplus */ |