paul@160 | 1 | /* |
paul@160 | 2 | * Clock and power management. This exposes the combined functionality |
paul@160 | 3 | * provided by the X1600 and related SoCs. The power management |
paul@160 | 4 | * functionality could be exposed using a separate driver. |
paul@160 | 5 | * |
paul@160 | 6 | * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@160 | 7 | * |
paul@160 | 8 | * This program is free software; you can redistribute it and/or |
paul@160 | 9 | * modify it under the terms of the GNU General Public License as |
paul@160 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@160 | 11 | * the License, or (at your option) any later version. |
paul@160 | 12 | * |
paul@160 | 13 | * This program is distributed in the hope that it will be useful, |
paul@160 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@160 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@160 | 16 | * GNU General Public License for more details. |
paul@160 | 17 | * |
paul@160 | 18 | * You should have received a copy of the GNU General Public License |
paul@160 | 19 | * along with this program; if not, write to the Free Software |
paul@160 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@160 | 21 | * Boston, MA 02110-1301, USA |
paul@160 | 22 | */ |
paul@160 | 23 | |
paul@160 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@160 | 25 | #include "cpm-x1600.h" |
paul@160 | 26 | #include <math.h> |
paul@161 | 27 | #include <stdio.h> |
paul@160 | 28 | |
paul@160 | 29 | |
paul@160 | 30 | |
paul@161 | 31 | // Register locations. |
paul@161 | 32 | |
paul@160 | 33 | enum Regs : unsigned |
paul@160 | 34 | { |
paul@160 | 35 | Clock_control = 0x000, // CPCCR |
paul@160 | 36 | Low_power_control = 0x004, // LCR |
paul@160 | 37 | Clock_gate0 = 0x020, // CLKGR0 |
paul@160 | 38 | Clock_gate1 = 0x028, // CLKGR1 |
paul@160 | 39 | Sleep_control = 0x024, // OPCR (oscillator and power control) |
paul@160 | 40 | Clock_status = 0x0d4, // CPCSR |
paul@167 | 41 | Divider_ddr = 0x02c, // DDRCDR |
paul@167 | 42 | Divider_mac = 0x054, // MACCDR |
paul@175 | 43 | Divider0_i2s0 = 0x060, // I2S0CDR |
paul@175 | 44 | Divider1_i2s0 = 0x070, // I2S0CDR1 |
paul@175 | 45 | Divider0_i2s1 = 0x07c, // I2S1CDR (from X2000 manual) |
paul@175 | 46 | Divider1_i2s1 = 0x080, // I2S1CDR1 (from X2000 manual) |
paul@167 | 47 | Divider_lcd = 0x064, // LPCDR |
paul@167 | 48 | Divider_msc0 = 0x068, // MSC0CDR |
paul@167 | 49 | Divider_msc1 = 0x0a4, // MSC1CDR |
paul@167 | 50 | Divider_sfc = 0x074, // SFCCDR |
paul@167 | 51 | Divider_ssi = 0x05c, // SSICDR |
paul@167 | 52 | Divider_cim = 0x078, // CIMCDR |
paul@167 | 53 | Divider_pwm = 0x06c, // PWMCDR |
paul@167 | 54 | Divider_can0 = 0x0a0, // CAN0CDR |
paul@167 | 55 | Divider_can1 = 0x0a8, // CAN1CDR |
paul@167 | 56 | Divider_cdbus = 0x0ac, // CDBUSCDR |
paul@167 | 57 | Divider_macphy0 = 0x0e4, // MPHY0C |
paul@160 | 58 | Cpm_interrupt = 0x0b0, // CPM_INTR |
paul@160 | 59 | Cpm_interrupt_en = 0x0b4, // CPM_INTRE |
paul@160 | 60 | Cpm_swi = 0x0bc, // CPM_SFTINT |
paul@160 | 61 | Ddr_gate = 0x0d0, // DRCG |
paul@160 | 62 | Cpm_scratch_prot = 0x038, // CPSPPR |
paul@160 | 63 | Cpm_scratch = 0x034, // CPSPR |
paul@160 | 64 | Usb_param_control0 = 0x03c, // USBPCR |
paul@160 | 65 | Usb_reset_detect = 0x040, // USBRDT |
paul@160 | 66 | Usb_vbus_jitter = 0x044, // USBVBFIL |
paul@160 | 67 | Usb_param_control1 = 0x048, // USBPCR1 |
paul@160 | 68 | Pll_control = 0x00c, // CPPCR |
paul@160 | 69 | Pll_control_A = 0x010, // CPAPCR |
paul@160 | 70 | Pll_control_M = 0x014, // CPMPCR |
paul@160 | 71 | Pll_control_E = 0x018, // CPEPCR |
paul@160 | 72 | Pll_fraction_A = 0x084, // CPAPACR |
paul@160 | 73 | Pll_fraction_M = 0x088, // CPMPACR |
paul@160 | 74 | Pll_fraction_E = 0x08c, // CPEPACR |
paul@160 | 75 | }; |
paul@160 | 76 | |
paul@161 | 77 | enum Clock_source_values : unsigned |
paul@160 | 78 | { |
paul@161 | 79 | Source_mME_main = 0, |
paul@161 | 80 | Source_mME_pll_M = 1, |
paul@161 | 81 | Source_mME_pll_E = 2, |
paul@160 | 82 | |
paul@161 | 83 | // Special value |
paul@160 | 84 | |
paul@161 | 85 | Source_mask = 0x3, |
paul@160 | 86 | }; |
paul@160 | 87 | |
paul@160 | 88 | |
paul@160 | 89 | |
paul@167 | 90 | // Register field definitions. |
paul@167 | 91 | |
paul@175 | 92 | static Field Clock_source_main (Clock_control, 3, 30), // SEL_SRC (output to SCLK_A) |
paul@175 | 93 | Clock_source_cpu (Clock_control, 3, 28), // SEL_CPLL (output to CCLK) |
paul@175 | 94 | Clock_source_hclock0 (Clock_control, 3, 26), // SEL_H0PLL (output to AHB0) |
paul@175 | 95 | Clock_source_hclock2 (Clock_control, 3, 24), // SEL_H2PLL (output to AHB2) |
paul@175 | 96 | Clock_source_can0 (Divider_can0, 3, 30), // CA0CS |
paul@175 | 97 | Clock_source_can1 (Divider_can1, 3, 30), // CA1CS |
paul@175 | 98 | Clock_source_cdbus (Divider_cdbus, 3, 30), // CDCS |
paul@175 | 99 | Clock_source_cim (Divider_cim, 3, 30), // CIMPCS |
paul@175 | 100 | Clock_source_ddr (Divider_ddr, 3, 30), // DCS |
paul@175 | 101 | Clock_source_i2s (Divider0_i2s0, 1, 31), // I2PCS |
paul@175 | 102 | Clock_source_lcd (Divider_lcd, 3, 30), // LPCS |
paul@175 | 103 | Clock_source_mac (Divider_mac, 3, 30), // MACPCS |
paul@175 | 104 | Clock_source_msc0 (Divider_msc0, 3, 30), // MPCS |
paul@175 | 105 | Clock_source_msc1 (Divider_msc1, 3, 30), // MPCS |
paul@175 | 106 | Clock_source_pwm (Divider_pwm, 3, 30), // PWMPCS |
paul@175 | 107 | Clock_source_sfc (Divider_sfc, 3, 30), // SFCS |
paul@175 | 108 | Clock_source_ssi (Divider_ssi, 3, 30), // SPCS |
paul@167 | 109 | |
paul@175 | 110 | Clock_busy_cpu (Clock_status, 1, 0), |
paul@175 | 111 | Clock_busy_ddr (Divider_ddr, 1, 28), |
paul@175 | 112 | Clock_busy_mac (Divider_mac, 1, 28), |
paul@175 | 113 | Clock_busy_lcd (Divider_lcd, 1, 28), |
paul@175 | 114 | Clock_busy_msc0 (Divider_msc0, 1, 28), |
paul@175 | 115 | Clock_busy_msc1 (Divider_msc1, 1, 28), |
paul@175 | 116 | Clock_busy_sfc (Divider_sfc, 1, 28), |
paul@175 | 117 | Clock_busy_ssi (Divider_ssi, 1, 28), |
paul@175 | 118 | Clock_busy_cim (Divider_cim, 1, 28), |
paul@175 | 119 | Clock_busy_pwm (Divider_pwm, 1, 28), |
paul@175 | 120 | Clock_busy_can0 (Divider_can0, 1, 28), |
paul@175 | 121 | Clock_busy_can1 (Divider_can1, 1, 28), |
paul@175 | 122 | Clock_busy_cdbus (Divider_cdbus, 1, 28), |
paul@167 | 123 | |
paul@175 | 124 | Clock_change_enable_cpu (Clock_control, 1, 22), |
paul@175 | 125 | Clock_change_enable_ahb0 (Clock_control, 1, 21), |
paul@175 | 126 | Clock_change_enable_ahb2 (Clock_control, 1, 20), |
paul@175 | 127 | Clock_change_enable_ddr (Divider_ddr, 1, 29), |
paul@175 | 128 | Clock_change_enable_mac (Divider_mac, 1, 29), |
paul@175 | 129 | Clock_change_enable_i2s (Divider0_i2s0, 1, 29), |
paul@175 | 130 | Clock_change_enable_lcd (Divider_lcd, 1, 29), |
paul@175 | 131 | Clock_change_enable_msc0 (Divider_msc0, 1, 29), |
paul@175 | 132 | Clock_change_enable_msc1 (Divider_msc1, 1, 29), |
paul@175 | 133 | Clock_change_enable_sfc (Divider_sfc, 1, 29), |
paul@175 | 134 | Clock_change_enable_ssi (Divider_ssi, 1, 29), |
paul@175 | 135 | Clock_change_enable_cim (Divider_cim, 1, 29), |
paul@175 | 136 | Clock_change_enable_pwm (Divider_pwm, 1, 29), |
paul@175 | 137 | Clock_change_enable_can0 (Divider_can0, 1, 29), |
paul@175 | 138 | Clock_change_enable_can1 (Divider_can1, 1, 29), |
paul@175 | 139 | Clock_change_enable_cdbus (Divider_cdbus, 1, 29), |
paul@167 | 140 | |
paul@175 | 141 | Clock_divider_can0 (Divider_can0, 0xff, 0), // CAN0CDR |
paul@175 | 142 | Clock_divider_can1 (Divider_can1, 0xff, 0), // CAN1CDR |
paul@175 | 143 | Clock_divider_cdbus (Divider_cdbus, 0xff, 0), // CDBUSCDR |
paul@175 | 144 | Clock_divider_cim (Divider_cim, 0xff, 0), // CIMCDR |
paul@175 | 145 | Clock_divider_cpu (Clock_control, 0x0f, 0), // CDIV |
paul@175 | 146 | Clock_divider_ddr (Divider_ddr, 0x0f, 0), // DDRCDR |
paul@175 | 147 | Clock_divider_hclock0 (Clock_control, 0x0f, 8), // H0DIV (fast AHB peripherals) |
paul@175 | 148 | Clock_divider_hclock2 (Clock_control, 0x0f, 12), // H2DIV (fast AHB peripherals) |
paul@175 | 149 | Clock_divider_i2s0_m (Divider0_i2s0, 0x1ff, 20), // I2SDIV_M |
paul@175 | 150 | Clock_divider_i2s0_n (Divider0_i2s0, 0xfffff, 0), // I2SDIV_N |
paul@175 | 151 | Clock_divider_i2s0_d (Divider1_i2s0, 0xfffff, 0), // I2SDIV_D |
paul@175 | 152 | Clock_divider_i2s1_m (Divider0_i2s1, 0x1ff, 20), // I2SDIV_M |
paul@175 | 153 | Clock_divider_i2s1_n (Divider0_i2s1, 0xfffff, 0), // I2SDIV_N |
paul@175 | 154 | Clock_divider_i2s1_d (Divider1_i2s1, 0xfffff, 0), // I2SDIV_D |
paul@175 | 155 | Clock_divider_l2cache (Clock_control, 0x0f, 4), // L2CDIV |
paul@175 | 156 | Clock_divider_lcd (Divider_lcd, 0xff, 0), // LPCDR |
paul@175 | 157 | Clock_divider_mac (Divider_mac, 0xff, 0), // MACCDR |
paul@175 | 158 | Clock_divider_msc0 (Divider_msc0, 0xff, 0), // MSC0CDR |
paul@175 | 159 | Clock_divider_msc1 (Divider_msc1, 0xff, 0), // MSC1CDR |
paul@175 | 160 | Clock_divider_pclock (Clock_control, 0x0f, 16), // PDIV (slow APB peripherals) |
paul@175 | 161 | Clock_divider_pwm (Divider_pwm, 0x0f, 0), // PWMCDR |
paul@175 | 162 | Clock_divider_sfc (Divider_sfc, 0xff, 0), // SFCCDR |
paul@175 | 163 | Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR |
paul@168 | 164 | |
paul@175 | 165 | Clock_gate_main (Clock_control, 1, 23), // GATE_SCLKA |
paul@175 | 166 | Clock_gate_ddr (Clock_gate0, 1, 31), // DDR |
paul@175 | 167 | Clock_gate_ahb0 (Clock_gate0, 1, 29), // AHB0 |
paul@175 | 168 | Clock_gate_apb0 (Clock_gate0, 1, 28), // APB0 |
paul@175 | 169 | Clock_gate_rtc (Clock_gate0, 1, 27), // RTC |
paul@175 | 170 | Clock_gate_aes (Clock_gate0, 1, 24), // AES |
paul@175 | 171 | Clock_gate_lcd_pixel (Clock_gate0, 1, 23), // LCD |
paul@175 | 172 | Clock_gate_cim (Clock_gate0, 1, 22), // CIM |
paul@175 | 173 | Clock_gate_dma (Clock_gate0, 1, 21), // PDMA |
paul@175 | 174 | Clock_gate_ost (Clock_gate0, 1, 20), // OST |
paul@175 | 175 | Clock_gate_ssi0 (Clock_gate0, 1, 19), // SSI0 |
paul@175 | 176 | Clock_gate_timer (Clock_gate0, 1, 18), // TCU |
paul@175 | 177 | Clock_gate_dtrng (Clock_gate0, 1, 17), // DTRNG |
paul@175 | 178 | Clock_gate_uart2 (Clock_gate0, 1, 16), // UART2 |
paul@175 | 179 | Clock_gate_uart1 (Clock_gate0, 1, 15), // UART1 |
paul@175 | 180 | Clock_gate_uart0 (Clock_gate0, 1, 14), // UART0 |
paul@175 | 181 | Clock_gate_sadc (Clock_gate0, 1, 13), // SADC |
paul@175 | 182 | Clock_gate_audio (Clock_gate0, 1, 11), // AUDIO |
paul@175 | 183 | Clock_gate_ssi_slv (Clock_gate0, 1, 10), // SSI_SLV |
paul@175 | 184 | Clock_gate_i2c1 (Clock_gate0, 1, 8), // I2C1 |
paul@175 | 185 | Clock_gate_i2c0 (Clock_gate0, 1, 7), // I2C0 |
paul@175 | 186 | Clock_gate_msc1 (Clock_gate0, 1, 5), // MSC1 |
paul@175 | 187 | Clock_gate_msc0 (Clock_gate0, 1, 4), // MSC0 |
paul@175 | 188 | Clock_gate_otg (Clock_gate0, 1, 3), // OTG |
paul@175 | 189 | Clock_gate_sfc (Clock_gate0, 1, 2), // SFC |
paul@175 | 190 | Clock_gate_efuse (Clock_gate0, 1, 1), // EFUSE |
paul@175 | 191 | Clock_gate_nemc (Clock_gate0, 1, 0), // NEMC |
paul@175 | 192 | Clock_gate_arb (Clock_gate1, 1, 30), // ARB |
paul@175 | 193 | Clock_gate_mipi_csi (Clock_gate1, 1, 28), // MIPI_CSI |
paul@175 | 194 | Clock_gate_intc (Clock_gate1, 1, 26), // INTC |
paul@175 | 195 | Clock_gate_gmac0 (Clock_gate1, 1, 23), // GMAC0 |
paul@175 | 196 | Clock_gate_uart3 (Clock_gate1, 1, 16), // UART3 |
paul@175 | 197 | Clock_gate_i2s0_tx (Clock_gate1, 1, 9), // I2S0_dev_tclk |
paul@175 | 198 | Clock_gate_i2s0_rx (Clock_gate1, 1, 8), // I2S0_dev_rclk |
paul@175 | 199 | Clock_gate_hash (Clock_gate1, 1, 6), // HASH |
paul@175 | 200 | Clock_gate_pwm (Clock_gate1, 1, 5), // PWM |
paul@175 | 201 | Clock_gate_cdbus (Clock_gate1, 1, 2), // CDBUS |
paul@175 | 202 | Clock_gate_can1 (Clock_gate1, 1, 1), // CAN1 |
paul@175 | 203 | Clock_gate_can0 (Clock_gate1, 1, 0), // CAN0 |
paul@168 | 204 | |
paul@175 | 205 | Pll_enable_A (Pll_control_A, 1, 0), // APLLEN |
paul@175 | 206 | Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN |
paul@175 | 207 | Pll_enable_M (Pll_control_M, 1, 0), // MPLLEN |
paul@168 | 208 | |
paul@175 | 209 | Pll_stable_A (Pll_control_A, 1, 3), // APLL_ON |
paul@175 | 210 | Pll_stable_E (Pll_control_E, 1, 3), // EPLL_ON |
paul@175 | 211 | Pll_stable_M (Pll_control_M, 1, 3), // MPLL_ON |
paul@175 | 212 | |
paul@175 | 213 | Pll_bypass_A (Pll_control_A, 1, 30), // APLL_BP |
paul@175 | 214 | Pll_bypass_E (Pll_control_E, 1, 26), // EPLL_BP |
paul@175 | 215 | Pll_bypass_M (Pll_control_M, 1, 28), // MPLL_BP |
paul@168 | 216 | |
paul@175 | 217 | Pll_multiplier_A (Pll_control_A, 0x1fff, 20), // APLLM |
paul@175 | 218 | Pll_multiplier_E (Pll_control_E, 0x1fff, 20), // EPLLM |
paul@175 | 219 | Pll_multiplier_M (Pll_control_M, 0x1fff, 20), // MPLLM |
paul@175 | 220 | |
paul@175 | 221 | Pll_input_division_A (Pll_control_A, 0x3f, 14), // APLLN |
paul@175 | 222 | Pll_input_division_E (Pll_control_E, 0x3f, 14), // EPLLN |
paul@175 | 223 | Pll_input_division_M (Pll_control_M, 0x3f, 14), // MPLLN |
paul@168 | 224 | |
paul@175 | 225 | Pll_output_division1_A (Pll_control_A, 0x07, 11), // APLLOD1 |
paul@175 | 226 | Pll_output_division1_E (Pll_control_E, 0x07, 11), // EPLLOD1 |
paul@175 | 227 | Pll_output_division1_M (Pll_control_M, 0x07, 11), // MPLLOD1 |
paul@175 | 228 | |
paul@175 | 229 | Pll_output_division0_A (Pll_control_A, 0x07, 8), // APLLOD0 |
paul@175 | 230 | Pll_output_division0_E (Pll_control_E, 0x07, 8), // EPLLOD0 |
paul@175 | 231 | Pll_output_division0_M (Pll_control_M, 0x07, 8); // MPLLOD0 |
paul@167 | 232 | |
paul@167 | 233 | |
paul@167 | 234 | |
paul@169 | 235 | // Multiplexer instances. |
paul@169 | 236 | |
paul@169 | 237 | #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) |
paul@169 | 238 | |
paul@171 | 239 | Mux mux_external(Clock_external); |
paul@171 | 240 | |
paul@171 | 241 | Mux mux_pclock(Clock_pclock); |
paul@171 | 242 | |
paul@171 | 243 | Mux mux_ahb2_apb(Clock_ahb2_apb); |
paul@169 | 244 | |
paul@169 | 245 | Mux mux_core(3, Clocks(Clock_none, Clock_main, Clock_pll_M)); |
paul@169 | 246 | |
paul@169 | 247 | Mux mux_bus(4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)); |
paul@169 | 248 | |
paul@169 | 249 | Mux mux_dev(3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)); |
paul@169 | 250 | |
paul@169 | 251 | Mux mux_i2s(2, Clocks(Clock_main, Clock_pll_E)); |
paul@169 | 252 | |
paul@169 | 253 | |
paul@169 | 254 | |
paul@165 | 255 | // Clock instances. |
paul@165 | 256 | |
paul@171 | 257 | Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)); |
paul@165 | 258 | |
paul@171 | 259 | Clock clock_can0(Source(mux_bus, Clock_source_can0), |
paul@175 | 260 | Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0), |
paul@174 | 261 | Divider(Clock_divider_can0)); |
paul@165 | 262 | |
paul@171 | 263 | Clock clock_can1(Source(mux_bus, Clock_source_can1), |
paul@175 | 264 | Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1), |
paul@174 | 265 | Divider(Clock_divider_can1)); |
paul@165 | 266 | |
paul@171 | 267 | Clock clock_cdbus(Source(mux_dev, Clock_source_cdbus), |
paul@175 | 268 | Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus), |
paul@174 | 269 | Divider(Clock_divider_cdbus)); |
paul@165 | 270 | |
paul@171 | 271 | Clock clock_cim(Source(mux_dev, Clock_source_cim), |
paul@175 | 272 | Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), |
paul@174 | 273 | Divider(Clock_divider_cim)); |
paul@165 | 274 | |
paul@171 | 275 | Clock clock_cpu(Source(mux_core, Clock_source_cpu), |
paul@175 | 276 | Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu), |
paul@174 | 277 | Divider(Clock_divider_cpu)); |
paul@165 | 278 | |
paul@171 | 279 | Clock clock_ddr(Source(mux_core, Clock_source_ddr), |
paul@175 | 280 | Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), |
paul@174 | 281 | Divider(Clock_divider_ddr)); |
paul@165 | 282 | |
paul@175 | 283 | Clock clock_dma(Source(mux_pclock), Control(Clock_gate_dma), Divider::undefined); |
paul@165 | 284 | |
paul@175 | 285 | Clock_passive clock_external; |
paul@165 | 286 | |
paul@171 | 287 | Clock clock_hclock0(Source(mux_core, Clock_source_hclock0), |
paul@175 | 288 | Control(Clock_gate_ahb0, Clock_change_enable_ahb0), |
paul@174 | 289 | Divider(Clock_divider_hclock0)); |
paul@165 | 290 | |
paul@171 | 291 | Clock clock_hclock2(Source(mux_ahb2_apb), |
paul@175 | 292 | Control(Clock_gate_apb0, Clock_change_enable_ahb2), |
paul@174 | 293 | Divider(Clock_divider_hclock2)); |
paul@165 | 294 | |
paul@175 | 295 | Clock clock_i2c(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined); |
paul@165 | 296 | |
paul@175 | 297 | Clock clock_i2c0(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined); |
paul@165 | 298 | |
paul@175 | 299 | Clock clock_i2c1(Source(mux_pclock), Control(Clock_gate_i2c1), Divider::undefined); |
paul@165 | 300 | |
paul@175 | 301 | Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s), |
paul@175 | 302 | Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s), |
paul@175 | 303 | Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n, |
paul@175 | 304 | Clock_divider_i2s0_d)); |
paul@165 | 305 | |
paul@175 | 306 | Clock_divided_i2s clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s), |
paul@175 | 307 | Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s), |
paul@175 | 308 | Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n, |
paul@175 | 309 | Clock_divider_i2s1_d)); |
paul@165 | 310 | |
paul@171 | 311 | Clock clock_lcd_pixel(Source(mux_dev, Clock_source_lcd), |
paul@175 | 312 | Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd), |
paul@174 | 313 | Divider(Clock_divider_lcd)); |
paul@165 | 314 | |
paul@171 | 315 | Clock clock_mac(Source(mux_dev, Clock_source_mac), |
paul@175 | 316 | Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac), |
paul@174 | 317 | Divider(Clock_divider_mac)); |
paul@165 | 318 | |
paul@171 | 319 | Clock clock_main(Source(mux_core, Clock_source_main), |
paul@175 | 320 | Control(Clock_gate_main)); |
paul@165 | 321 | |
paul@171 | 322 | Clock clock_msc(Source(mux_dev, Clock_source_msc0), |
paul@175 | 323 | Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), |
paul@174 | 324 | Divider(Clock_divider_msc0)); |
paul@165 | 325 | |
paul@171 | 326 | Clock clock_msc0(Source(mux_dev, Clock_source_msc0), |
paul@175 | 327 | Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), |
paul@174 | 328 | Divider(Clock_divider_msc0)); |
paul@165 | 329 | |
paul@171 | 330 | Clock clock_msc1(Source(mux_dev, Clock_source_msc1), |
paul@175 | 331 | Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), |
paul@174 | 332 | Divider(Clock_divider_msc1)); |
paul@165 | 333 | |
paul@175 | 334 | Clock_null clock_none; |
paul@161 | 335 | |
paul@171 | 336 | Clock clock_pclock(Source(mux_ahb2_apb), |
paul@175 | 337 | Control(Clock_gate_apb0, Field::undefined, Field::undefined), |
paul@174 | 338 | Divider(Clock_divider_pclock)); |
paul@165 | 339 | |
paul@171 | 340 | Pll clock_pll_A(Source(mux_external), |
paul@175 | 341 | Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A), |
paul@174 | 342 | Divider_pll(Pll_multiplier_A, Pll_input_division_A, |
paul@174 | 343 | Pll_output_division0_A, Pll_output_division1_A)); |
paul@165 | 344 | |
paul@171 | 345 | Pll clock_pll_E(Source(mux_external), |
paul@175 | 346 | Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E), |
paul@174 | 347 | Divider_pll(Pll_multiplier_E, Pll_input_division_E, |
paul@174 | 348 | Pll_output_division0_E, Pll_output_division1_E)); |
paul@165 | 349 | |
paul@171 | 350 | Pll clock_pll_M(Source(mux_external), |
paul@175 | 351 | Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M), |
paul@174 | 352 | Divider_pll(Pll_multiplier_M, Pll_input_division_M, |
paul@174 | 353 | Pll_output_division0_M, Pll_output_division1_M)); |
paul@165 | 354 | |
paul@171 | 355 | Clock clock_pwm(Source(mux_dev, Clock_source_pwm), |
paul@175 | 356 | Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), |
paul@174 | 357 | Divider(Clock_divider_pwm)); |
paul@165 | 358 | |
paul@171 | 359 | Clock clock_pwm0(Source(mux_dev, Clock_source_pwm), |
paul@175 | 360 | Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), |
paul@174 | 361 | Divider(Clock_divider_pwm)); |
paul@165 | 362 | |
paul@171 | 363 | Clock clock_sfc(Source(mux_dev, Clock_source_sfc), |
paul@175 | 364 | Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc), |
paul@174 | 365 | Divider(Clock_divider_sfc)); |
paul@165 | 366 | |
paul@171 | 367 | Clock clock_ssi(Source(mux_dev, Clock_source_ssi), |
paul@175 | 368 | Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi), |
paul@174 | 369 | Divider(Clock_divider_ssi)); |
paul@165 | 370 | |
paul@175 | 371 | Clock clock_timer(Source(mux_pclock), Control(Clock_gate_timer), Divider::undefined); |
paul@165 | 372 | |
paul@175 | 373 | Clock clock_uart0(Source(mux_external), Control(Clock_gate_uart0), Divider::undefined); |
paul@165 | 374 | |
paul@175 | 375 | Clock clock_uart1(Source(mux_external), Control(Clock_gate_uart1), Divider::undefined); |
paul@165 | 376 | |
paul@175 | 377 | Clock clock_uart2(Source(mux_external), Control(Clock_gate_uart2), Divider::undefined); |
paul@165 | 378 | |
paul@175 | 379 | Clock clock_uart3(Source(mux_external), Control(Clock_gate_uart3), Divider::undefined); |
paul@165 | 380 | |
paul@165 | 381 | |
paul@165 | 382 | |
paul@165 | 383 | // Clock register. |
paul@165 | 384 | |
paul@165 | 385 | static Clock_base *clocks[Clock_identifier_count] = { |
paul@165 | 386 | &clock_ahb2_apb, |
paul@175 | 387 | &clock_none, // Clock_aic_bitclk |
paul@175 | 388 | &clock_none, // Clock_aic_pclk |
paul@165 | 389 | &clock_can0, |
paul@165 | 390 | &clock_can1, |
paul@165 | 391 | &clock_cdbus, |
paul@165 | 392 | &clock_cim, |
paul@165 | 393 | &clock_cpu, |
paul@165 | 394 | &clock_ddr, |
paul@165 | 395 | &clock_dma, |
paul@175 | 396 | &clock_none, // Clock_emac |
paul@165 | 397 | &clock_external, |
paul@165 | 398 | &clock_hclock0, |
paul@165 | 399 | &clock_hclock2, |
paul@175 | 400 | &clock_none, // Clock_hdmi |
paul@165 | 401 | &clock_i2c, |
paul@165 | 402 | &clock_i2c0, |
paul@165 | 403 | &clock_i2c1, |
paul@175 | 404 | &clock_none, // Clock_i2s |
paul@165 | 405 | &clock_i2s0_rx, |
paul@165 | 406 | &clock_i2s0_tx, |
paul@175 | 407 | &clock_none, // Clock_kbc |
paul@175 | 408 | &clock_none, // Clock_lcd |
paul@165 | 409 | &clock_lcd_pixel, |
paul@165 | 410 | &clock_mac, |
paul@165 | 411 | &clock_main, |
paul@165 | 412 | &clock_msc, |
paul@165 | 413 | &clock_msc0, |
paul@165 | 414 | &clock_msc1, |
paul@165 | 415 | &clock_none, |
paul@165 | 416 | &clock_pclock, |
paul@165 | 417 | &clock_pll_A, |
paul@165 | 418 | &clock_pll_E, |
paul@165 | 419 | &clock_pll_M, |
paul@165 | 420 | &clock_pwm, |
paul@165 | 421 | &clock_pwm0, |
paul@175 | 422 | &clock_none, // Clock_pwm1 |
paul@175 | 423 | &clock_none, // Clock_scc |
paul@165 | 424 | &clock_sfc, |
paul@175 | 425 | &clock_none, // Clock_smb0 |
paul@175 | 426 | &clock_none, // Clock_smb1 |
paul@175 | 427 | &clock_none, // Clock_smb2 |
paul@175 | 428 | &clock_none, // Clock_smb3 |
paul@175 | 429 | &clock_none, // Clock_smb4 |
paul@165 | 430 | &clock_ssi, |
paul@165 | 431 | &clock_timer, |
paul@165 | 432 | &clock_uart0, |
paul@165 | 433 | &clock_uart1, |
paul@165 | 434 | &clock_uart2, |
paul@165 | 435 | &clock_uart3, |
paul@175 | 436 | &clock_none, // Clock_udc |
paul@175 | 437 | &clock_none, // Clock_uhc |
paul@175 | 438 | &clock_none, // Clock_uprt |
paul@165 | 439 | }; |
paul@165 | 440 | |
paul@165 | 441 | |
paul@165 | 442 | |
paul@160 | 443 | // If implemented as a Hw::Device, various properties would be |
paul@160 | 444 | // initialised in the constructor and obtained from the device tree |
paul@160 | 445 | // definitions. |
paul@160 | 446 | |
paul@160 | 447 | Cpm_x1600_chip::Cpm_x1600_chip(l4_addr_t addr, uint32_t exclk_freq) |
paul@173 | 448 | : _cpm_regs(addr, clocks, exclk_freq) |
paul@160 | 449 | { |
paul@160 | 450 | // add_cid("cpm"); |
paul@160 | 451 | // add_cid("cpm-x1600"); |
paul@165 | 452 | // register_property("exclk_freq", &exclk_freq); |
paul@161 | 453 | } |
paul@160 | 454 | |
paul@161 | 455 | int |
paul@161 | 456 | Cpm_x1600_chip::have_clock(enum Clock_identifiers clock) |
paul@161 | 457 | { |
paul@165 | 458 | return clocks[clock]->have_clock(_cpm_regs); |
paul@161 | 459 | } |
paul@161 | 460 | |
paul@161 | 461 | void |
paul@161 | 462 | Cpm_x1600_chip::start_clock(enum Clock_identifiers clock) |
paul@160 | 463 | { |
paul@165 | 464 | clocks[clock]->start_clock(_cpm_regs); |
paul@161 | 465 | } |
paul@161 | 466 | |
paul@161 | 467 | void |
paul@161 | 468 | Cpm_x1600_chip::stop_clock(enum Clock_identifiers clock) |
paul@161 | 469 | { |
paul@165 | 470 | clocks[clock]->stop_clock(_cpm_regs); |
paul@160 | 471 | } |
paul@160 | 472 | |
paul@161 | 473 | uint32_t |
paul@161 | 474 | Cpm_x1600_chip::get_divider(enum Clock_identifiers clock) |
paul@160 | 475 | { |
paul@175 | 476 | Clock *clk = dynamic_cast<Clock *>(clocks[clock]); |
paul@175 | 477 | |
paul@175 | 478 | if (clk != NULL) |
paul@175 | 479 | return clk->get_divider(_cpm_regs); |
paul@175 | 480 | else |
paul@175 | 481 | return 1; |
paul@160 | 482 | } |
paul@160 | 483 | |
paul@161 | 484 | void |
paul@161 | 485 | Cpm_x1600_chip::set_divider(enum Clock_identifiers clock, uint32_t division) |
paul@160 | 486 | { |
paul@175 | 487 | Clock *clk = dynamic_cast<Clock *>(clocks[clock]); |
paul@175 | 488 | |
paul@175 | 489 | if (clk != NULL) |
paul@175 | 490 | clk->set_divider(_cpm_regs, division); |
paul@160 | 491 | } |
paul@160 | 492 | |
paul@160 | 493 | uint8_t |
paul@161 | 494 | Cpm_x1600_chip::get_source(enum Clock_identifiers clock) |
paul@160 | 495 | { |
paul@175 | 496 | Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); |
paul@175 | 497 | |
paul@175 | 498 | if (clk != NULL) |
paul@175 | 499 | return clk->get_source(_cpm_regs); |
paul@175 | 500 | else |
paul@175 | 501 | return 0; |
paul@160 | 502 | } |
paul@160 | 503 | |
paul@160 | 504 | void |
paul@161 | 505 | Cpm_x1600_chip::set_source(enum Clock_identifiers clock, uint8_t source) |
paul@160 | 506 | { |
paul@175 | 507 | Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); |
paul@175 | 508 | |
paul@175 | 509 | if (clk != NULL) |
paul@175 | 510 | clk->set_source(_cpm_regs, source); |
paul@160 | 511 | } |
paul@160 | 512 | |
paul@161 | 513 | uint32_t |
paul@161 | 514 | Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock) |
paul@160 | 515 | { |
paul@175 | 516 | Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]); |
paul@175 | 517 | |
paul@175 | 518 | if (clk != NULL) |
paul@175 | 519 | return clk->get_source_frequency(_cpm_regs); |
paul@175 | 520 | else |
paul@175 | 521 | return 0; |
paul@160 | 522 | } |
paul@160 | 523 | |
paul@160 | 524 | uint32_t |
paul@160 | 525 | Cpm_x1600_chip::get_frequency(enum Clock_identifiers clock) |
paul@160 | 526 | { |
paul@165 | 527 | return clocks[clock]->get_frequency(_cpm_regs); |
paul@160 | 528 | } |
paul@160 | 529 | |
paul@160 | 530 | void |
paul@160 | 531 | Cpm_x1600_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 532 | { |
paul@160 | 533 | switch (clock) |
paul@160 | 534 | { |
paul@160 | 535 | // The pixel frequency is based on the selected clock source (SCLK_A, MPLL or |
paul@160 | 536 | // EPLL). |
paul@160 | 537 | |
paul@160 | 538 | case Clock_lcd_pixel: |
paul@165 | 539 | { |
paul@160 | 540 | |
paul@160 | 541 | // Switch to the MPLL and attempt to set the divider. |
paul@160 | 542 | |
paul@175 | 543 | Clock *lcd = dynamic_cast<Clock *>(clocks[Clock_lcd_pixel]); |
paul@165 | 544 | Clock_base *pll = clocks[Clock_pll_M]; |
paul@165 | 545 | |
paul@175 | 546 | if (lcd != NULL) |
paul@175 | 547 | { |
paul@175 | 548 | lcd->set_source(_cpm_regs, Source_mME_pll_M); |
paul@175 | 549 | pll->start_clock(_cpm_regs); |
paul@175 | 550 | lcd->set_divider(_cpm_regs, lcd->get_source_frequency(_cpm_regs) / frequency); |
paul@175 | 551 | } |
paul@160 | 552 | break; |
paul@165 | 553 | } |
paul@160 | 554 | |
paul@160 | 555 | default: |
paul@160 | 556 | break; |
paul@160 | 557 | } |
paul@160 | 558 | } |
paul@160 | 559 | |
paul@165 | 560 | void |
paul@165 | 561 | Cpm_x1600_chip::set_pll_parameters(enum Clock_identifiers clock, uint16_t multiplier, |
paul@165 | 562 | uint8_t in_divider, uint8_t out_divider) |
paul@165 | 563 | { |
paul@165 | 564 | Pll *pll = dynamic_cast<Pll *>(clocks[clock]); |
paul@165 | 565 | |
paul@175 | 566 | if (pll != NULL) |
paul@175 | 567 | pll->set_parameters(_cpm_regs, multiplier, in_divider, out_divider); |
paul@165 | 568 | } |
paul@165 | 569 | |
paul@160 | 570 | |
paul@160 | 571 | |
paul@160 | 572 | // C language interface functions. |
paul@160 | 573 | |
paul@160 | 574 | void |
paul@160 | 575 | *x1600_cpm_init(l4_addr_t cpm_base) |
paul@160 | 576 | { |
paul@160 | 577 | /* Initialise the clock and power management peripheral with the |
paul@160 | 578 | register memory region and a 24MHz EXCLK frequency. */ |
paul@160 | 579 | |
paul@160 | 580 | return (void *) new Cpm_x1600_chip(cpm_base, 24000000); |
paul@160 | 581 | } |
paul@160 | 582 | |
paul@160 | 583 | int |
paul@160 | 584 | x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 585 | { |
paul@160 | 586 | return static_cast<Cpm_x1600_chip *>(cpm)->have_clock(clock); |
paul@160 | 587 | } |
paul@160 | 588 | |
paul@160 | 589 | void |
paul@160 | 590 | x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 591 | { |
paul@160 | 592 | static_cast<Cpm_x1600_chip *>(cpm)->start_clock(clock); |
paul@160 | 593 | } |
paul@160 | 594 | |
paul@160 | 595 | void |
paul@160 | 596 | x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 597 | { |
paul@160 | 598 | static_cast<Cpm_x1600_chip *>(cpm)->stop_clock(clock); |
paul@160 | 599 | } |
paul@160 | 600 | |
paul@161 | 601 | uint32_t |
paul@161 | 602 | x1600_cpm_get_divider(void *cpm, enum Clock_identifiers clock) |
paul@160 | 603 | { |
paul@161 | 604 | return static_cast<Cpm_x1600_chip *>(cpm)->get_divider(clock); |
paul@160 | 605 | } |
paul@160 | 606 | |
paul@161 | 607 | void |
paul@161 | 608 | x1600_cpm_set_divider(void *cpm, enum Clock_identifiers clock, uint32_t divider) |
paul@160 | 609 | { |
paul@161 | 610 | return static_cast<Cpm_x1600_chip *>(cpm)->set_divider(clock, divider); |
paul@160 | 611 | } |
paul@160 | 612 | |
paul@160 | 613 | uint8_t |
paul@161 | 614 | x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock) |
paul@160 | 615 | { |
paul@161 | 616 | return static_cast<Cpm_x1600_chip *>(cpm)->get_source(clock); |
paul@160 | 617 | } |
paul@160 | 618 | |
paul@160 | 619 | void |
paul@161 | 620 | x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) |
paul@160 | 621 | { |
paul@161 | 622 | static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source); |
paul@160 | 623 | } |
paul@160 | 624 | |
paul@160 | 625 | uint32_t |
paul@161 | 626 | x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 627 | { |
paul@161 | 628 | return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock); |
paul@160 | 629 | } |
paul@160 | 630 | |
paul@160 | 631 | uint32_t |
paul@160 | 632 | x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 633 | { |
paul@160 | 634 | return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock); |
paul@160 | 635 | } |
paul@160 | 636 | |
paul@160 | 637 | void |
paul@160 | 638 | x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 639 | { |
paul@160 | 640 | static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency); |
paul@160 | 641 | } |
paul@160 | 642 | |
paul@160 | 643 | void |
paul@160 | 644 | x1600_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@160 | 645 | { |
paul@165 | 646 | static_cast<Cpm_x1600_chip *>(cpm)->set_pll_parameters(Clock_pll_M, multiplier, in_divider, out_divider); |
paul@160 | 647 | } |