paul@0 | 1 | /* |
paul@0 | 2 | * Clock and power management. This exposes the combined functionality |
paul@0 | 3 | * provided by the jz4740 and related SoCs. The power management |
paul@0 | 4 | * functionality could be exposed using a separate driver. |
paul@0 | 5 | * |
paul@0 | 6 | * (c) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 7 | * |
paul@0 | 8 | * This program is free software; you can redistribute it and/or |
paul@0 | 9 | * modify it under the terms of the GNU General Public License as |
paul@0 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 11 | * the License, or (at your option) any later version. |
paul@0 | 12 | * |
paul@0 | 13 | * This program is distributed in the hope that it will be useful, |
paul@0 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 16 | * GNU General Public License for more details. |
paul@0 | 17 | * |
paul@0 | 18 | * You should have received a copy of the GNU General Public License |
paul@0 | 19 | * along with this program; if not, write to the Free Software |
paul@0 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 21 | * Boston, MA 02110-1301, USA |
paul@0 | 22 | */ |
paul@0 | 23 | |
paul@0 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@0 | 25 | #include "cpm-jz4740.h" |
paul@0 | 26 | |
paul@0 | 27 | |
paul@0 | 28 | |
paul@0 | 29 | enum Regs : unsigned |
paul@0 | 30 | { |
paul@0 | 31 | Clock_control = 0x000, // CPCCR |
paul@0 | 32 | Low_power_control = 0x004, // LCR |
paul@0 | 33 | Pll_control = 0x010, // CPPCR |
paul@0 | 34 | Clock_gate = 0x020, // CLKGR |
paul@0 | 35 | Sleep_control = 0x024, // SCR |
paul@0 | 36 | I2s_divider = 0x060, // I2SCDR |
paul@0 | 37 | Lcd_divider = 0x064, // LPCDR |
paul@0 | 38 | Msc_divider = 0x068, // MSCCDR |
paul@0 | 39 | Uhc_divider = 0x06c, // UHCCDR |
paul@0 | 40 | Ssi_divider = 0x074, // SSICDR |
paul@0 | 41 | }; |
paul@0 | 42 | |
paul@0 | 43 | enum Clock_bits : unsigned |
paul@0 | 44 | { |
paul@0 | 45 | Clock_enable = 22, // CE |
paul@0 | 46 | Clock_pllout_source = 21, // PCS |
paul@0 | 47 | Clock_lcd_divider = 16, // LCD |
paul@0 | 48 | Clock_memory_divider = 12, // MDIV |
paul@0 | 49 | Clock_pclock_divider = 8, // PDIV (slow APB peripherals) |
paul@0 | 50 | Clock_hclock_divider = 4, // HDIV (fast AHB peripherals) |
paul@0 | 51 | Clock_cpu_divider = 0, // CDIV |
paul@0 | 52 | }; |
paul@0 | 53 | |
paul@0 | 54 | enum Pll_bits : unsigned |
paul@0 | 55 | { |
paul@0 | 56 | Pll_multiplier = 23, // PLLM |
paul@0 | 57 | Pll_input_division = 18, // PLLN |
paul@0 | 58 | Pll_output_division = 16, // PLLOD |
paul@0 | 59 | Pll_stable = 10, // PLLS |
paul@0 | 60 | Pll_bypassed = 9, // PLLBP |
paul@0 | 61 | Pll_enabled = 8, // PLLEN |
paul@0 | 62 | }; |
paul@0 | 63 | |
paul@0 | 64 | enum Clock_gate_bits : unsigned |
paul@0 | 65 | { |
paul@0 | 66 | Clock_gate_lcd = 10, // LCD |
paul@0 | 67 | Clock_gate_timer = 1, // TCU |
paul@0 | 68 | }; |
paul@0 | 69 | |
paul@0 | 70 | enum Lcd_divider_bits : unsigned |
paul@0 | 71 | { |
paul@0 | 72 | Lcd_divider_value = 0, |
paul@0 | 73 | }; |
paul@0 | 74 | |
paul@0 | 75 | |
paul@0 | 76 | |
paul@0 | 77 | // If implemented as a Hw::Device, various properties would be |
paul@0 | 78 | // initialised in the constructor and obtained from the device tree |
paul@0 | 79 | // definitions. |
paul@0 | 80 | |
paul@0 | 81 | Cpm_jz4740_chip::Cpm_jz4740_chip(l4_addr_t addr, uint32_t exclk_freq) |
paul@0 | 82 | : _exclk_freq(exclk_freq) |
paul@0 | 83 | { |
paul@0 | 84 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@0 | 85 | |
paul@0 | 86 | // add_cid("cpm"); |
paul@0 | 87 | // add_cid("cpm-jz4740"); |
paul@0 | 88 | // register_property("exclk_freq", &_exclk_freq); |
paul@0 | 89 | } |
paul@0 | 90 | |
paul@0 | 91 | // Clock/timer control. |
paul@0 | 92 | |
paul@0 | 93 | int |
paul@0 | 94 | Cpm_jz4740_chip::have_clock() |
paul@0 | 95 | { |
paul@0 | 96 | return !(_regs[Clock_gate] & (1 << Clock_gate_timer)); |
paul@0 | 97 | } |
paul@0 | 98 | |
paul@0 | 99 | void |
paul@0 | 100 | Cpm_jz4740_chip::start_clock() |
paul@0 | 101 | { |
paul@0 | 102 | _regs[Clock_gate] = _regs[Clock_gate] & ~(1 << Clock_gate_timer); |
paul@0 | 103 | } |
paul@0 | 104 | |
paul@0 | 105 | // PLL control. |
paul@0 | 106 | |
paul@0 | 107 | // Return whether the PLL is stable. |
paul@0 | 108 | |
paul@0 | 109 | int |
paul@0 | 110 | Cpm_jz4740_chip::have_pll() |
paul@0 | 111 | { |
paul@0 | 112 | return _regs[Pll_control] & (1 << Pll_stable); |
paul@0 | 113 | } |
paul@0 | 114 | |
paul@0 | 115 | int |
paul@0 | 116 | Cpm_jz4740_chip::pll_enabled() |
paul@0 | 117 | { |
paul@0 | 118 | return _regs[Pll_control] & (1 << Pll_enabled); |
paul@0 | 119 | } |
paul@0 | 120 | |
paul@0 | 121 | int |
paul@0 | 122 | Cpm_jz4740_chip::pll_bypassed() |
paul@0 | 123 | { |
paul@0 | 124 | return _regs[Pll_control] & (1 << Pll_bypassed); |
paul@0 | 125 | } |
paul@0 | 126 | |
paul@0 | 127 | // Feedback (9-bit) multiplier. |
paul@0 | 128 | |
paul@0 | 129 | uint16_t |
paul@0 | 130 | Cpm_jz4740_chip::get_multiplier() |
paul@0 | 131 | { |
paul@0 | 132 | return ((_regs[Pll_control] & (0x1ff << Pll_multiplier)) >> Pll_multiplier) + 2; |
paul@0 | 133 | } |
paul@0 | 134 | |
paul@0 | 135 | // Input (5-bit) divider. |
paul@0 | 136 | |
paul@0 | 137 | uint8_t |
paul@0 | 138 | Cpm_jz4740_chip::get_input_division() |
paul@0 | 139 | { |
paul@0 | 140 | return ((_regs[Pll_control] & (0x1f << Pll_input_division)) >> Pll_input_division) + 2; |
paul@0 | 141 | } |
paul@0 | 142 | |
paul@0 | 143 | // Output divider. |
paul@0 | 144 | |
paul@0 | 145 | uint8_t |
paul@0 | 146 | Cpm_jz4740_chip::get_output_division() |
paul@0 | 147 | { |
paul@0 | 148 | uint8_t od[4] = {1, 2, 2, 4}; |
paul@0 | 149 | return od[(_regs[Pll_control] & (0x03 << Pll_output_division)) >> Pll_output_division]; |
paul@0 | 150 | } |
paul@0 | 151 | |
paul@0 | 152 | // General clock divider. |
paul@0 | 153 | |
paul@0 | 154 | uint8_t |
paul@0 | 155 | Cpm_jz4740_chip::_get_divider(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@0 | 156 | { |
paul@0 | 157 | uint8_t cd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@0 | 158 | uint8_t d = (_regs[reg] & mask) >> shift; |
paul@0 | 159 | return (d < 10) ? cd[d] : 1; |
paul@0 | 160 | } |
paul@0 | 161 | |
paul@0 | 162 | // CPU clock (CCLK) divider. |
paul@0 | 163 | |
paul@0 | 164 | uint8_t |
paul@0 | 165 | Cpm_jz4740_chip::get_cpu_divider() |
paul@0 | 166 | { |
paul@0 | 167 | return _get_divider(Clock_control, 0xf << Clock_cpu_divider, Clock_cpu_divider); |
paul@0 | 168 | } |
paul@0 | 169 | |
paul@0 | 170 | // Fast peripheral clock (HCLK) divider. |
paul@0 | 171 | |
paul@0 | 172 | uint8_t |
paul@0 | 173 | Cpm_jz4740_chip::get_hclock_divider() |
paul@0 | 174 | { |
paul@0 | 175 | return _get_divider(Clock_control, 0xf << Clock_hclock_divider, Clock_hclock_divider); |
paul@0 | 176 | } |
paul@0 | 177 | |
paul@0 | 178 | // Slow peripheral clock (PCLK) divider. |
paul@0 | 179 | |
paul@0 | 180 | uint8_t |
paul@0 | 181 | Cpm_jz4740_chip::get_pclock_divider() |
paul@0 | 182 | { |
paul@0 | 183 | return _get_divider(Clock_control, 0xf << Clock_pclock_divider, Clock_pclock_divider); |
paul@0 | 184 | } |
paul@0 | 185 | |
paul@0 | 186 | // Memory clock (MCLK) divider. |
paul@0 | 187 | |
paul@0 | 188 | uint8_t |
paul@0 | 189 | Cpm_jz4740_chip::get_memory_divider() |
paul@0 | 190 | { |
paul@0 | 191 | return _get_divider(Clock_control, 0xf << Clock_memory_divider, Clock_memory_divider); |
paul@0 | 192 | } |
paul@0 | 193 | |
paul@0 | 194 | // Clock source divider for MSC, I2S, LCD and USB. |
paul@0 | 195 | |
paul@0 | 196 | uint8_t |
paul@0 | 197 | Cpm_jz4740_chip::get_source_divider() |
paul@0 | 198 | { |
paul@0 | 199 | return _regs[Clock_control] & (1 << Clock_pllout_source) ? 1 : 2; |
paul@0 | 200 | } |
paul@0 | 201 | |
paul@0 | 202 | // LCD device clock divider. |
paul@0 | 203 | |
paul@0 | 204 | void |
paul@0 | 205 | Cpm_jz4740_chip::set_lcd_device_divider(uint8_t division) |
paul@0 | 206 | { |
paul@0 | 207 | if (division == 0) |
paul@0 | 208 | division = 1; |
paul@0 | 209 | else if (division > 32) |
paul@0 | 210 | division = 32; |
paul@0 | 211 | |
paul@0 | 212 | _regs[Clock_control] = (_regs[Clock_control] & ~(0x1f << Clock_lcd_divider)) | |
paul@0 | 213 | ((division - 1) << Clock_lcd_divider); |
paul@0 | 214 | } |
paul@0 | 215 | |
paul@0 | 216 | // LCD pixel clock divider. |
paul@0 | 217 | |
paul@0 | 218 | uint16_t |
paul@0 | 219 | Cpm_jz4740_chip::get_lcd_pixel_divider() |
paul@0 | 220 | { |
paul@0 | 221 | return (_regs[Lcd_divider] >> Lcd_divider_value) + 1; |
paul@0 | 222 | } |
paul@0 | 223 | |
paul@0 | 224 | void |
paul@0 | 225 | Cpm_jz4740_chip::set_lcd_pixel_divider(uint16_t division) |
paul@0 | 226 | { |
paul@0 | 227 | if (division == 0) |
paul@0 | 228 | division = 1; |
paul@0 | 229 | else if (division > 2048) |
paul@0 | 230 | division = 2048; |
paul@0 | 231 | |
paul@0 | 232 | _regs[Lcd_divider] = (_regs[Lcd_divider] & ~(0x7ff << Lcd_divider_value)) | |
paul@0 | 233 | ((division - 1) << Lcd_divider_value); |
paul@0 | 234 | } |
paul@0 | 235 | |
paul@0 | 236 | |
paul@0 | 237 | |
paul@0 | 238 | uint32_t |
paul@0 | 239 | Cpm_jz4740_chip::get_lcd_pixel_frequency() |
paul@0 | 240 | { |
paul@0 | 241 | return get_output_frequency() / get_lcd_pixel_divider(); |
paul@0 | 242 | } |
paul@0 | 243 | |
paul@0 | 244 | // Set the device and pixel frequencies, indicating the latter and |
paul@0 | 245 | // providing the device:pixel frequency ratio. |
paul@0 | 246 | |
paul@0 | 247 | void |
paul@0 | 248 | Cpm_jz4740_chip::set_lcd_frequencies(uint32_t pclk, uint8_t ratio) |
paul@0 | 249 | { |
paul@0 | 250 | uint32_t out = get_output_frequency(), |
paul@0 | 251 | lcd = pclk * ratio; |
paul@0 | 252 | |
paul@0 | 253 | set_lcd_pixel_divider(out / pclk); |
paul@0 | 254 | |
paul@0 | 255 | // Limit the device frequency to 150MHz. |
paul@0 | 256 | |
paul@0 | 257 | if (lcd > 150000000) lcd = 150000000; |
paul@0 | 258 | |
paul@0 | 259 | set_lcd_device_divider(out / lcd); |
paul@0 | 260 | } |
paul@0 | 261 | |
paul@0 | 262 | |
paul@0 | 263 | |
paul@0 | 264 | // LCD clock control. |
paul@0 | 265 | |
paul@0 | 266 | void |
paul@0 | 267 | Cpm_jz4740_chip::start_lcd() |
paul@0 | 268 | { |
paul@0 | 269 | _regs[Clock_gate] = _regs[Clock_gate] & ~(1 << Clock_gate_lcd); |
paul@0 | 270 | } |
paul@0 | 271 | |
paul@0 | 272 | void |
paul@0 | 273 | Cpm_jz4740_chip::stop_lcd() |
paul@0 | 274 | { |
paul@0 | 275 | _regs[Clock_gate] = _regs[Clock_gate] | (1 << Clock_gate_lcd); |
paul@0 | 276 | } |
paul@0 | 277 | |
paul@0 | 278 | |
paul@0 | 279 | |
paul@0 | 280 | uint32_t |
paul@0 | 281 | Cpm_jz4740_chip::get_pll_frequency() |
paul@0 | 282 | { |
paul@0 | 283 | // Test for PLL enable and not PLL bypass. |
paul@0 | 284 | |
paul@0 | 285 | if (pll_enabled() && !pll_bypassed()) |
paul@0 | 286 | return (_exclk_freq * get_multiplier()) / |
paul@0 | 287 | (get_input_division() * get_output_division()); |
paul@0 | 288 | else |
paul@0 | 289 | return _exclk_freq; |
paul@0 | 290 | } |
paul@0 | 291 | |
paul@0 | 292 | // Clock frequency for MSC, I2S, LCD and USB. |
paul@0 | 293 | |
paul@0 | 294 | uint32_t |
paul@0 | 295 | Cpm_jz4740_chip::get_output_frequency() |
paul@0 | 296 | { |
paul@0 | 297 | return get_pll_frequency() / get_source_divider(); |
paul@0 | 298 | } |
paul@0 | 299 | |
paul@0 | 300 | void |
paul@0 | 301 | Cpm_jz4740_chip::update_output_frequency() |
paul@0 | 302 | { |
paul@0 | 303 | _regs[Clock_control] = _regs[Clock_control] | (1 << Clock_enable); |
paul@0 | 304 | } |
paul@0 | 305 | |
paul@0 | 306 | // Clock frequency for the CPU. |
paul@0 | 307 | |
paul@0 | 308 | uint32_t Cpm_jz4740_chip::get_cpu_frequency() |
paul@0 | 309 | { |
paul@0 | 310 | return get_pll_frequency() / get_cpu_divider(); |
paul@0 | 311 | } |
paul@0 | 312 | |
paul@0 | 313 | // Clock frequency for fast peripherals. |
paul@0 | 314 | |
paul@0 | 315 | uint32_t |
paul@0 | 316 | Cpm_jz4740_chip::get_hclock_frequency() |
paul@0 | 317 | { |
paul@0 | 318 | return get_pll_frequency() / get_hclock_divider(); |
paul@0 | 319 | } |
paul@0 | 320 | |
paul@0 | 321 | // Clock frequency for slow peripherals. |
paul@0 | 322 | |
paul@0 | 323 | uint32_t |
paul@0 | 324 | Cpm_jz4740_chip::get_pclock_frequency() |
paul@0 | 325 | { |
paul@0 | 326 | return get_pll_frequency() / get_pclock_divider(); |
paul@0 | 327 | } |
paul@0 | 328 | |
paul@0 | 329 | // Clock frequency for the memory. |
paul@0 | 330 | |
paul@0 | 331 | uint32_t |
paul@0 | 332 | Cpm_jz4740_chip::get_memory_frequency() |
paul@0 | 333 | { |
paul@0 | 334 | return get_pll_frequency() / get_memory_divider(); |
paul@0 | 335 | } |
paul@0 | 336 | |
paul@0 | 337 | |
paul@0 | 338 | |
paul@0 | 339 | // C language interface functions. |
paul@0 | 340 | |
paul@0 | 341 | void |
paul@0 | 342 | *jz4740_cpm_init(l4_addr_t cpm_base) |
paul@0 | 343 | { |
paul@0 | 344 | /* Initialise the clock and power management peripheral with the |
paul@0 | 345 | register memory region and a 12MHz EXCLK frequency. */ |
paul@0 | 346 | |
paul@0 | 347 | return (void *) new Cpm_jz4740_chip(cpm_base, 12000000); |
paul@0 | 348 | } |
paul@0 | 349 | |
paul@0 | 350 | int |
paul@0 | 351 | jz4740_cpm_have_clock(void *cpm) |
paul@0 | 352 | { |
paul@0 | 353 | return static_cast<Cpm_jz4740_chip *>(cpm)->have_clock(); |
paul@0 | 354 | } |
paul@0 | 355 | |
paul@0 | 356 | void |
paul@0 | 357 | jz4740_cpm_start_clock(void *cpm) |
paul@0 | 358 | { |
paul@0 | 359 | static_cast<Cpm_jz4740_chip *>(cpm)->start_clock(); |
paul@0 | 360 | } |
paul@0 | 361 | |
paul@0 | 362 | void |
paul@0 | 363 | jz4740_cpm_start_lcd(void *cpm) |
paul@0 | 364 | { |
paul@0 | 365 | static_cast<Cpm_jz4740_chip *>(cpm)->start_lcd(); |
paul@0 | 366 | } |
paul@0 | 367 | |
paul@0 | 368 | void |
paul@0 | 369 | jz4740_cpm_stop_lcd(void *cpm) |
paul@0 | 370 | { |
paul@0 | 371 | static_cast<Cpm_jz4740_chip *>(cpm)->stop_lcd(); |
paul@0 | 372 | } |
paul@0 | 373 | |
paul@0 | 374 | uint32_t |
paul@0 | 375 | jz4740_cpm_get_cpu_frequency(void *cpm) |
paul@0 | 376 | { |
paul@0 | 377 | return static_cast<Cpm_jz4740_chip *>(cpm)->get_cpu_frequency(); |
paul@0 | 378 | } |
paul@0 | 379 | |
paul@0 | 380 | uint32_t |
paul@0 | 381 | jz4740_cpm_get_hclock_frequency(void *cpm) |
paul@0 | 382 | { |
paul@0 | 383 | return static_cast<Cpm_jz4740_chip *>(cpm)->get_hclock_frequency(); |
paul@0 | 384 | } |
paul@0 | 385 | |
paul@0 | 386 | uint32_t |
paul@0 | 387 | jz4740_cpm_get_output_frequency(void *cpm) |
paul@0 | 388 | { |
paul@0 | 389 | return static_cast<Cpm_jz4740_chip *>(cpm)->get_output_frequency(); |
paul@0 | 390 | } |
paul@0 | 391 | |
paul@0 | 392 | uint32_t |
paul@0 | 393 | jz4740_cpm_get_pclock_frequency(void *cpm) |
paul@0 | 394 | { |
paul@0 | 395 | return static_cast<Cpm_jz4740_chip *>(cpm)->get_pclock_frequency(); |
paul@0 | 396 | } |
paul@0 | 397 | |
paul@0 | 398 | uint32_t |
paul@0 | 399 | jz4740_cpm_get_memory_frequency(void *cpm) |
paul@0 | 400 | { |
paul@0 | 401 | return static_cast<Cpm_jz4740_chip *>(cpm)->get_memory_frequency(); |
paul@0 | 402 | } |
paul@0 | 403 | |
paul@0 | 404 | uint16_t |
paul@0 | 405 | jz4740_cpm_get_lcd_pixel_divider(void *cpm) |
paul@0 | 406 | { |
paul@0 | 407 | return static_cast<Cpm_jz4740_chip *>(cpm)->get_lcd_pixel_divider(); |
paul@0 | 408 | } |
paul@0 | 409 | |
paul@0 | 410 | uint32_t |
paul@0 | 411 | jz4740_cpm_get_lcd_pixel_frequency(void *cpm) |
paul@0 | 412 | { |
paul@0 | 413 | return static_cast<Cpm_jz4740_chip *>(cpm)->get_lcd_pixel_frequency(); |
paul@0 | 414 | } |
paul@0 | 415 | |
paul@0 | 416 | void |
paul@0 | 417 | jz4740_cpm_set_lcd_frequencies(void *cpm, uint32_t pclk, uint8_t ratio) |
paul@0 | 418 | { |
paul@0 | 419 | static_cast<Cpm_jz4740_chip *>(cpm)->set_lcd_frequencies(pclk, ratio); |
paul@0 | 420 | } |
paul@0 | 421 | |
paul@0 | 422 | void |
paul@0 | 423 | jz4740_cpm_update_output_frequency(void *cpm) |
paul@0 | 424 | { |
paul@0 | 425 | static_cast<Cpm_jz4740_chip *>(cpm)->update_output_frequency(); |
paul@0 | 426 | } |