paul@0 | 1 | /* |
paul@0 | 2 | * LCD peripheral support for the JZ4740 and related SoCs. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> |
paul@0 | 5 | * Copyright (C) 2015, 2016, 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 6 | * |
paul@0 | 7 | * This program is free software; you can redistribute it and/or |
paul@0 | 8 | * modify it under the terms of the GNU General Public License as |
paul@0 | 9 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 10 | * the License, or (at your option) any later version. |
paul@0 | 11 | * |
paul@0 | 12 | * This program is distributed in the hope that it will be useful, |
paul@0 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 15 | * GNU General Public License for more details. |
paul@0 | 16 | * |
paul@0 | 17 | * You should have received a copy of the GNU General Public License |
paul@0 | 18 | * along with this program; if not, write to the Free Software |
paul@0 | 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 20 | * Boston, MA 02110-1301, USA |
paul@0 | 21 | */ |
paul@0 | 22 | |
paul@0 | 23 | #include <l4/devices/hw_mmio_register_block.h> |
paul@0 | 24 | #include <l4/sys/cache.h> |
paul@0 | 25 | #include <l4/sys/types.h> |
paul@0 | 26 | |
paul@0 | 27 | #include "lcd-jz4740.h" |
paul@0 | 28 | #include "lcd-jz4740-config.h" |
paul@0 | 29 | |
paul@0 | 30 | #include <stdint.h> |
paul@0 | 31 | |
paul@0 | 32 | enum Regs : unsigned |
paul@0 | 33 | { |
paul@0 | 34 | Lcd_config = 0x000, // LCD_CFG |
paul@0 | 35 | Lcd_vsync = 0x004, // LCD_VSYNC |
paul@0 | 36 | Lcd_hsync = 0x008, // LCD_HSYNC |
paul@0 | 37 | Vertical_area = 0x00c, // LCD_VAT |
paul@0 | 38 | Display_hlimits = 0x010, // LCD_DAH |
paul@0 | 39 | Display_vlimits = 0x014, // LCD_DAV |
paul@0 | 40 | Lcd_ps = 0x018, // LCD_PS |
paul@0 | 41 | Lcd_cls = 0x01c, // LCD_CLS |
paul@0 | 42 | Lcd_spl = 0x020, // LCD_SPL |
paul@0 | 43 | Lcd_rev = 0x024, // LCD_REV |
paul@0 | 44 | Lcd_control = 0x030, // LCD_CTRL |
paul@0 | 45 | Lcd_status = 0x034, // LCD_STATE |
paul@0 | 46 | Lcd_irq_id = 0x038, // LCD_IID |
paul@0 | 47 | Desc_address_0 = 0x040, // LCD_DA0 |
paul@0 | 48 | Source_address_0 = 0x044, // LCD_SA0 |
paul@0 | 49 | Frame_id_0 = 0x048, // LCD_FID0 |
paul@0 | 50 | Command_0 = 0x04c, // LCD_CMD0 |
paul@0 | 51 | Desc_address_1 = 0x050, // LCD_DA1 |
paul@0 | 52 | Source_address_1 = 0x054, // LCD_SA1 |
paul@0 | 53 | Frame_id_1 = 0x058, // LCD_FID1 |
paul@0 | 54 | Command_1 = 0x05c, // LCD_CMD1 |
paul@0 | 55 | }; |
paul@0 | 56 | |
paul@0 | 57 | // Lcd_config descriptions. |
paul@0 | 58 | |
paul@0 | 59 | enum Config_values : unsigned |
paul@0 | 60 | { |
paul@0 | 61 | Config_stn_pins_mask = 0x3, |
paul@0 | 62 | Config_mode_mask = 0xf, |
paul@0 | 63 | }; |
paul@0 | 64 | |
paul@0 | 65 | // Field positions for registers employing two values, with the first typically |
paul@0 | 66 | // being the start value and the second being an end value. |
paul@0 | 67 | |
paul@0 | 68 | enum Value_pair_bits : unsigned |
paul@0 | 69 | { |
paul@0 | 70 | Value_first = 16, |
paul@0 | 71 | Value_second = 0, |
paul@0 | 72 | }; |
paul@0 | 73 | |
paul@0 | 74 | // Vertical_area bits. |
paul@0 | 75 | |
paul@0 | 76 | enum Vertical_area_values : unsigned |
paul@0 | 77 | { |
paul@0 | 78 | Vertical_area_horizontal_size = Value_first, // sum of display and blank regions (dot/pixel clock periods) |
paul@0 | 79 | Vertical_area_vertical_size = Value_second, // sum of display and blank regions (line periods) |
paul@0 | 80 | }; |
paul@0 | 81 | |
paul@0 | 82 | // Lcd_control descriptions. |
paul@0 | 83 | |
paul@0 | 84 | enum Control_bits : unsigned |
paul@0 | 85 | { |
paul@0 | 86 | Control_burst_length = 28, // BST (burst length selection) |
paul@0 | 87 | Control_rgb_mode = 27, // RGB (RGB mode) |
paul@0 | 88 | Control_out_underrun = 26, // OFUP (output FIFO underrun protection) |
paul@0 | 89 | Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection) |
paul@0 | 90 | Control_palette_delay = 16, // PDD (load palette delay counter) |
paul@0 | 91 | Control_frame_end_irq_mask = 13, // EOFM (end of frame interrupt mask) |
paul@0 | 92 | Control_frame_start_irq_mask = 12, // SOFM (start of frame interrupt mask) |
paul@0 | 93 | Control_out_underrun_irq_mask = 11, // OFUM (output FIFO underrun interrupt mask) |
paul@0 | 94 | Control_in0_underrun_irq_mask = 10, // IFUM0 (input FIFO 0 underrun interrupt mask) |
paul@0 | 95 | Control_in1_underrun_irq_mask = 9, // IFUM1 (input FIFO 1 underrun interrupt mask) |
paul@0 | 96 | Control_disabled_irq_mask = 8, // LDDM (LCD disable done interrupt mask) |
paul@0 | 97 | Control_quick_disabled_irq_mask = 7, // QDM (LCD quick disable done interrupt mask) |
paul@0 | 98 | Control_endian_select = 6, // BEDN (endian selection) |
paul@0 | 99 | Control_bit_order = 5, // PEDN (bit order in bytes) |
paul@0 | 100 | Control_disable = 4, // DIS (disable controller) |
paul@0 | 101 | Control_enable = 3, // ENA (enable controller) |
paul@0 | 102 | Control_bpp = 0, // BPP (bits per pixel) |
paul@0 | 103 | }; |
paul@0 | 104 | |
paul@0 | 105 | enum Burst_length_values : unsigned |
paul@0 | 106 | { |
paul@0 | 107 | Burst_length_4 = 0, // 4 word |
paul@0 | 108 | Burst_length_8 = 1, // 8 word |
paul@0 | 109 | Burst_length_16 = 2, // 16 word |
paul@0 | 110 | |
paul@0 | 111 | // JZ4780 extensions. |
paul@0 | 112 | |
paul@0 | 113 | Burst_length_32 = 3, // 32 word |
paul@0 | 114 | Burst_length_64 = 4, // 64 word |
paul@0 | 115 | Burst_length_mask = 0x7, |
paul@0 | 116 | }; |
paul@0 | 117 | |
paul@0 | 118 | enum Rgb_mode_values : unsigned |
paul@0 | 119 | { |
paul@0 | 120 | Rgb_mode_565 = 0, |
paul@0 | 121 | Rgb_mode_555 = 1, |
paul@0 | 122 | Rgb_mode_mask = 0x1, |
paul@0 | 123 | }; |
paul@0 | 124 | |
paul@0 | 125 | enum Frc_algorithm_values : unsigned |
paul@0 | 126 | { |
paul@0 | 127 | Frc_greyscales_16 = 0, |
paul@0 | 128 | Frc_greyscales_4 = 1, |
paul@0 | 129 | Frc_greyscales_2 = 2, |
paul@0 | 130 | Frc_greyscales_mask = 0x3, |
paul@0 | 131 | }; |
paul@0 | 132 | |
paul@0 | 133 | enum Control_bpp_values : unsigned |
paul@0 | 134 | { |
paul@0 | 135 | Control_bpp_1bpp = 0, |
paul@0 | 136 | Control_bpp_2bpp = 1, |
paul@0 | 137 | Control_bpp_4bpp = 2, |
paul@0 | 138 | Control_bpp_8bpp = 3, |
paul@0 | 139 | Control_bpp_15bpp = 4, |
paul@0 | 140 | Control_bpp_16bpp = 4, |
paul@0 | 141 | Control_bpp_18bpp = 5, |
paul@0 | 142 | Control_bpp_24bpp = 5, |
paul@0 | 143 | Control_bpp_24bpp_comp = 6, |
paul@0 | 144 | Control_bpp_30bpp = 7, |
paul@0 | 145 | Control_bpp_32bpp = 7, |
paul@0 | 146 | Control_bpp_mask = 0x7, |
paul@0 | 147 | }; |
paul@0 | 148 | |
paul@0 | 149 | // Command descriptions. |
paul@0 | 150 | |
paul@0 | 151 | enum Command_bits : unsigned |
paul@0 | 152 | { |
paul@0 | 153 | Command_frame_start_irq = 31, // SOFINT (start of frame interrupt) |
paul@0 | 154 | Command_frame_end_irq = 30, // EOFINT (end of frame interrupt) |
paul@0 | 155 | Command_lcm_command = 29, // JZ4780: CMD (LCM command/data via DMA0) |
paul@0 | 156 | Command_palette_buffer = 28, // PAL (descriptor references palette, not display data) |
paul@0 | 157 | Command_frame_compressed = 27, // JZ4780: COMPEN (16/24bpp compression enabled) |
paul@0 | 158 | Command_frame_enable = 26, // JZ4780: FRM_EN |
paul@0 | 159 | Command_field_even = 25, // JZ4780: FIELD_SEL (interlace even field) |
paul@0 | 160 | Command_16x16_block = 24, // JZ4780: 16x16BLOCK (fetch data by 16x16 block) |
paul@0 | 161 | Command_buffer_length = 0, // LEN |
paul@0 | 162 | }; |
paul@0 | 163 | |
paul@0 | 164 | enum Command_values : unsigned |
paul@0 | 165 | { |
paul@0 | 166 | Command_buffer_length_mask = 0x00ffffff, |
paul@0 | 167 | }; |
paul@0 | 168 | |
paul@0 | 169 | |
paul@0 | 170 | |
paul@0 | 171 | // Utility functions. |
paul@0 | 172 | |
paul@0 | 173 | // Round values up according to the resolution. |
paul@0 | 174 | |
paul@0 | 175 | static uint32_t align(uint32_t value, uint32_t resolution) |
paul@0 | 176 | { |
paul@0 | 177 | return (value + (resolution - 1)) & ~(resolution - 1); |
paul@0 | 178 | } |
paul@0 | 179 | |
paul@0 | 180 | // Value pair encoding. |
paul@0 | 181 | |
paul@0 | 182 | static uint32_t encode_pair(uint32_t start, uint32_t end) |
paul@0 | 183 | { |
paul@0 | 184 | return (start << Value_first) | (end << Value_second); |
paul@0 | 185 | } |
paul@0 | 186 | |
paul@0 | 187 | // RGB conversions. |
paul@0 | 188 | |
paul@0 | 189 | static uint16_t rgb8_to_rgb16(uint8_t rgb) |
paul@0 | 190 | { |
paul@0 | 191 | return ((((rgb & 0xe0) >> 5) * 4) << 11) | ((((rgb & 0x1c) >> 2) * 9) << 6) | ((rgb & 0x03) * 10); |
paul@0 | 192 | } |
paul@0 | 193 | |
paul@0 | 194 | static uint16_t rgb4_to_rgb16(uint8_t rgb) |
paul@0 | 195 | { |
paul@0 | 196 | return ((((rgb & 8) >> 3) * 0x1f) << 11) | ((((rgb & 6) >> 1) * 0x15) << 5) | ((rgb & 1) * 0x1f); |
paul@0 | 197 | } |
paul@0 | 198 | |
paul@0 | 199 | |
paul@0 | 200 | |
paul@0 | 201 | |
paul@0 | 202 | // If implemented as a Hw::Device, various properties would be |
paul@0 | 203 | // initialised in the constructor and obtained from the device tree |
paul@0 | 204 | // definitions. |
paul@0 | 205 | |
paul@0 | 206 | Lcd_jz4740_chip::Lcd_jz4740_chip(l4_addr_t addr, Jz4740_lcd_panel *panel) |
paul@0 | 207 | : _panel(panel) |
paul@0 | 208 | { |
paul@0 | 209 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@0 | 210 | _burst_size = 16; // 16-word burst size |
paul@0 | 211 | |
paul@0 | 212 | // add_cid("lcd"); |
paul@0 | 213 | // add_cid("lcd-jz4740"); |
paul@0 | 214 | } |
paul@0 | 215 | |
paul@0 | 216 | struct Jz4740_lcd_panel * |
paul@0 | 217 | Lcd_jz4740_chip::get_panel() |
paul@0 | 218 | { |
paul@0 | 219 | return _panel; |
paul@0 | 220 | } |
paul@0 | 221 | |
paul@0 | 222 | void |
paul@0 | 223 | Lcd_jz4740_chip::disable() |
paul@0 | 224 | { |
paul@0 | 225 | // Set the disable bit for normal shutdown. |
paul@0 | 226 | |
paul@0 | 227 | _regs[Lcd_control] = _regs[Lcd_control] | (1 << Control_disable); |
paul@0 | 228 | } |
paul@0 | 229 | |
paul@0 | 230 | void |
paul@0 | 231 | Lcd_jz4740_chip::disable_quick() |
paul@0 | 232 | { |
paul@0 | 233 | // Clear the enable bit for quick shutdown. |
paul@0 | 234 | |
paul@0 | 235 | _regs[Lcd_control] = _regs[Lcd_control] & ~(1 << Control_enable); |
paul@0 | 236 | } |
paul@0 | 237 | |
paul@0 | 238 | void |
paul@0 | 239 | Lcd_jz4740_chip::enable() |
paul@0 | 240 | { |
paul@0 | 241 | // Clear the disable bit and set the enable bit. |
paul@0 | 242 | |
paul@0 | 243 | _regs[Lcd_control] = (_regs[Lcd_control] & ~(1 << Control_disable)) | (1 << Control_enable); |
paul@0 | 244 | } |
paul@0 | 245 | |
paul@0 | 246 | // Calculate and return the pixel clock frequency. |
paul@0 | 247 | |
paul@0 | 248 | int |
paul@0 | 249 | Lcd_jz4740_chip::get_pixel_clock() |
paul@0 | 250 | { |
paul@0 | 251 | int pclk, multiplier; |
paul@0 | 252 | |
paul@0 | 253 | // Serial mode: 3 pixel clock cycles per pixel (one per channel). |
paul@0 | 254 | // Parallel mode: 1 pixel clock cycle per pixel. |
paul@0 | 255 | |
paul@0 | 256 | multiplier = have_serial_tft() ? 3 : 1; |
paul@0 | 257 | |
paul@0 | 258 | // Derive pixel clock rate from frame rate. |
paul@0 | 259 | // This multiplies the number of pixel periods in a line by the number of |
paul@0 | 260 | // lines in a frame, thus obtaining the number of such periods in a frame. |
paul@0 | 261 | // Multiplying this result with the frame rate yields the pixel frequency. |
paul@0 | 262 | |
paul@0 | 263 | pclk = _panel->frame_rate * |
paul@0 | 264 | (_panel->width * multiplier + |
paul@0 | 265 | _panel->hsync + _panel->line_start + _panel->line_end) * |
paul@0 | 266 | (_panel->height + |
paul@0 | 267 | _panel->vsync + _panel->frame_start + _panel->frame_end); |
paul@0 | 268 | |
paul@0 | 269 | // STN panel adjustments. |
paul@0 | 270 | |
paul@0 | 271 | if (have_stn_panel()) |
paul@0 | 272 | { |
paul@0 | 273 | // Colour STN panels apparently need to be driven at three times the rate. |
paul@0 | 274 | |
paul@0 | 275 | if (have_colour_stn()) pclk = (pclk * 3); |
paul@0 | 276 | |
paul@0 | 277 | // Reduce the rate according to the width of the STN connection. |
paul@0 | 278 | // Since the pins setting employs log2(pins), a shift by this value is |
paul@0 | 279 | // equivalent to a division by the number of pins. |
paul@0 | 280 | |
paul@0 | 281 | pclk = pclk >> ((_panel->config & Config_stn_pins_mask) >> Jz4740_lcd_config_stn_pins); |
paul@0 | 282 | |
paul@0 | 283 | // Divide the rate by the number of panels. |
paul@0 | 284 | |
paul@0 | 285 | pclk /= get_panels(); |
paul@0 | 286 | } |
paul@0 | 287 | |
paul@0 | 288 | return pclk; |
paul@0 | 289 | } |
paul@0 | 290 | |
paul@0 | 291 | |
paul@0 | 292 | |
paul@0 | 293 | // Return the panel mode. |
paul@0 | 294 | |
paul@0 | 295 | uint32_t |
paul@0 | 296 | Lcd_jz4740_chip::_mode() |
paul@0 | 297 | { |
paul@0 | 298 | return _panel->config & Config_mode_mask; |
paul@0 | 299 | } |
paul@0 | 300 | |
paul@0 | 301 | // Return the number of panels available. |
paul@0 | 302 | |
paul@0 | 303 | int |
paul@0 | 304 | Lcd_jz4740_chip::get_panels() |
paul@0 | 305 | { |
paul@0 | 306 | uint32_t mode = _mode(); |
paul@0 | 307 | |
paul@0 | 308 | return (mode == Jz4740_lcd_mode_stn_dual_colour) || |
paul@0 | 309 | (mode == Jz4740_lcd_mode_stn_dual_mono) ? 2 : 1; |
paul@0 | 310 | } |
paul@0 | 311 | |
paul@0 | 312 | // Return whether the panel is STN. |
paul@0 | 313 | |
paul@0 | 314 | int |
paul@0 | 315 | Lcd_jz4740_chip::have_stn_panel() |
paul@0 | 316 | { |
paul@0 | 317 | uint32_t mode = _mode(); |
paul@0 | 318 | |
paul@0 | 319 | return ((mode == Jz4740_lcd_mode_stn_single_colour) || |
paul@0 | 320 | (mode == Jz4740_lcd_mode_stn_dual_colour) || |
paul@0 | 321 | (mode == Jz4740_lcd_mode_stn_single_mono) || |
paul@0 | 322 | (mode == Jz4740_lcd_mode_stn_dual_mono)); |
paul@0 | 323 | } |
paul@0 | 324 | |
paul@0 | 325 | // Return whether the panel is colour STN. |
paul@0 | 326 | |
paul@0 | 327 | int |
paul@0 | 328 | Lcd_jz4740_chip::have_colour_stn() |
paul@0 | 329 | { |
paul@0 | 330 | uint32_t mode = _mode(); |
paul@0 | 331 | |
paul@0 | 332 | return ((mode == Jz4740_lcd_mode_stn_single_colour) || |
paul@0 | 333 | (mode == Jz4740_lcd_mode_stn_dual_colour)); |
paul@0 | 334 | } |
paul@0 | 335 | |
paul@0 | 336 | // Return whether the panel is colour STN. |
paul@0 | 337 | |
paul@0 | 338 | int |
paul@0 | 339 | Lcd_jz4740_chip::have_serial_tft() |
paul@0 | 340 | { |
paul@0 | 341 | return _mode() == Jz4740_lcd_mode_tft_serial; |
paul@0 | 342 | } |
paul@0 | 343 | |
paul@0 | 344 | |
paul@0 | 345 | |
paul@0 | 346 | // Return the line memory size. |
paul@0 | 347 | |
paul@0 | 348 | l4_size_t |
paul@0 | 349 | Lcd_jz4740_chip::get_line_size() |
paul@0 | 350 | { |
paul@0 | 351 | // Lines must be aligned to a word boundary. |
paul@0 | 352 | |
paul@0 | 353 | return align((_panel->width * _panel->bpp) / 8, sizeof(uint32_t)); |
paul@0 | 354 | } |
paul@0 | 355 | |
paul@0 | 356 | // Return the screen memory size. |
paul@0 | 357 | |
paul@0 | 358 | l4_size_t |
paul@0 | 359 | Lcd_jz4740_chip::get_screen_size() |
paul@0 | 360 | { |
paul@0 | 361 | return get_line_size() * _panel->height; |
paul@0 | 362 | } |
paul@0 | 363 | |
paul@0 | 364 | // Return the aligned size for the DMA transfer. |
paul@0 | 365 | |
paul@0 | 366 | l4_size_t |
paul@0 | 367 | Lcd_jz4740_chip::get_aligned_size() |
paul@0 | 368 | { |
paul@0 | 369 | return align(get_screen_size(), _burst_size * sizeof(uint32_t)); |
paul@0 | 370 | } |
paul@0 | 371 | |
paul@0 | 372 | // Return the size of the palette. |
paul@0 | 373 | |
paul@0 | 374 | l4_size_t |
paul@0 | 375 | Lcd_jz4740_chip::get_palette_size() |
paul@0 | 376 | { |
paul@0 | 377 | // No palette for modes with more than eight bits per pixel. |
paul@0 | 378 | |
paul@0 | 379 | if (_panel->bpp > 8) return 0; |
paul@0 | 380 | |
paul@0 | 381 | // Get the size of a collection of two-byte entries, one per colour. |
paul@0 | 382 | |
paul@0 | 383 | return (1 << (_panel->bpp)) * sizeof(uint16_t); |
paul@0 | 384 | } |
paul@0 | 385 | |
paul@0 | 386 | // Return the aligned size of the palette for the DMA transfer. |
paul@0 | 387 | |
paul@0 | 388 | l4_size_t |
paul@0 | 389 | Lcd_jz4740_chip::get_aligned_palette_size() |
paul@0 | 390 | { |
paul@0 | 391 | return align(get_palette_size(), _burst_size * sizeof(uint32_t)); |
paul@0 | 392 | } |
paul@0 | 393 | |
paul@0 | 394 | // Return the total memory requirements of the framebuffers and palette. |
paul@0 | 395 | |
paul@0 | 396 | l4_size_t |
paul@0 | 397 | Lcd_jz4740_chip::get_total_size() |
paul@0 | 398 | { |
paul@0 | 399 | return get_aligned_size() * get_panels() + get_aligned_palette_size(); |
paul@0 | 400 | } |
paul@0 | 401 | |
paul@0 | 402 | // Return the total memory requirements of any DMA descriptors. |
paul@0 | 403 | |
paul@0 | 404 | l4_size_t |
paul@0 | 405 | Lcd_jz4740_chip::get_descriptors_size() |
paul@0 | 406 | { |
paul@0 | 407 | return 3 * sizeof(struct Jz4740_lcd_descriptor); |
paul@0 | 408 | } |
paul@0 | 409 | |
paul@0 | 410 | |
paul@0 | 411 | |
paul@0 | 412 | // Functions returning addresses of each data region. |
paul@0 | 413 | // The base parameter permits the retrieval of virtual or physical addresses. |
paul@0 | 414 | |
paul@0 | 415 | l4_addr_t |
paul@0 | 416 | Lcd_jz4740_chip::get_palette(l4_addr_t base) |
paul@0 | 417 | { |
paul@0 | 418 | // Use memory at the end of the allocated region for the palette. |
paul@0 | 419 | |
paul@0 | 420 | return base + (get_panels() * get_aligned_size()) - get_aligned_palette_size(); |
paul@0 | 421 | } |
paul@0 | 422 | |
paul@0 | 423 | l4_addr_t |
paul@0 | 424 | Lcd_jz4740_chip::get_framebuffer(int panel, l4_addr_t base) |
paul@0 | 425 | { |
paul@0 | 426 | // Framebuffers for panels are allocated at the start of the region. |
paul@0 | 427 | |
paul@0 | 428 | return base + (panel * get_aligned_size()); |
paul@0 | 429 | } |
paul@0 | 430 | |
paul@0 | 431 | |
paul@0 | 432 | |
paul@0 | 433 | // Palette initialisation. |
paul@0 | 434 | |
paul@0 | 435 | void |
paul@0 | 436 | Lcd_jz4740_chip::init_palette(l4_addr_t palette) |
paul@0 | 437 | { |
paul@0 | 438 | uint8_t colours = 1 << (_panel->bpp); |
paul@0 | 439 | uint16_t *entry = (uint16_t *) palette; |
paul@0 | 440 | uint16_t *end = entry + colours; |
paul@0 | 441 | uint8_t value = 0; |
paul@0 | 442 | |
paul@0 | 443 | while (entry < end) |
paul@0 | 444 | { |
paul@0 | 445 | switch (_panel->bpp) |
paul@0 | 446 | { |
paul@0 | 447 | case 4: |
paul@0 | 448 | *entry = rgb4_to_rgb16(value); |
paul@0 | 449 | break; |
paul@0 | 450 | |
paul@0 | 451 | case 8: |
paul@0 | 452 | *entry = rgb8_to_rgb16(value); |
paul@0 | 453 | break; |
paul@0 | 454 | |
paul@0 | 455 | default: |
paul@0 | 456 | break; |
paul@0 | 457 | } |
paul@0 | 458 | |
paul@0 | 459 | value++; |
paul@0 | 460 | entry++; |
paul@0 | 461 | } |
paul@0 | 462 | } |
paul@0 | 463 | |
paul@0 | 464 | |
paul@0 | 465 | |
paul@0 | 466 | // Return colour depth control value. |
paul@0 | 467 | // NOTE: Not supporting JZ4780 options. |
paul@0 | 468 | |
paul@0 | 469 | uint32_t |
paul@0 | 470 | Lcd_jz4740_chip::_control_bpp() |
paul@0 | 471 | { |
paul@0 | 472 | switch (_panel->bpp) |
paul@0 | 473 | { |
paul@0 | 474 | case 1: return Control_bpp_1bpp; |
paul@0 | 475 | case 2: return Control_bpp_2bpp; |
paul@0 | 476 | case 3 ... 4: return Control_bpp_4bpp; |
paul@0 | 477 | case 5 ... 8: return Control_bpp_8bpp; |
paul@0 | 478 | case 9 ... 15: return Control_bpp_15bpp | (Rgb_mode_555 << Control_rgb_mode); |
paul@0 | 479 | case 17 ... 18: return Control_bpp_18bpp; |
paul@0 | 480 | case 19 ... 32: return Control_bpp_24bpp; |
paul@0 | 481 | case 16: |
paul@0 | 482 | default: return Control_bpp_16bpp; |
paul@0 | 483 | } |
paul@0 | 484 | } |
paul@0 | 485 | |
paul@0 | 486 | // Return a panel-related control value. |
paul@0 | 487 | |
paul@0 | 488 | uint32_t |
paul@0 | 489 | Lcd_jz4740_chip::_control_panel() |
paul@0 | 490 | { |
paul@0 | 491 | if (have_stn_panel()) |
paul@0 | 492 | return _control_stn_frc(); |
paul@0 | 493 | else |
paul@0 | 494 | return 0; |
paul@0 | 495 | } |
paul@0 | 496 | |
paul@0 | 497 | // Return a STN-related control value. |
paul@0 | 498 | |
paul@0 | 499 | uint32_t |
paul@0 | 500 | Lcd_jz4740_chip::_control_stn_frc() |
paul@0 | 501 | { |
paul@0 | 502 | if (_panel->bpp <= 2) |
paul@0 | 503 | return Frc_greyscales_2; |
paul@0 | 504 | if (_panel->bpp <= 4) |
paul@0 | 505 | return Frc_greyscales_4; |
paul@0 | 506 | return Frc_greyscales_16; |
paul@0 | 507 | } |
paul@0 | 508 | |
paul@0 | 509 | // Return a transfer-related control value. |
paul@0 | 510 | |
paul@0 | 511 | uint32_t |
paul@0 | 512 | Lcd_jz4740_chip::_control_transfer() |
paul@0 | 513 | { |
paul@0 | 514 | uint32_t length; |
paul@0 | 515 | |
paul@0 | 516 | switch (_burst_size) |
paul@0 | 517 | { |
paul@0 | 518 | case 4: length = Burst_length_4; break; |
paul@0 | 519 | case 8: length = Burst_length_8; break; |
paul@0 | 520 | case 32: length = Burst_length_32; break; |
paul@0 | 521 | case 64: length = Burst_length_64; break; |
paul@0 | 522 | case 16: |
paul@0 | 523 | default: length = Burst_length_16; break; |
paul@0 | 524 | } |
paul@0 | 525 | |
paul@0 | 526 | return (length << Control_burst_length) | (1 << Control_out_underrun); |
paul@0 | 527 | } |
paul@0 | 528 | |
paul@0 | 529 | // STN panel-specific initialisation. |
paul@0 | 530 | |
paul@0 | 531 | void |
paul@0 | 532 | Lcd_jz4740_chip::_init_stn() |
paul@0 | 533 | { |
paul@0 | 534 | // Divide the height by the number of panels. |
paul@0 | 535 | |
paul@0 | 536 | uint32_t height = _panel->height / get_panels(); |
paul@0 | 537 | |
paul@0 | 538 | // Since the value is log2(pins), 1 << value yields the number of pins. |
paul@0 | 539 | |
paul@0 | 540 | int pins = 1 << ((_panel->config & Config_stn_pins_mask) >> Jz4740_lcd_config_stn_pins); |
paul@0 | 541 | |
paul@0 | 542 | // Round parameters up to a multiple of the number of pins. |
paul@0 | 543 | |
paul@0 | 544 | uint32_t hsync = align(_panel->hsync, pins); |
paul@0 | 545 | uint32_t line_start = align(_panel->line_start, pins); |
paul@0 | 546 | uint32_t line_end = align(_panel->line_end, pins); |
paul@0 | 547 | |
paul@0 | 548 | // Define the start and end positions of visible data on a line and in a frame. |
paul@0 | 549 | // Visible frame data is anchored at line zero, with the start region |
paul@0 | 550 | // preceding this line (and thus appearing at the end of the preceding frame). |
paul@0 | 551 | |
paul@0 | 552 | uint32_t line_start_pos = line_start; |
paul@0 | 553 | uint32_t line_end_pos = line_start_pos + _panel->width; |
paul@0 | 554 | uint32_t frame_start_pos = 0; |
paul@0 | 555 | uint32_t frame_end_pos = frame_start_pos + height; |
paul@0 | 556 | |
paul@0 | 557 | // Define sync pulse locations, with hsync occurring after the visible data. |
paul@0 | 558 | |
paul@0 | 559 | _regs[Lcd_hsync] = encode_pair(line_end_pos, line_end_pos + hsync); |
paul@0 | 560 | _regs[Lcd_vsync] = encode_pair(0, _panel->vsync); |
paul@0 | 561 | |
paul@0 | 562 | // Set the display area and limits. |
paul@0 | 563 | |
paul@0 | 564 | _regs[Vertical_area] = encode_pair(line_end_pos + hsync + line_end, |
paul@0 | 565 | frame_end_pos + _panel->vsync + _panel->frame_end + _panel->frame_start); |
paul@0 | 566 | |
paul@0 | 567 | _regs[Display_hlimits] = encode_pair(line_start_pos, line_end_pos); |
paul@0 | 568 | _regs[Display_vlimits] = encode_pair(frame_start_pos, frame_end_pos); |
paul@0 | 569 | |
paul@0 | 570 | // Set the AC bias signal. |
paul@0 | 571 | |
paul@0 | 572 | _regs[Lcd_ps] = encode_pair(0, _panel->frame_start + height + _panel->vsync + _panel->frame_end); |
paul@0 | 573 | } |
paul@0 | 574 | |
paul@0 | 575 | // TFT panel-specific initialisation. |
paul@0 | 576 | |
paul@0 | 577 | void |
paul@0 | 578 | Lcd_jz4740_chip::_init_tft() |
paul@0 | 579 | { |
paul@0 | 580 | // Define the start and end positions of visible data on a line and in a frame. |
paul@0 | 581 | |
paul@0 | 582 | uint32_t line_start_pos = _panel->line_start + _panel->hsync; |
paul@0 | 583 | uint32_t line_end_pos = line_start_pos + _panel->width; |
paul@0 | 584 | uint32_t frame_start_pos = _panel->frame_start + _panel->vsync; |
paul@0 | 585 | uint32_t frame_end_pos = frame_start_pos + _panel->height; |
paul@0 | 586 | |
paul@0 | 587 | // Define sync pulse locations, with pulses appearing before visible data. |
paul@0 | 588 | |
paul@0 | 589 | _regs[Lcd_hsync] = encode_pair(0, _panel->hsync); |
paul@0 | 590 | _regs[Lcd_vsync] = encode_pair(0, _panel->vsync); |
paul@0 | 591 | |
paul@0 | 592 | // Set the display area and limits. |
paul@0 | 593 | |
paul@0 | 594 | _regs[Vertical_area] = encode_pair(line_end_pos + _panel->line_end, |
paul@0 | 595 | frame_end_pos + _panel->frame_end); |
paul@0 | 596 | |
paul@0 | 597 | _regs[Display_hlimits] = encode_pair(line_start_pos, line_end_pos); |
paul@0 | 598 | _regs[Display_vlimits] = encode_pair(frame_start_pos, frame_end_pos); |
paul@0 | 599 | } |
paul@0 | 600 | |
paul@0 | 601 | // Initialise the panel. |
paul@0 | 602 | // NOTE: Only generic STN and TFT panels are supported. |
paul@0 | 603 | |
paul@0 | 604 | void |
paul@0 | 605 | Lcd_jz4740_chip::_init_panel() |
paul@0 | 606 | { |
paul@0 | 607 | if (have_stn_panel()) |
paul@0 | 608 | _init_stn(); |
paul@0 | 609 | else |
paul@0 | 610 | switch (_mode()) |
paul@0 | 611 | { |
paul@0 | 612 | case Jz4740_lcd_mode_tft_generic: |
paul@0 | 613 | case Jz4740_lcd_mode_tft_casio: |
paul@0 | 614 | case Jz4740_lcd_mode_tft_serial: _init_tft(); |
paul@0 | 615 | |
paul@0 | 616 | default: break; |
paul@0 | 617 | } |
paul@0 | 618 | } |
paul@0 | 619 | |
paul@0 | 620 | // Initialise a DMA descriptor. |
paul@0 | 621 | |
paul@0 | 622 | void |
paul@0 | 623 | Lcd_jz4740_chip::_set_descriptor(struct Jz4740_lcd_descriptor &desc, |
paul@0 | 624 | l4_addr_t source, l4_size_t size, |
paul@0 | 625 | struct Jz4740_lcd_descriptor *next, |
paul@0 | 626 | uint32_t flags) |
paul@0 | 627 | { |
paul@0 | 628 | // In the command, indicate the number of words from the source for transfer. |
paul@0 | 629 | |
paul@0 | 630 | desc.next = next; |
paul@0 | 631 | desc.source = source; |
paul@0 | 632 | desc.identifier = 0; |
paul@0 | 633 | desc.command = ((size / sizeof(uint32_t)) & Command_buffer_length_mask) | flags; |
paul@0 | 634 | } |
paul@0 | 635 | |
paul@0 | 636 | |
paul@0 | 637 | |
paul@0 | 638 | // Initialise the LCD controller with the memory, panel and framebuffer details. |
paul@0 | 639 | // Any palette must be initialised separately using get_palette and init_palette. |
paul@0 | 640 | |
paul@0 | 641 | void |
paul@0 | 642 | Lcd_jz4740_chip::config(struct Jz4740_lcd_descriptor *desc_vaddr, |
paul@0 | 643 | struct Jz4740_lcd_descriptor *desc_paddr, |
paul@0 | 644 | l4_addr_t fb_paddr) |
paul@0 | 645 | { |
paul@0 | 646 | int have_palette = (_panel->bpp <= 8); |
paul@0 | 647 | |
paul@0 | 648 | // Provide the first framebuffer descriptor in single and dual modes. |
paul@0 | 649 | // Flip back and forth between any palette and the framebuffer. |
paul@0 | 650 | |
paul@0 | 651 | _set_descriptor(desc_vaddr[0], get_framebuffer(0, fb_paddr), |
paul@0 | 652 | get_screen_size(), |
paul@0 | 653 | have_palette ? desc_paddr + 2 : desc_paddr); |
paul@0 | 654 | |
paul@0 | 655 | // Provide the second framebuffer descriptor only in dual-panel mode. |
paul@0 | 656 | // Only employ this descriptor in the second DMA channel. |
paul@0 | 657 | |
paul@0 | 658 | if (get_panels() == 2) |
paul@0 | 659 | _set_descriptor(desc_vaddr[1], get_framebuffer(1, fb_paddr), |
paul@0 | 660 | get_screen_size(), |
paul@0 | 661 | desc_paddr + 1); |
paul@0 | 662 | |
paul@0 | 663 | // Initialise palette descriptor details for lower colour depths. |
paul@0 | 664 | |
paul@0 | 665 | if (have_palette) |
paul@0 | 666 | _set_descriptor(desc_vaddr[2], get_palette(fb_paddr), |
paul@0 | 667 | get_palette_size(), |
paul@0 | 668 | desc_paddr, |
paul@0 | 669 | Command_palette_buffer); |
paul@0 | 670 | |
paul@0 | 671 | // Flush cached structure data. |
paul@0 | 672 | |
paul@0 | 673 | l4_cache_clean_data((unsigned long) desc_vaddr, |
paul@0 | 674 | (unsigned long) desc_vaddr + get_descriptors_size()); |
paul@0 | 675 | |
paul@0 | 676 | // Configure DMA by setting frame descriptor addresses. |
paul@0 | 677 | |
paul@0 | 678 | // Provide the palette descriptor address first, if employed. |
paul@0 | 679 | |
paul@0 | 680 | _regs[Desc_address_0] = (uint32_t) (have_palette ? desc_paddr + 2 : desc_paddr); |
paul@0 | 681 | |
paul@0 | 682 | // Provide a descriptor for the second DMA channel in dual-panel mode. |
paul@0 | 683 | |
paul@0 | 684 | if (get_panels() == 2) |
paul@0 | 685 | _regs[Desc_address_1] = (uint32_t) (desc_paddr + 1); |
paul@0 | 686 | |
paul@0 | 687 | // Initialise panel-related registers. |
paul@0 | 688 | |
paul@0 | 689 | _init_panel(); |
paul@0 | 690 | |
paul@0 | 691 | // Initialise the control and configuration registers. |
paul@0 | 692 | |
paul@0 | 693 | _regs[Lcd_control] = _control_panel() | _control_bpp() | _control_transfer(); |
paul@0 | 694 | _regs[Lcd_config] = _panel->config; |
paul@0 | 695 | } |
paul@0 | 696 | |
paul@0 | 697 | |
paul@0 | 698 | |
paul@0 | 699 | // C language interface functions. |
paul@0 | 700 | |
paul@0 | 701 | void * |
paul@0 | 702 | jz4740_lcd_init(l4_addr_t lcd_base, struct Jz4740_lcd_panel *panel) |
paul@0 | 703 | { |
paul@0 | 704 | return (void *) new Lcd_jz4740_chip(lcd_base, panel); |
paul@0 | 705 | } |
paul@0 | 706 | |
paul@0 | 707 | void |
paul@0 | 708 | jz4740_lcd_config(void *lcd, struct Jz4740_lcd_descriptor *desc_vaddr, |
paul@0 | 709 | struct Jz4740_lcd_descriptor *desc_paddr, |
paul@0 | 710 | l4_addr_t fb_paddr) |
paul@0 | 711 | { |
paul@0 | 712 | static_cast<Lcd_jz4740_chip *>(lcd)->config(desc_vaddr, desc_paddr, fb_paddr); |
paul@0 | 713 | } |
paul@0 | 714 | |
paul@0 | 715 | void |
paul@0 | 716 | jz4740_lcd_disable(void *lcd) |
paul@0 | 717 | { |
paul@0 | 718 | static_cast<Lcd_jz4740_chip *>(lcd)->disable(); |
paul@0 | 719 | } |
paul@0 | 720 | |
paul@0 | 721 | void |
paul@0 | 722 | jz4740_lcd_disable_quick(void *lcd) |
paul@0 | 723 | { |
paul@0 | 724 | static_cast<Lcd_jz4740_chip *>(lcd)->disable_quick(); |
paul@0 | 725 | } |
paul@0 | 726 | |
paul@0 | 727 | void |
paul@0 | 728 | jz4740_lcd_enable(void *lcd) |
paul@0 | 729 | { |
paul@0 | 730 | static_cast<Lcd_jz4740_chip *>(lcd)->enable(); |
paul@0 | 731 | } |
paul@0 | 732 | |
paul@0 | 733 | int |
paul@0 | 734 | jz4740_lcd_get_pixel_clock(void *lcd) |
paul@0 | 735 | { |
paul@0 | 736 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_pixel_clock(); |
paul@0 | 737 | } |
paul@0 | 738 | |
paul@0 | 739 | l4_addr_t |
paul@0 | 740 | jz4740_lcd_get_palette(void *lcd, l4_addr_t base) |
paul@0 | 741 | { |
paul@0 | 742 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_palette(base); |
paul@0 | 743 | } |
paul@0 | 744 | |
paul@0 | 745 | void |
paul@0 | 746 | jz4740_lcd_init_palette(void *lcd, l4_addr_t palette) |
paul@0 | 747 | { |
paul@0 | 748 | static_cast<Lcd_jz4740_chip *>(lcd)->init_palette(palette); |
paul@0 | 749 | } |