| paul@0 | 1 | /* |
| paul@0 | 2 | * U-Boot and jz4740 LCD controller definitions. |
| paul@0 | 3 | * |
| paul@0 | 4 | * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| paul@0 | 5 | * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. |
| paul@0 | 6 | * Copyright (C) 2009 Qi Hardware Inc. |
| paul@0 | 7 | * Author: Xiangfu Liu <xiangfu@sharism.cc> |
| paul@0 | 8 | * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> |
| paul@0 | 9 | * Copyright (C) 2015, 2016, 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
| paul@0 | 10 | * |
| paul@0 | 11 | * This program is free software; you can redistribute it and/or |
| paul@0 | 12 | * modify it under the terms of the GNU General Public License as |
| paul@0 | 13 | * published by the Free Software Foundation; either version 2 of |
| paul@0 | 14 | * the License, or (at your option) any later version. |
| paul@0 | 15 | * |
| paul@0 | 16 | * This program is distributed in the hope that it will be useful, |
| paul@0 | 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| paul@0 | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| paul@0 | 19 | * GNU General Public License for more details. |
| paul@0 | 20 | * |
| paul@0 | 21 | * You should have received a copy of the GNU General Public License |
| paul@0 | 22 | * along with this program; if not, write to the Free Software |
| paul@0 | 23 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| paul@0 | 24 | * Boston, MA 02110-1301, USA |
| paul@0 | 25 | */ |
| paul@0 | 26 | |
| paul@0 | 27 | #ifndef __JZLCD_H__ |
| paul@0 | 28 | #define __JZLCD_H__ |
| paul@0 | 29 | |
| paul@0 | 30 | #include <stdint.h> |
| paul@0 | 31 | |
| paul@0 | 32 | /* Framebuffer characteristics. */ |
| paul@0 | 33 | |
| paul@0 | 34 | struct jzfb_info { |
| paul@0 | 35 | uint32_t cfg; /* panel mode and pin usage etc. */ |
| paul@0 | 36 | uint32_t w; /* display width in pixels */ |
| paul@0 | 37 | uint32_t h; /* display height in pixels */ |
| paul@0 | 38 | uint32_t bpp; /* bits per pixel */ |
| paul@0 | 39 | uint32_t fclk; /* frame clock */ |
| paul@0 | 40 | uint32_t hsw; /* hsync width, in pixel clock */ |
| paul@0 | 41 | uint32_t vsw; /* vsync width, in line count */ |
| paul@0 | 42 | uint32_t elw; /* end of line, in pixel clock */ |
| paul@0 | 43 | uint32_t blw; /* begin of line, in pixel clock */ |
| paul@0 | 44 | uint32_t efw; /* end of frame, in line count */ |
| paul@0 | 45 | uint32_t bfw; /* begin of frame, in line count */ |
| paul@0 | 46 | }; |
| paul@0 | 47 | |
| paul@0 | 48 | /* LCD controller stucture for jz4740. */ |
| paul@0 | 49 | |
| paul@0 | 50 | struct jz_fb_dma_descriptor { |
| paul@0 | 51 | struct jz_fb_dma_descriptor *fdadr; /* frame descriptor address register */ |
| paul@0 | 52 | uint32_t fsadr; /* frame source address register */ |
| paul@0 | 53 | uint32_t fidr; /* frame identifier register */ |
| paul@0 | 54 | uint32_t ldcmd; /* command register */ |
| paul@0 | 55 | }; |
| paul@0 | 56 | |
| paul@0 | 57 | /* Display characteristics and memory resources. */ |
| paul@0 | 58 | |
| paul@0 | 59 | typedef struct vidinfo { |
| paul@0 | 60 | struct jzfb_info *jz_fb; /* framebuffer and panel properties */ |
| paul@0 | 61 | void *lcd; /* address of LCD controller registers */ |
| paul@0 | 62 | } vidinfo_t; |
| paul@0 | 63 | |
| paul@0 | 64 | |
| paul@0 | 65 | |
| paul@0 | 66 | /* Public functions. */ |
| paul@0 | 67 | |
| paul@0 | 68 | uint32_t jz4740_lcd_get_aligned_size(vidinfo_t *vid); |
| paul@0 | 69 | uint32_t jz4740_lcd_get_descriptors_size(vidinfo_t *vid); |
| paul@0 | 70 | uint32_t jz4740_lcd_get_line_size(vidinfo_t *vid); |
| paul@0 | 71 | uint32_t jz4740_lcd_get_screen_size(vidinfo_t *vid); |
| paul@0 | 72 | uint32_t jz4740_lcd_get_pixel_clock(vidinfo_t *vid); |
| paul@0 | 73 | |
| paul@0 | 74 | void jz4740_lcd_set_base(vidinfo_t *vid, void *lcd_base); |
| paul@0 | 75 | |
| paul@0 | 76 | void jz4740_lcd_ctrl_init( |
| paul@0 | 77 | struct jz_fb_dma_descriptor *desc_vaddr, |
| paul@0 | 78 | struct jz_fb_dma_descriptor *desc_paddr, |
| paul@0 | 79 | void *fb_vaddr, void *fb_paddr, |
| paul@0 | 80 | vidinfo_t *vid); |
| paul@0 | 81 | |
| paul@0 | 82 | void jz4740_lcd_hw_init(vidinfo_t *vid); |
| paul@0 | 83 | void jz4740_lcd_set_bpp(uint8_t bpp, vidinfo_t *vid); |
| paul@0 | 84 | void jz4740_lcd_enable(vidinfo_t *vid); |
| paul@0 | 85 | void jz4740_lcd_disable(vidinfo_t *vid); |
| paul@0 | 86 | void jz4740_lcd_quick_disable(vidinfo_t *vid); |
| paul@0 | 87 | |
| paul@0 | 88 | |
| paul@0 | 89 | |
| paul@0 | 90 | /* Alignment/rounding macros. */ |
| paul@0 | 91 | |
| paul@0 | 92 | #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) |
| paul@0 | 93 | #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) |
| paul@0 | 94 | |
| paul@0 | 95 | /* Display device mode select (LCD_CFG.MODE). */ |
| paul@0 | 96 | |
| paul@0 | 97 | #define MODE_MASK 0x0f |
| paul@0 | 98 | #define MODE_TFT_GEN 0x00 |
| paul@0 | 99 | #define MODE_TFT_SHARP 0x01 |
| paul@0 | 100 | #define MODE_TFT_CASIO 0x02 |
| paul@0 | 101 | #define MODE_TFT_SAMSUNG 0x03 |
| paul@0 | 102 | #define MODE_CCIR656_NONINT 0x04 |
| paul@0 | 103 | #define MODE_CCIR656_INT 0x05 |
| paul@0 | 104 | #define MODE_STN_COLOR_SINGLE 0x08 |
| paul@0 | 105 | #define MODE_STN_MONO_SINGLE 0x09 |
| paul@0 | 106 | #define MODE_STN_COLOR_DUAL 0x0a |
| paul@0 | 107 | #define MODE_STN_MONO_DUAL 0x0b |
| paul@0 | 108 | #define MODE_8BIT_SERIAL_TFT 0x0c |
| paul@0 | 109 | |
| paul@0 | 110 | /* 16-bit or 18-bit TFT panel selection (LCD_CFG.18/16). */ |
| paul@0 | 111 | |
| paul@0 | 112 | #define MODE_TFT_18BIT (1<<7) |
| paul@0 | 113 | |
| paul@0 | 114 | /* STN pin utilisation (LCD_CFG.PDW). */ |
| paul@0 | 115 | |
| paul@0 | 116 | #define STN_DAT_PIN1 (0x00 << 4) |
| paul@0 | 117 | #define STN_DAT_PIN2 (0x01 << 4) |
| paul@0 | 118 | #define STN_DAT_PIN4 (0x02 << 4) |
| paul@0 | 119 | #define STN_DAT_PIN8 (0x03 << 4) |
| paul@0 | 120 | #define STN_DAT_PINMASK STN_DAT_PIN8 |
| paul@0 | 121 | |
| paul@0 | 122 | /* Pin reset states (LCD_CFG). */ |
| paul@0 | 123 | |
| paul@0 | 124 | #define STFT_PSHI (1 << 15) |
| paul@0 | 125 | #define STFT_CLSHI (1 << 14) |
| paul@0 | 126 | #define STFT_SPLHI (1 << 13) |
| paul@0 | 127 | #define STFT_REVHI (1 << 12) |
| paul@0 | 128 | |
| paul@0 | 129 | /* Sync direction (LCD_CFG.SYNDIR). */ |
| paul@0 | 130 | |
| paul@0 | 131 | #define SYNC_MASTER (0 << 16) |
| paul@0 | 132 | #define SYNC_SLAVE (1 << 16) |
| paul@0 | 133 | |
| paul@0 | 134 | /* Data enable polarity (LCD_CFG.DEP). */ |
| paul@0 | 135 | |
| paul@0 | 136 | #define DE_P (0 << 9) |
| paul@0 | 137 | #define DE_N (1 << 9) |
| paul@0 | 138 | |
| paul@0 | 139 | /* Pixel clock polarity (LCD_CFG.PCP). */ |
| paul@0 | 140 | |
| paul@0 | 141 | #define PCLK_P (0 << 10) |
| paul@0 | 142 | #define PCLK_N (1 << 10) |
| paul@0 | 143 | |
| paul@0 | 144 | /* Horizontal sync polarity (LCD_CFG.HSP). */ |
| paul@0 | 145 | |
| paul@0 | 146 | #define HSYNC_P (0 << 11) |
| paul@0 | 147 | #define HSYNC_N (1 << 11) |
| paul@0 | 148 | |
| paul@0 | 149 | /* Vertical sync polarity (LCD_CFG.VSP). */ |
| paul@0 | 150 | |
| paul@0 | 151 | #define VSYNC_P (0 << 8) |
| paul@0 | 152 | #define VSYNC_N (1 << 8) |
| paul@0 | 153 | |
| paul@0 | 154 | /* Inverse output data (LCD_CFG.INVDAT). */ |
| paul@0 | 155 | |
| paul@0 | 156 | #define DATA_NORMAL (0 << 17) |
| paul@0 | 157 | #define DATA_INVERSE (1 << 17) |
| paul@0 | 158 | |
| paul@0 | 159 | /* Register offsets. */ |
| paul@0 | 160 | |
| paul@0 | 161 | #define LCD_CFG 0x00 /* LCD Configure Register */ |
| paul@0 | 162 | #define LCD_VSYNC 0x04 /* Vertical Synchronize Register */ |
| paul@0 | 163 | #define LCD_HSYNC 0x08 /* Horizontal Synchronize Register */ |
| paul@0 | 164 | #define LCD_VAT 0x0c /* Virtual Area Setting Register */ |
| paul@0 | 165 | #define LCD_DAH 0x10 /* Display Area Horizontal Start/End Point */ |
| paul@0 | 166 | #define LCD_DAV 0x14 /* Display Area Vertical Start/End Point */ |
| paul@0 | 167 | #define LCD_PS 0x18 /* PS Signal Setting */ |
| paul@0 | 168 | #define LCD_CLS 0x1c /* CLS Signal Setting */ |
| paul@0 | 169 | #define LCD_SPL 0x20 /* SPL Signal Setting */ |
| paul@0 | 170 | #define LCD_REV 0x24 /* REV Signal Setting */ |
| paul@0 | 171 | #define LCD_CTRL 0x30 /* LCD Control Register */ |
| paul@0 | 172 | #define LCD_STATE 0x34 /* LCD Status Register */ |
| paul@0 | 173 | #define LCD_IID 0x38 /* Interrupt ID Register */ |
| paul@0 | 174 | #define LCD_DA0 0x40 /* Descriptor Address Register 0 */ |
| paul@0 | 175 | #define LCD_SA0 0x44 /* Source Address Register 0 */ |
| paul@0 | 176 | #define LCD_FID0 0x48 /* Frame ID Register 0 */ |
| paul@0 | 177 | #define LCD_CMD0 0x4c /* DMA Command Register 0 */ |
| paul@0 | 178 | #define LCD_DA1 0x50 /* Descriptor Address Register 1 */ |
| paul@0 | 179 | #define LCD_SA1 0x54 /* Source Address Register 1 */ |
| paul@0 | 180 | #define LCD_FID1 0x58 /* Frame ID Register 1 */ |
| paul@0 | 181 | #define LCD_CMD1 0x5c /* DMA Command Register 1 */ |
| paul@0 | 182 | |
| paul@0 | 183 | /* Burst length selection (LCD_CTRL.BST). */ |
| paul@0 | 184 | |
| paul@0 | 185 | #define LCD_CTRL_BST_MASK (0x03 << 28) |
| paul@0 | 186 | #define LCD_CTRL_BST_4 (0 << 28) /* 4-word */ |
| paul@0 | 187 | #define LCD_CTRL_BST_8 (1 << 28) /* 8-word */ |
| paul@0 | 188 | #define LCD_CTRL_BST_16 (2 << 28) /* 16-word */ |
| paul@0 | 189 | |
| paul@0 | 190 | /* RGB mode (LCD_CTRL.RGB). */ |
| paul@0 | 191 | |
| paul@0 | 192 | #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ |
| paul@0 | 193 | #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ |
| paul@0 | 194 | |
| paul@0 | 195 | /* Output FIFO underrun protection (LCD_CTRL.OFUP). */ |
| paul@0 | 196 | |
| paul@0 | 197 | #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ |
| paul@0 | 198 | |
| paul@0 | 199 | /* STN FRC algorithm selection (LCD_CTRL.FRC). */ |
| paul@0 | 200 | |
| paul@0 | 201 | #define LCD_CTRL_FRC_16 (0 << 24) /* 16 grayscale */ |
| paul@0 | 202 | #define LCD_CTRL_FRC_4 (1 << 24) /* 4 grayscale */ |
| paul@0 | 203 | #define LCD_CTRL_FRC_2 (2 << 24) /* 2 grayscale */ |
| paul@0 | 204 | #define LCD_CTRL_FRC_MASK (0x03 << 24) |
| paul@0 | 205 | |
| paul@0 | 206 | /* Load palette delay counter (LCD_CTRL.PDD) */ |
| paul@0 | 207 | |
| paul@0 | 208 | #define LCD_CTRL_PDD_MASK (0xff << 16) |
| paul@0 | 209 | |
| paul@0 | 210 | #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ |
| paul@0 | 211 | #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ |
| paul@0 | 212 | #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ |
| paul@0 | 213 | #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ |
| paul@0 | 214 | #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ |
| paul@0 | 215 | #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ |
| paul@0 | 216 | #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ |
| paul@0 | 217 | #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ |
| paul@0 | 218 | #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ |
| paul@0 | 219 | #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ |
| paul@0 | 220 | #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ |
| paul@0 | 221 | |
| paul@0 | 222 | /* Bits per pixel (LCD_CTRL.BPP). */ |
| paul@0 | 223 | |
| paul@0 | 224 | #define LCD_CTRL_BPP_1 0 /* 1 bpp */ |
| paul@0 | 225 | #define LCD_CTRL_BPP_2 1 /* 2 bpp */ |
| paul@0 | 226 | #define LCD_CTRL_BPP_4 2 /* 4 bpp */ |
| paul@0 | 227 | #define LCD_CTRL_BPP_8 3 /* 8 bpp */ |
| paul@0 | 228 | #define LCD_CTRL_BPP_16 4 /* 15/16 bpp */ |
| paul@0 | 229 | #define LCD_CTRL_BPP_18_24 5 /* 18/24/32 bpp */ |
| paul@0 | 230 | #define LCD_CTRL_BPP_MASK 0x07 |
| paul@0 | 231 | |
| paul@0 | 232 | /* Palette buffer (LCD_CMDx.PAL). */ |
| paul@0 | 233 | |
| paul@0 | 234 | #define LCD_CMD_PAL (1 << 28) |
| paul@0 | 235 | |
| paul@0 | 236 | #endif /* __JZLCD_H__ */ |
