paul@237 | 1 | /* |
paul@237 | 2 | * Real-time clock support. |
paul@237 | 3 | * |
paul@237 | 4 | * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> |
paul@237 | 5 | * |
paul@237 | 6 | * This program is free software; you can redistribute it and/or |
paul@237 | 7 | * modify it under the terms of the GNU General Public License as |
paul@237 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@237 | 9 | * the License, or (at your option) any later version. |
paul@237 | 10 | * |
paul@237 | 11 | * This program is distributed in the hope that it will be useful, |
paul@237 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@237 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@237 | 14 | * GNU General Public License for more details. |
paul@237 | 15 | * |
paul@237 | 16 | * You should have received a copy of the GNU General Public License |
paul@237 | 17 | * along with this program; if not, write to the Free Software |
paul@237 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@237 | 19 | * Boston, MA 02110-1301, USA |
paul@237 | 20 | */ |
paul@237 | 21 | |
paul@237 | 22 | #include <l4/devices/hw_mmio_register_block.h> |
paul@237 | 23 | #include "rtc-x1600.h" |
paul@237 | 24 | |
paul@237 | 25 | |
paul@237 | 26 | |
paul@237 | 27 | // Register locations. |
paul@237 | 28 | |
paul@237 | 29 | enum Regs : unsigned |
paul@237 | 30 | { |
paul@237 | 31 | Rtc_control = 0x000, // RTCCR |
paul@237 | 32 | Rtc_seconds = 0x004, // RTCSR |
paul@237 | 33 | Rtc_alarm_seconds = 0x008, // RTCSAR |
paul@237 | 34 | Rtc_regulator = 0x00c, // RTCGR |
paul@237 | 35 | |
paul@237 | 36 | Hibernate_control = 0x020, // HCR |
paul@237 | 37 | Hibernate_wakeup_filter_counter = 0x024, // HWFCR |
paul@237 | 38 | Hibernate_reset_counter = 0x028, // HRCR |
paul@237 | 39 | Hibernate_wakeup_control = 0x02c, // HWCR |
paul@237 | 40 | Hibernate_wakeup_status = 0x030, // HWRSR |
paul@237 | 41 | Hibernate_scratch_pattern = 0x034, // HSPR |
paul@237 | 42 | Hibernate_write_enable_pattern = 0x03c, // WENR |
paul@237 | 43 | Hibernate_wakeup_pin_configure = 0x048, // WKUPPINCR |
paul@237 | 44 | }; |
paul@237 | 45 | |
paul@249 | 46 | // Field definitions. |
paul@237 | 47 | |
paul@237 | 48 | enum Control_bits : unsigned |
paul@237 | 49 | { |
paul@237 | 50 | Control_write_ready = 0x80, // WRDY |
paul@237 | 51 | Control_1Hz = 0x40, // 1HZ |
paul@237 | 52 | Control_1Hz_irq_enable = 0x20, // 1HZIE |
paul@237 | 53 | Control_alarm = 0x10, // AF |
paul@237 | 54 | Control_alarm_irq_enable = 0x08, // AIE |
paul@237 | 55 | Control_alarm_enable = 0x04, // AE |
paul@237 | 56 | Control_rtc_enable = 0x01, // RTCE |
paul@237 | 57 | }; |
paul@237 | 58 | |
paul@237 | 59 | enum Regulator_bits : unsigned |
paul@237 | 60 | { |
paul@237 | 61 | Regulator_lock = 0x80000000, // LOCK |
paul@237 | 62 | Regulator_adjust_count_mask = 0x03ff0000, // ADJC |
paul@237 | 63 | Regulator_1Hz_cycle_count_mask = 0x0000ffff, // NC1HZ |
paul@237 | 64 | }; |
paul@237 | 65 | |
paul@237 | 66 | enum Regulator_limits : unsigned |
paul@237 | 67 | { |
paul@237 | 68 | Regulator_adjust_count_limit = 0x03ff, // ADJC |
paul@237 | 69 | Regulator_1Hz_cycle_count_limit = 0xffff, // NC1HZ |
paul@237 | 70 | }; |
paul@237 | 71 | |
paul@237 | 72 | enum Regulator_shifts : unsigned |
paul@237 | 73 | { |
paul@237 | 74 | Regulator_adjust_count_shift = 16, // ADJC |
paul@237 | 75 | Regulator_1Hz_cycle_count_shift = 0, // NC1HZ |
paul@237 | 76 | }; |
paul@237 | 77 | |
paul@237 | 78 | enum Hibernate_control_bits : unsigned |
paul@237 | 79 | { |
paul@237 | 80 | Hibernate_power_down = 0x01, // PD |
paul@237 | 81 | }; |
paul@237 | 82 | |
paul@237 | 83 | enum Hibernate_wakeup_filter_counter_bits : unsigned |
paul@237 | 84 | { |
paul@237 | 85 | Wakeup_minimum_time_mask = 0xffe0, // HWFCR |
paul@237 | 86 | }; |
paul@237 | 87 | |
paul@237 | 88 | enum Hibernate_reset_counter_bits : unsigned |
paul@237 | 89 | { |
paul@237 | 90 | Reset_assert_time_mask = 0x7800, // HRCR |
paul@237 | 91 | }; |
paul@237 | 92 | |
paul@237 | 93 | enum Hibernate_wakeup_control_bits : unsigned |
paul@237 | 94 | { |
paul@237 | 95 | Power_detect_enable_mask = 0xfffffff8, // EPDET |
paul@237 | 96 | Rtc_alarm_wakeup_enable = 0x00000001, // EALM |
paul@237 | 97 | }; |
paul@237 | 98 | |
paul@237 | 99 | enum Hibernate_wakeup_status_bits : unsigned |
paul@237 | 100 | { |
paul@237 | 101 | Accident_power_down = 0x0100, // APD |
paul@237 | 102 | Hibernate_reset = 0x0020, // HR |
paul@237 | 103 | Pad_pin_reset = 0x0010, // PPR |
paul@237 | 104 | Wakeup_pin_status = 0x0002, // PIN |
paul@237 | 105 | Rtc_alarm_status = 0x0001, // ALM |
paul@237 | 106 | }; |
paul@237 | 107 | |
paul@237 | 108 | enum Hibernate_write_enable_pattern_bits : unsigned |
paul@237 | 109 | { |
paul@237 | 110 | Write_enable_status = 0x80000000, // WEN |
paul@237 | 111 | Write_enable_pattern_mask = 0x0000ffff, // WENPAT |
paul@237 | 112 | Write_enable_pattern = 0x0000a55a, // WENPAT |
paul@237 | 113 | }; |
paul@237 | 114 | |
paul@237 | 115 | enum Hibernate_wakeup_pin_configure_bits : unsigned |
paul@237 | 116 | { |
paul@237 | 117 | Rtc_oscillator_test_enable = 0x00080000, // OSC_TE |
paul@237 | 118 | Oscillator_xtclk_rtclk = 0x00040000, // OSC_RETON |
paul@237 | 119 | Oscillator_xtclk_low = 0x00000000, // OSC_RETON |
paul@237 | 120 | Rtc_internal_oscillator_enable = 0x00010000, // OSC_EN |
paul@237 | 121 | Wakeup_pin_extended_press_mask = 0x000000f0, // P_JUD_LEN |
paul@237 | 122 | Wakeup_pin_extended_press_enable = 0x0000000f, // P_RST_LEN |
paul@237 | 123 | }; |
paul@237 | 124 | |
paul@237 | 125 | |
paul@237 | 126 | |
paul@237 | 127 | // Peripheral abstraction. |
paul@237 | 128 | |
paul@240 | 129 | Rtc_x1600_chip::Rtc_x1600_chip(l4_addr_t addr, Cpm_x1600_chip *cpm) |
paul@240 | 130 | : _cpm(cpm) |
paul@237 | 131 | { |
paul@237 | 132 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@237 | 133 | } |
paul@237 | 134 | |
paul@237 | 135 | uint32_t |
paul@237 | 136 | Rtc_x1600_chip::read_checked(unsigned reg) |
paul@237 | 137 | { |
paul@237 | 138 | uint32_t last, current; |
paul@237 | 139 | |
paul@237 | 140 | wait(); |
paul@237 | 141 | last = _regs[reg]; |
paul@237 | 142 | |
paul@237 | 143 | while (1) |
paul@237 | 144 | { |
paul@237 | 145 | wait(); |
paul@237 | 146 | current = _regs[reg]; |
paul@237 | 147 | |
paul@237 | 148 | if (current == last) |
paul@237 | 149 | return current; |
paul@237 | 150 | else |
paul@237 | 151 | last = current; |
paul@237 | 152 | } |
paul@237 | 153 | } |
paul@237 | 154 | |
paul@237 | 155 | void |
paul@237 | 156 | Rtc_x1600_chip::wait() |
paul@237 | 157 | { |
paul@237 | 158 | while (!(_regs[Rtc_control] & Control_write_ready)); |
paul@237 | 159 | } |
paul@237 | 160 | |
paul@237 | 161 | void |
paul@237 | 162 | Rtc_x1600_chip::write_enable() |
paul@237 | 163 | { |
paul@237 | 164 | wait(); |
paul@237 | 165 | _regs[Hibernate_write_enable_pattern] = Write_enable_pattern; |
paul@237 | 166 | |
paul@237 | 167 | while (!(_regs[Hibernate_write_enable_pattern] & Write_enable_status)); |
paul@237 | 168 | |
paul@237 | 169 | wait(); |
paul@237 | 170 | } |
paul@237 | 171 | |
paul@237 | 172 | void |
paul@237 | 173 | Rtc_x1600_chip::disable() |
paul@237 | 174 | { |
paul@237 | 175 | write_enable(); |
paul@237 | 176 | _regs[Rtc_control] = _regs[Rtc_control] & ~Control_rtc_enable; |
paul@237 | 177 | } |
paul@237 | 178 | |
paul@237 | 179 | void |
paul@237 | 180 | Rtc_x1600_chip::enable() |
paul@237 | 181 | { |
paul@237 | 182 | write_enable(); |
paul@237 | 183 | _regs[Rtc_control] = _regs[Rtc_control] | Control_rtc_enable; |
paul@237 | 184 | } |
paul@237 | 185 | |
paul@237 | 186 | void |
paul@237 | 187 | Rtc_x1600_chip::alarm_disable() |
paul@237 | 188 | { |
paul@237 | 189 | write_enable(); |
paul@237 | 190 | _regs[Rtc_control] = _regs[Rtc_control] & ~Control_alarm_enable; |
paul@237 | 191 | } |
paul@237 | 192 | |
paul@237 | 193 | void |
paul@237 | 194 | Rtc_x1600_chip::alarm_enable() |
paul@237 | 195 | { |
paul@237 | 196 | write_enable(); |
paul@238 | 197 | _regs[Rtc_control] = (_regs[Rtc_control] & ~Control_alarm) | Control_alarm_enable; |
paul@238 | 198 | } |
paul@238 | 199 | |
paul@238 | 200 | void |
paul@238 | 201 | Rtc_x1600_chip::wakeup_alarm_disable() |
paul@238 | 202 | { |
paul@238 | 203 | write_enable(); |
paul@238 | 204 | _regs[Hibernate_wakeup_control] = _regs[Hibernate_wakeup_control] & ~Rtc_alarm_wakeup_enable; |
paul@238 | 205 | } |
paul@238 | 206 | |
paul@238 | 207 | void |
paul@238 | 208 | Rtc_x1600_chip::wakeup_alarm_enable() |
paul@238 | 209 | { |
paul@238 | 210 | write_enable(); |
paul@238 | 211 | _regs[Hibernate_wakeup_control] = _regs[Hibernate_wakeup_control] | Rtc_alarm_wakeup_enable; |
paul@237 | 212 | } |
paul@237 | 213 | |
paul@237 | 214 | uint32_t |
paul@237 | 215 | Rtc_x1600_chip::get_seconds() |
paul@237 | 216 | { |
paul@237 | 217 | return read_checked(Rtc_seconds); |
paul@237 | 218 | } |
paul@237 | 219 | |
paul@237 | 220 | void |
paul@237 | 221 | Rtc_x1600_chip::set_seconds(uint32_t seconds) |
paul@237 | 222 | { |
paul@237 | 223 | write_enable(); |
paul@237 | 224 | _regs[Rtc_seconds] = seconds; |
paul@237 | 225 | } |
paul@237 | 226 | |
paul@237 | 227 | uint32_t |
paul@237 | 228 | Rtc_x1600_chip::get_alarm_seconds() |
paul@237 | 229 | { |
paul@237 | 230 | return read_checked(Rtc_alarm_seconds); |
paul@237 | 231 | } |
paul@237 | 232 | |
paul@237 | 233 | void |
paul@237 | 234 | Rtc_x1600_chip::set_alarm_seconds(uint32_t seconds) |
paul@237 | 235 | { |
paul@237 | 236 | write_enable(); |
paul@237 | 237 | _regs[Rtc_alarm_seconds] = seconds; |
paul@237 | 238 | } |
paul@237 | 239 | |
paul@237 | 240 | void |
paul@237 | 241 | Rtc_x1600_chip::set_regulator(uint32_t base, uint32_t adjustment) |
paul@237 | 242 | { |
paul@237 | 243 | base = base ? base - 1 : 0; |
paul@237 | 244 | adjustment = adjustment ? adjustment - 1 : 0; |
paul@237 | 245 | |
paul@237 | 246 | if (base > Regulator_1Hz_cycle_count_limit) |
paul@237 | 247 | base = Regulator_1Hz_cycle_count_limit; |
paul@237 | 248 | |
paul@237 | 249 | if (adjustment > Regulator_adjust_count_limit) |
paul@237 | 250 | adjustment = Regulator_adjust_count_limit; |
paul@237 | 251 | |
paul@237 | 252 | write_enable(); |
paul@237 | 253 | _regs[Rtc_regulator] = (base << Regulator_1Hz_cycle_count_shift) | |
paul@237 | 254 | (adjustment << Regulator_adjust_count_shift); |
paul@237 | 255 | } |
paul@237 | 256 | |
paul@237 | 257 | void |
paul@242 | 258 | Rtc_x1600_chip::_power_down() |
paul@237 | 259 | { |
paul@240 | 260 | /* Set CPU frequency to L2 cache frequency before powering down. This is |
paul@240 | 261 | apparently necessary according to the X1600 manual. */ |
paul@240 | 262 | |
paul@240 | 263 | if (_cpm != NULL) |
paul@240 | 264 | _cpm->set_frequency(Clock_cpu, _cpm->get_frequency(Clock_l2cache)); |
paul@240 | 265 | |
paul@237 | 266 | write_enable(); |
paul@237 | 267 | _regs[Hibernate_control] = _regs[Hibernate_control] | Hibernate_power_down; |
paul@237 | 268 | } |
paul@237 | 269 | |
paul@242 | 270 | void |
paul@242 | 271 | Rtc_x1600_chip::hibernate() |
paul@242 | 272 | { |
paul@242 | 273 | alarm_enable(); |
paul@242 | 274 | wakeup_alarm_enable(); |
paul@242 | 275 | _power_down(); |
paul@242 | 276 | } |
paul@242 | 277 | |
paul@242 | 278 | void |
paul@242 | 279 | Rtc_x1600_chip::power_down() |
paul@242 | 280 | { |
paul@242 | 281 | wakeup_alarm_disable(); |
paul@242 | 282 | _power_down(); |
paul@242 | 283 | } |
paul@242 | 284 | |
paul@237 | 285 | |
paul@237 | 286 | |
paul@237 | 287 | // C language interface functions. |
paul@237 | 288 | |
paul@237 | 289 | void |
paul@240 | 290 | *x1600_rtc_init(l4_addr_t rtc_base, void *cpm) |
paul@237 | 291 | { |
paul@240 | 292 | return (void *) new Rtc_x1600_chip(rtc_base, static_cast<Cpm_x1600_chip *>(cpm)); |
paul@237 | 293 | } |
paul@237 | 294 | |
paul@237 | 295 | void x1600_rtc_disable(void *rtc) |
paul@237 | 296 | { |
paul@237 | 297 | static_cast<Rtc_x1600_chip *>(rtc)->disable(); |
paul@237 | 298 | } |
paul@237 | 299 | |
paul@237 | 300 | void x1600_rtc_enable(void *rtc) |
paul@237 | 301 | { |
paul@237 | 302 | static_cast<Rtc_x1600_chip *>(rtc)->enable(); |
paul@237 | 303 | } |
paul@237 | 304 | |
paul@237 | 305 | void x1600_rtc_alarm_disable(void *rtc) |
paul@237 | 306 | { |
paul@237 | 307 | static_cast<Rtc_x1600_chip *>(rtc)->alarm_disable(); |
paul@237 | 308 | } |
paul@237 | 309 | |
paul@237 | 310 | void x1600_rtc_alarm_enable(void *rtc) |
paul@237 | 311 | { |
paul@237 | 312 | static_cast<Rtc_x1600_chip *>(rtc)->alarm_enable(); |
paul@237 | 313 | } |
paul@237 | 314 | |
paul@237 | 315 | uint32_t x1600_rtc_get_seconds(void *rtc) |
paul@237 | 316 | { |
paul@237 | 317 | return static_cast<Rtc_x1600_chip *>(rtc)->get_seconds(); |
paul@237 | 318 | } |
paul@237 | 319 | |
paul@237 | 320 | void x1600_rtc_set_seconds(void *rtc, uint32_t seconds) |
paul@237 | 321 | { |
paul@237 | 322 | static_cast<Rtc_x1600_chip *>(rtc)->set_seconds(seconds); |
paul@237 | 323 | } |
paul@237 | 324 | |
paul@237 | 325 | uint32_t x1600_rtc_get_alarm_seconds(void *rtc) |
paul@237 | 326 | { |
paul@237 | 327 | return static_cast<Rtc_x1600_chip *>(rtc)->get_alarm_seconds(); |
paul@237 | 328 | } |
paul@237 | 329 | |
paul@237 | 330 | void x1600_rtc_set_alarm_seconds(void *rtc, uint32_t seconds) |
paul@237 | 331 | { |
paul@237 | 332 | static_cast<Rtc_x1600_chip *>(rtc)->set_alarm_seconds(seconds); |
paul@237 | 333 | } |
paul@237 | 334 | |
paul@237 | 335 | void x1600_rtc_set_regulator(void *rtc, uint32_t base, uint32_t adjustment) |
paul@237 | 336 | { |
paul@237 | 337 | static_cast<Rtc_x1600_chip *>(rtc)->set_regulator(base, adjustment); |
paul@237 | 338 | } |
paul@237 | 339 | |
paul@238 | 340 | void x1600_rtc_hibernate(void *rtc) |
paul@238 | 341 | { |
paul@238 | 342 | static_cast<Rtc_x1600_chip *>(rtc)->hibernate(); |
paul@238 | 343 | } |
paul@238 | 344 | |
paul@237 | 345 | void x1600_rtc_power_down(void *rtc) |
paul@237 | 346 | { |
paul@237 | 347 | static_cast<Rtc_x1600_chip *>(rtc)->power_down(); |
paul@237 | 348 | } |