paul@250 | 1 | /* |
paul@250 | 2 | * Timer/counter unit support. |
paul@250 | 3 | * |
paul@250 | 4 | * Copyright (C) 2024 Paul Boddie <paul@boddie.org.uk> |
paul@250 | 5 | * |
paul@250 | 6 | * This program is free software; you can redistribute it and/or |
paul@250 | 7 | * modify it under the terms of the GNU General Public License as |
paul@250 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@250 | 9 | * the License, or (at your option) any later version. |
paul@250 | 10 | * |
paul@250 | 11 | * This program is distributed in the hope that it will be useful, |
paul@250 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@250 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@250 | 14 | * GNU General Public License for more details. |
paul@250 | 15 | * |
paul@250 | 16 | * You should have received a copy of the GNU General Public License |
paul@250 | 17 | * along with this program; if not, write to the Free Software |
paul@250 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@250 | 19 | * Boston, MA 02110-1301, USA |
paul@250 | 20 | */ |
paul@250 | 21 | |
paul@250 | 22 | #include "tcu-x1600.h" |
paul@250 | 23 | |
paul@250 | 24 | |
paul@250 | 25 | |
paul@250 | 26 | // Register locations. |
paul@250 | 27 | |
paul@250 | 28 | enum Regs : unsigned |
paul@250 | 29 | { |
paul@250 | 30 | Tcu_control_base = 0x04c, // TCRn |
paul@250 | 31 | |
paul@250 | 32 | // Block size/step/offset for the above register set. |
paul@250 | 33 | |
paul@250 | 34 | Tcu_data_block_offset = 0x010, |
paul@250 | 35 | }; |
paul@250 | 36 | |
paul@250 | 37 | enum Regs_x1600 : unsigned |
paul@250 | 38 | { |
paul@250 | 39 | // X1600 channel-related locations. |
paul@250 | 40 | |
paul@250 | 41 | Tcu_store_flag_status = 0x200, // TSFR |
paul@250 | 42 | Tcu_store_set_flag = 0x204, // TSFSR |
paul@250 | 43 | Tcu_store_clear_flag = 0x208, // TSFCR |
paul@250 | 44 | Tcu_store_mask_status = 0x210, // TSMR |
paul@250 | 45 | Tcu_store_set_mask = 0x214, // TSMSR |
paul@250 | 46 | Tcu_store_clear_mask = 0x218, // TSMCR |
paul@250 | 47 | |
paul@250 | 48 | Tcu_capture_control_base = 0x0c0, // TCRn |
paul@250 | 49 | Tcu_capture_counter_base = 0x0e0, // CAPVRn |
paul@250 | 50 | Tcu_filter_value_base = 0x1a0, // FIRVRn |
paul@250 | 51 | Tcu_stored_counter_base = 0x220, // TSVRn |
paul@250 | 52 | Tcu_stored_filter_counter_base = 0x240, // TSFVRn |
paul@250 | 53 | |
paul@250 | 54 | // Block size/step/offset for the above register set. |
paul@250 | 55 | |
paul@250 | 56 | Tcu_capture_block_offset = 0x004, |
paul@250 | 57 | |
paul@250 | 58 | // Limits. |
paul@250 | 59 | |
paul@250 | 60 | Tcu_capture_channel_max = 3, |
paul@250 | 61 | }; |
paul@250 | 62 | |
paul@250 | 63 | // Field definitions. |
paul@250 | 64 | |
paul@250 | 65 | // Counter data constraints. |
paul@250 | 66 | |
paul@250 | 67 | enum Data_masks : unsigned |
paul@250 | 68 | { |
paul@250 | 69 | Data_mask = 0xffff, |
paul@250 | 70 | }; |
paul@250 | 71 | |
paul@250 | 72 | enum Control_bits_x1600 : unsigned |
paul@250 | 73 | { |
paul@250 | 74 | Store_negative_edge_enable = 0x04000000, // STORE_NEG_EN |
paul@250 | 75 | Store_positive_edge_enable = 0x02000000, // STORE_POS_EN |
paul@250 | 76 | Store_enable = 0x01000000, // STORE_EN |
paul@250 | 77 | |
paul@250 | 78 | Count_mode_field_mask = 0x3, // COUNT_MODE |
paul@250 | 79 | Count_mode_wrap_at_full_data = 0, |
paul@250 | 80 | Count_mode_wrap_at_field_limit = 1, |
paul@250 | 81 | Count_mode_stop_at_field_limit = 2, |
paul@250 | 82 | Count_mode_field_shift = 22, |
paul@250 | 83 | |
paul@250 | 84 | Count_source_field_mask = 0x3f, |
paul@250 | 85 | Count_gpio1_negative_edge_enable = 0x20, // GPIO1_NEG_EN |
paul@250 | 86 | Count_gpio1_positive_edge_enable = 0x10, // GPIO1_POS_EN |
paul@250 | 87 | Count_gpio0_negative_edge_enable = 0x08, // GPIO0_NEG_EN |
paul@250 | 88 | Count_gpio0_positive_edge_enable = 0x04, // GPIO0_POS_EN |
paul@250 | 89 | Count_clock_negative_edge_enable = 0x02, // CLK_NEG_EN |
paul@250 | 90 | Count_clock_positive_edge_enable = 0x01, // CLK_POS_EN |
paul@250 | 91 | Count_source_field_shift = 16, |
paul@250 | 92 | |
paul@250 | 93 | Count_shutdown = 0x00008000, // SHUTDOWN |
paul@250 | 94 | Count_gate_polarity_low = 0x00000000, // GATE_POLA = 0 |
paul@250 | 95 | Count_gate_polarity_high = 0x00004000, // GATE_POLA = 1 |
paul@250 | 96 | Count_direction_polarity_low = 0x00000000, // DIRECTION_POLA = 0 |
paul@250 | 97 | Count_direction_polarity_high = 0x00002000, // DIRECTION_POLA = 1 |
paul@250 | 98 | |
paul@250 | 99 | Count_gate_select_field_mask = 0x3, // GATE_SEL |
paul@250 | 100 | Count_gate_select_none = 0, |
paul@250 | 101 | Count_gate_select_clock = 1, |
paul@250 | 102 | Count_gate_select_gpio0 = 2, |
paul@250 | 103 | Count_gate_select_gpio1 = 3, |
paul@250 | 104 | Count_gate_select_field_shift = 11, |
paul@250 | 105 | |
paul@250 | 106 | Count_direction_select_field_mask = 0x7, // DIRECTION_SEL |
paul@250 | 107 | Count_direction_select_none = 0, |
paul@250 | 108 | Count_direction_select_clock = 1, |
paul@250 | 109 | Count_direction_select_gpio0 = 2, |
paul@250 | 110 | Count_direction_select_gpio1 = 3, |
paul@250 | 111 | Count_direction_select_gpio01 = 4, |
paul@250 | 112 | Count_direction_select_field_shift = 8, |
paul@250 | 113 | |
paul@250 | 114 | Count_gpio1_enable = 0x00000080, // GPIO1_EN |
paul@250 | 115 | Count_gpio0_enable = 0x00000040, // GPIO0_EN |
paul@250 | 116 | }; |
paul@250 | 117 | |
paul@250 | 118 | enum Capture_bits : unsigned |
paul@250 | 119 | { |
paul@250 | 120 | Capture_select_mask = 0x00070000, // CAPTURE_SEL |
paul@250 | 121 | Capture_select_clock = 0x00000000, // CAPTURE_SEL = 0 |
paul@250 | 122 | Capture_select_gpio0 = 0x00010000, // CAPTURE_SEL = 1 |
paul@250 | 123 | Capture_select_gpio1 = 0x00020000, // CAPTURE_SEL = 2 |
paul@250 | 124 | Capture_count_mask = 0x000000ff, // CAPTURE_NUM |
paul@250 | 125 | }; |
paul@250 | 126 | |
paul@250 | 127 | enum Capture_value_bits : unsigned |
paul@250 | 128 | { |
paul@250 | 129 | Capture_time_all_mask = 0xffff0000, // CAPTURE_ALL |
paul@250 | 130 | Capture_time_high_mask = 0x0000ffff, // CAPTURE_HEIGHT (sic) |
paul@250 | 131 | }; |
paul@250 | 132 | |
paul@250 | 133 | enum Filter_value_bits : unsigned |
paul@250 | 134 | { |
paul@250 | 135 | Filter_gpio1_value_mask = 0x03ff0000, // FIL_B |
paul@250 | 136 | Filter_gpio0_value_mask = 0x000003ff, // FIL_A |
paul@250 | 137 | }; |
paul@250 | 138 | |
paul@250 | 139 | enum Store_filter_bits : unsigned |
paul@250 | 140 | { |
paul@250 | 141 | Store_filter_value_mask = 0x3ff, // STR_FIL |
paul@250 | 142 | }; |
paul@250 | 143 | |
paul@250 | 144 | |
paul@250 | 145 | |
paul@250 | 146 | // Channel abstraction. |
paul@250 | 147 | |
paul@252 | 148 | Tcu_x1600_channel::Tcu_x1600_channel(l4_addr_t addr, uint8_t channel, |
paul@252 | 149 | l4_cap_idx_t irq) |
paul@252 | 150 | : Tcu_channel(addr, channel, irq) |
paul@250 | 151 | { |
paul@250 | 152 | } |
paul@250 | 153 | |
paul@250 | 154 | // Operation methods. |
paul@250 | 155 | |
paul@250 | 156 | void |
paul@250 | 157 | Tcu_x1600_channel::enable() |
paul@250 | 158 | { |
paul@250 | 159 | // NOTE: Use a positive clock edge for the timer event by default. |
paul@250 | 160 | |
paul@250 | 161 | set_field(Tcu_control_base + _channel * Tcu_data_block_offset, |
paul@250 | 162 | Count_source_field_mask, Count_source_field_shift, |
paul@250 | 163 | Count_clock_positive_edge_enable); |
paul@250 | 164 | |
paul@250 | 165 | Tcu_channel::enable(); |
paul@250 | 166 | } |
paul@250 | 167 | |
paul@250 | 168 | uint8_t |
paul@250 | 169 | Tcu_x1600_channel::get_count_mode() |
paul@250 | 170 | { |
paul@250 | 171 | return get_field(Tcu_control_base + _channel * Tcu_data_block_offset, |
paul@250 | 172 | Count_mode_field_mask, Count_mode_field_shift); |
paul@250 | 173 | } |
paul@250 | 174 | |
paul@250 | 175 | void |
paul@250 | 176 | Tcu_x1600_channel::set_count_mode(uint8_t mode) |
paul@250 | 177 | { |
paul@250 | 178 | set_field(Tcu_control_base + _channel * Tcu_data_block_offset, |
paul@250 | 179 | Count_mode_field_mask, Count_mode_field_shift, mode); |
paul@250 | 180 | } |
paul@250 | 181 | |
paul@250 | 182 | |
paul@250 | 183 | |
paul@250 | 184 | // Peripheral abstraction. |
paul@250 | 185 | |
paul@250 | 186 | Tcu_x1600_chip::Tcu_x1600_chip(l4_addr_t start, l4_addr_t end) |
paul@250 | 187 | : Tcu_chip(start, end) |
paul@250 | 188 | { |
paul@250 | 189 | } |
paul@250 | 190 | |
paul@252 | 191 | Tcu_channel *Tcu_x1600_chip::_get_channel(l4_addr_t addr, uint8_t channel, |
paul@252 | 192 | l4_cap_idx_t irq) |
paul@250 | 193 | { |
paul@252 | 194 | return new Tcu_x1600_channel(addr, channel, irq); |
paul@250 | 195 | } |
paul@250 | 196 | |
paul@250 | 197 | |
paul@250 | 198 | |
paul@250 | 199 | // C language interface functions. |
paul@250 | 200 | |
paul@250 | 201 | void *x1600_tcu_init(l4_addr_t tcu_base, l4_addr_t tcu_base_end) |
paul@250 | 202 | { |
paul@250 | 203 | return (void *) new Tcu_x1600_chip(tcu_base, tcu_base_end); |
paul@250 | 204 | } |
paul@250 | 205 | |
paul@252 | 206 | void *x1600_tcu_get_channel(void *tcu, uint8_t channel, l4_cap_idx_t irq) |
paul@250 | 207 | { |
paul@252 | 208 | return static_cast<Tcu_x1600_chip *>(tcu)->get_channel(channel, irq); |
paul@250 | 209 | } |
paul@250 | 210 | |
paul@250 | 211 | void x1600_tcu_disable(void *tcu_channel) |
paul@250 | 212 | { |
paul@250 | 213 | static_cast<Tcu_x1600_channel *>(tcu_channel)->disable(); |
paul@250 | 214 | } |
paul@250 | 215 | |
paul@250 | 216 | void x1600_tcu_enable(void *tcu_channel) |
paul@250 | 217 | { |
paul@250 | 218 | static_cast<Tcu_x1600_channel *>(tcu_channel)->enable(); |
paul@250 | 219 | } |
paul@250 | 220 | |
paul@250 | 221 | int x1600_tcu_is_enabled(void *tcu_channel) |
paul@250 | 222 | { |
paul@250 | 223 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->is_enabled(); |
paul@250 | 224 | } |
paul@250 | 225 | |
paul@250 | 226 | uint8_t x1600_tcu_get_clock(void *tcu_channel) |
paul@250 | 227 | { |
paul@250 | 228 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->get_clock(); |
paul@250 | 229 | } |
paul@250 | 230 | |
paul@250 | 231 | void x1600_tcu_set_clock(void *tcu_channel, uint8_t clock) |
paul@250 | 232 | { |
paul@250 | 233 | static_cast<Tcu_x1600_channel *>(tcu_channel)->set_clock(clock); |
paul@250 | 234 | } |
paul@250 | 235 | |
paul@250 | 236 | uint32_t x1600_tcu_get_prescale(void *tcu_channel) |
paul@250 | 237 | { |
paul@250 | 238 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->get_prescale(); |
paul@250 | 239 | } |
paul@250 | 240 | |
paul@250 | 241 | void x1600_tcu_set_prescale(void *tcu_channel, uint32_t prescale) |
paul@250 | 242 | { |
paul@250 | 243 | static_cast<Tcu_x1600_channel *>(tcu_channel)->set_prescale(prescale); |
paul@250 | 244 | } |
paul@250 | 245 | |
paul@250 | 246 | uint32_t x1600_tcu_get_counter(void *tcu_channel) |
paul@250 | 247 | { |
paul@250 | 248 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->get_counter(); |
paul@250 | 249 | } |
paul@250 | 250 | |
paul@250 | 251 | void x1600_tcu_set_counter(void *tcu_channel, uint32_t value) |
paul@250 | 252 | { |
paul@250 | 253 | static_cast<Tcu_x1600_channel *>(tcu_channel)->set_counter(value); |
paul@250 | 254 | } |
paul@250 | 255 | |
paul@250 | 256 | uint8_t x1600_tcu_get_count_mode(void *tcu_channel) |
paul@250 | 257 | { |
paul@250 | 258 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->get_count_mode(); |
paul@250 | 259 | } |
paul@250 | 260 | |
paul@250 | 261 | void x1600_tcu_set_count_mode(void *tcu_channel, uint8_t mode) |
paul@250 | 262 | { |
paul@250 | 263 | static_cast<Tcu_x1600_channel *>(tcu_channel)->set_count_mode(mode); |
paul@250 | 264 | } |
paul@250 | 265 | |
paul@250 | 266 | uint32_t x1600_tcu_get_full_data_value(void *tcu_channel) |
paul@250 | 267 | { |
paul@250 | 268 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->get_full_data_value(); |
paul@250 | 269 | } |
paul@250 | 270 | |
paul@250 | 271 | void x1600_tcu_set_full_data_value(void *tcu_channel, uint32_t value) |
paul@250 | 272 | { |
paul@250 | 273 | static_cast<Tcu_x1600_channel *>(tcu_channel)->set_full_data_value(value); |
paul@250 | 274 | } |
paul@250 | 275 | |
paul@250 | 276 | uint32_t x1600_tcu_get_half_data_value(void *tcu_channel) |
paul@250 | 277 | { |
paul@250 | 278 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->get_half_data_value(); |
paul@250 | 279 | } |
paul@250 | 280 | |
paul@250 | 281 | void x1600_tcu_set_half_data_value(void *tcu_channel, uint32_t value) |
paul@250 | 282 | { |
paul@250 | 283 | static_cast<Tcu_x1600_channel *>(tcu_channel)->set_full_data_value(value); |
paul@250 | 284 | } |
paul@252 | 285 | |
paul@252 | 286 | int x1600_tcu_get_full_data_mask(void *tcu_channel) |
paul@252 | 287 | { |
paul@252 | 288 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->get_full_data_mask(); |
paul@252 | 289 | } |
paul@252 | 290 | |
paul@252 | 291 | void x1600_tcu_set_full_data_mask(void *tcu_channel, int masked) |
paul@252 | 292 | { |
paul@252 | 293 | static_cast<Tcu_x1600_channel *>(tcu_channel)->set_full_data_mask(masked); |
paul@252 | 294 | } |
paul@252 | 295 | |
paul@252 | 296 | int x1600_tcu_get_half_data_mask(void *tcu_channel) |
paul@252 | 297 | { |
paul@252 | 298 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->get_half_data_mask(); |
paul@252 | 299 | } |
paul@252 | 300 | |
paul@252 | 301 | void x1600_tcu_set_half_data_mask(void *tcu_channel, int masked) |
paul@252 | 302 | { |
paul@252 | 303 | static_cast<Tcu_x1600_channel *>(tcu_channel)->set_half_data_mask(masked); |
paul@252 | 304 | } |
paul@252 | 305 | |
paul@252 | 306 | int x1600_tcu_have_interrupt(void *tcu_channel) |
paul@252 | 307 | { |
paul@252 | 308 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->have_interrupt(); |
paul@252 | 309 | } |
paul@252 | 310 | |
paul@252 | 311 | int x1600_tcu_wait_for_irq(void *tcu_channel, unsigned int timeout) |
paul@252 | 312 | { |
paul@252 | 313 | return static_cast<Tcu_x1600_channel *>(tcu_channel)->wait_for_irq(timeout); |
paul@252 | 314 | } |