paul@0 | 1 | /* |
paul@0 | 2 | * GPIO driver for Ingenic JZ4730. |
paul@0 | 3 | * (See below for additional copyright and licensing notices.) |
paul@0 | 4 | * |
paul@188 | 5 | * Copyright (C) 2017, 2018, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 6 | * |
paul@0 | 7 | * This program is free software; you can redistribute it and/or |
paul@0 | 8 | * modify it under the terms of the GNU General Public License as |
paul@0 | 9 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 10 | * the License, or (at your option) any later version. |
paul@0 | 11 | * |
paul@0 | 12 | * This program is distributed in the hope that it will be useful, |
paul@0 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 15 | * GNU General Public License for more details. |
paul@0 | 16 | * |
paul@0 | 17 | * You should have received a copy of the GNU General Public License |
paul@0 | 18 | * along with this program; if not, write to the Free Software |
paul@0 | 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 20 | * Boston, MA 02110-1301, USA |
paul@0 | 21 | * |
paul@0 | 22 | * |
paul@0 | 23 | * Subject to other copyrights, being derived from the bcm2835.cc and |
paul@0 | 24 | * omap.cc GPIO driver implementations. |
paul@0 | 25 | * |
paul@0 | 26 | * This file is part of TUD:OS and distributed under the terms of the |
paul@0 | 27 | * GNU General Public License 2. |
paul@0 | 28 | * Please see the COPYING-GPL-2 file for details. |
paul@0 | 29 | */ |
paul@0 | 30 | |
paul@0 | 31 | #include <l4/sys/icu.h> |
paul@0 | 32 | #include <l4/util/util.h> |
paul@0 | 33 | #include <l4/devices/hw_mmio_register_block.h> |
paul@0 | 34 | |
paul@0 | 35 | #include "gpio-jz4730.h" |
paul@0 | 36 | |
paul@0 | 37 | // GPIO register offsets (x in A..D). |
paul@0 | 38 | |
paul@0 | 39 | enum Regs |
paul@0 | 40 | { |
paul@0 | 41 | Port_data = 0x000, // PxGPDR |
paul@0 | 42 | Port_direction = 0x004, // PxGPDIR |
paul@0 | 43 | Pull_enable = 0x00c, // PxGPPUR |
paul@0 | 44 | Port_function_lower = 0x010, // PxGPALR |
paul@0 | 45 | Port_function_upper = 0x014, // PxGPAUR |
paul@0 | 46 | Irq_detect_lower = 0x018, // PxGPDLR |
paul@0 | 47 | Irq_detect_upper = 0x01c, // PxGPDUR |
paul@0 | 48 | Irq_enable = 0x020, // PxGPIER |
paul@188 | 49 | Irq_mask = 0x024, // PxGPIM |
paul@0 | 50 | Irq_flag = 0x028, // PxGPFR |
paul@0 | 51 | }; |
paul@0 | 52 | |
paul@0 | 53 | |
paul@0 | 54 | |
paul@0 | 55 | // Select the appropriate register and pin where two bits are assigned per pin, |
paul@0 | 56 | // thus requiring two 32-bit registers to hold the configuration of 32 pins. |
paul@0 | 57 | |
paul@0 | 58 | static |
paul@0 | 59 | uint32_t |
paul@0 | 60 | _select_bank_for_pin(uint32_t reg_upper, uint32_t reg_lower, uint8_t pin, uint8_t *pin_out) |
paul@0 | 61 | { |
paul@0 | 62 | if (pin < 16) |
paul@0 | 63 | { |
paul@0 | 64 | *pin_out = pin; |
paul@0 | 65 | return reg_lower; |
paul@0 | 66 | } |
paul@0 | 67 | else |
paul@0 | 68 | { |
paul@0 | 69 | *pin_out = pin - 16; |
paul@0 | 70 | return reg_upper; |
paul@0 | 71 | } |
paul@0 | 72 | } |
paul@0 | 73 | |
paul@0 | 74 | // IRQ control for each GPIO pin. |
paul@0 | 75 | |
paul@0 | 76 | Gpio_jz4730_irq_pin::Gpio_jz4730_irq_pin(unsigned pin, Hw::Register_block<32> const ®s) |
paul@0 | 77 | : _pin(pin), _regs(regs) |
paul@0 | 78 | {} |
paul@0 | 79 | |
paul@0 | 80 | void |
paul@0 | 81 | Gpio_jz4730_irq_pin::write_reg_pin(unsigned reg) |
paul@0 | 82 | { |
paul@0 | 83 | // Write the pin bit to the register, setting or clearing the pin |
paul@0 | 84 | // depending on the register chosen. |
paul@0 | 85 | |
paul@0 | 86 | _regs[reg] = _pin_bit(_pin); |
paul@0 | 87 | } |
paul@0 | 88 | |
paul@0 | 89 | void |
paul@0 | 90 | Gpio_jz4730_irq_pin::clear_reg_pin(unsigned reg) |
paul@0 | 91 | { |
paul@0 | 92 | // Clear the pin bit in the register. |
paul@0 | 93 | |
paul@0 | 94 | _regs[reg] = _regs[reg] & ~(_pin_bit(_pin)); |
paul@0 | 95 | } |
paul@0 | 96 | |
paul@0 | 97 | void |
paul@0 | 98 | Gpio_jz4730_irq_pin::set_reg_pin(unsigned reg) |
paul@0 | 99 | { |
paul@0 | 100 | // Set the pin bit in the register. |
paul@0 | 101 | |
paul@0 | 102 | _regs[reg] = _regs[reg] | _pin_bit(_pin); |
paul@0 | 103 | } |
paul@0 | 104 | |
paul@0 | 105 | // Clear the pin bits in the appropriate register. |
paul@0 | 106 | |
paul@0 | 107 | void |
paul@0 | 108 | Gpio_jz4730_irq_pin::clear_reg_pins(uint32_t reg_upper, uint32_t reg_lower) |
paul@0 | 109 | { |
paul@0 | 110 | uint8_t pin_out; |
paul@0 | 111 | uint32_t reg = _select_bank_for_pin(reg_upper, reg_lower, _pin, &pin_out); |
paul@0 | 112 | |
paul@0 | 113 | _regs[reg] = _regs[reg] & ~(3 << (pin_out << 1)); |
paul@0 | 114 | } |
paul@0 | 115 | |
paul@0 | 116 | // Clear and set the given value in the pin bits of the appropriate register. |
paul@0 | 117 | |
paul@0 | 118 | void |
paul@0 | 119 | Gpio_jz4730_irq_pin::set_reg_pins(uint32_t reg_upper, uint32_t reg_lower, uint8_t value) |
paul@0 | 120 | { |
paul@0 | 121 | uint8_t pin_out; |
paul@0 | 122 | uint32_t reg = _select_bank_for_pin(reg_upper, reg_lower, _pin, &pin_out); |
paul@0 | 123 | |
paul@0 | 124 | _regs[reg] = (_regs[reg] & ~(3 << (pin_out << 1))) | (value << (pin_out << 1)); |
paul@0 | 125 | } |
paul@0 | 126 | |
paul@0 | 127 | void Gpio_jz4730_irq_pin::do_mask() |
paul@0 | 128 | { |
paul@0 | 129 | // Set the interrupt bit in the PxGPIER register. |
paul@0 | 130 | |
paul@188 | 131 | /* NOTE: This should use the Irq_mask/PxGPIM register, with the enable |
paul@188 | 132 | register actually setting IRQ mode. */ |
paul@188 | 133 | |
paul@0 | 134 | clear_reg_pin(Irq_enable); |
paul@0 | 135 | } |
paul@0 | 136 | |
paul@0 | 137 | void Gpio_jz4730_irq_pin::do_unmask() |
paul@0 | 138 | { |
paul@0 | 139 | // Set the interrupt bit in the PxGPIER register, first also clearing the |
paul@0 | 140 | // flag bit in the PxGPFR register to allow interrupts to be delivered. |
paul@0 | 141 | |
paul@188 | 142 | /* NOTE: This should use the Irq_mask/PxGPIM register, with the enable |
paul@188 | 143 | register actually setting IRQ mode. */ |
paul@188 | 144 | |
paul@0 | 145 | clear_reg_pin(Irq_flag); |
paul@0 | 146 | set_reg_pin(Irq_enable); |
paul@0 | 147 | } |
paul@0 | 148 | |
paul@0 | 149 | bool Gpio_jz4730_irq_pin::do_set_mode(unsigned mode) |
paul@0 | 150 | { |
paul@0 | 151 | // Standard comment found for this method: |
paul@0 | 152 | // this operation touches multiple mmio registers and is thus |
paul@0 | 153 | // not atomic, that's why we first mask the IRQ and if it was |
paul@0 | 154 | // enabled we unmask it after we have changed the mode |
paul@0 | 155 | |
paul@0 | 156 | if (enabled()) |
paul@0 | 157 | do_mask(); |
paul@0 | 158 | |
paul@0 | 159 | // Do the PxGPDUR/PxGPDLR configuration. |
paul@0 | 160 | |
paul@0 | 161 | switch(mode) |
paul@0 | 162 | { |
paul@0 | 163 | case L4_IRQ_F_LEVEL_HIGH: |
paul@0 | 164 | set_reg_pins(Irq_detect_upper, Irq_detect_lower, 1); |
paul@0 | 165 | break; |
paul@0 | 166 | case L4_IRQ_F_LEVEL_LOW: |
paul@0 | 167 | set_reg_pins(Irq_detect_upper, Irq_detect_lower, 0); |
paul@0 | 168 | break; |
paul@0 | 169 | case L4_IRQ_F_POS_EDGE: |
paul@0 | 170 | set_reg_pins(Irq_detect_upper, Irq_detect_lower, 3); |
paul@0 | 171 | break; |
paul@0 | 172 | case L4_IRQ_F_NEG_EDGE: |
paul@0 | 173 | set_reg_pins(Irq_detect_upper, Irq_detect_lower, 2); |
paul@0 | 174 | break; |
paul@0 | 175 | |
paul@0 | 176 | default: |
paul@0 | 177 | return false; |
paul@0 | 178 | } |
paul@0 | 179 | |
paul@0 | 180 | // Do the PxGPDIR, PxGPAUR/PxGPALR configuration. |
paul@0 | 181 | |
paul@0 | 182 | clear_reg_pin(Port_direction); |
paul@0 | 183 | clear_reg_pins(Port_function_upper, Port_function_lower); |
paul@0 | 184 | |
paul@0 | 185 | if (enabled()) |
paul@0 | 186 | do_unmask(); |
paul@0 | 187 | |
paul@0 | 188 | return true; |
paul@0 | 189 | } |
paul@0 | 190 | |
paul@0 | 191 | int Gpio_jz4730_irq_pin::clear() |
paul@0 | 192 | { |
paul@0 | 193 | // Obtain the flag status for the pin, clearing it if set. |
paul@0 | 194 | |
paul@0 | 195 | l4_uint32_t e = _regs[Irq_flag] & (1UL << _pin); |
paul@0 | 196 | if (e) |
paul@0 | 197 | clear_reg_pin(Irq_flag); |
paul@0 | 198 | |
paul@0 | 199 | return (e >> _pin); |
paul@0 | 200 | } |
paul@0 | 201 | |
paul@0 | 202 | bool Gpio_jz4730_irq_pin::enabled() |
paul@0 | 203 | { |
paul@0 | 204 | return true; |
paul@0 | 205 | } |
paul@0 | 206 | |
paul@0 | 207 | |
paul@0 | 208 | |
paul@0 | 209 | // Return two bitmaps for the given bitmap and value. |
paul@0 | 210 | |
paul@0 | 211 | static |
paul@0 | 212 | void |
paul@0 | 213 | _get_bitmaps(uint32_t bitmap, uint8_t value, uint32_t *upper, uint32_t *lower) |
paul@0 | 214 | { |
paul@0 | 215 | uint32_t mask = 0x80000000; |
paul@0 | 216 | |
paul@0 | 217 | *upper = 0; *lower = 0; |
paul@0 | 218 | |
paul@0 | 219 | while (mask != 0x8000) |
paul@0 | 220 | { |
paul@0 | 221 | *upper = (*upper << 2) | (bitmap & mask ? value : 0); |
paul@0 | 222 | mask >>= 1; |
paul@0 | 223 | } |
paul@0 | 224 | |
paul@0 | 225 | while (mask != 0) |
paul@0 | 226 | { |
paul@0 | 227 | *lower = (*lower << 2) | (bitmap & mask ? value : 0); |
paul@0 | 228 | mask >>= 1; |
paul@0 | 229 | } |
paul@0 | 230 | } |
paul@0 | 231 | |
paul@0 | 232 | |
paul@0 | 233 | |
paul@0 | 234 | // Initialise the GPIO controller. |
paul@0 | 235 | |
paul@0 | 236 | Gpio_jz4730_chip::Gpio_jz4730_chip(l4_addr_t start, l4_addr_t end, |
paul@0 | 237 | unsigned nr_pins) |
paul@0 | 238 | : _start(start), _end(end), |
paul@0 | 239 | _nr_pins(nr_pins) |
paul@0 | 240 | { |
paul@0 | 241 | _regs = new Hw::Mmio_register_block<32>(_start); |
paul@0 | 242 | } |
paul@0 | 243 | |
paul@0 | 244 | // Return the value of a pin. |
paul@0 | 245 | |
paul@0 | 246 | int |
paul@0 | 247 | Gpio_jz4730_chip::get(unsigned pin) |
paul@0 | 248 | { |
paul@0 | 249 | if (pin >= _nr_pins) |
paul@0 | 250 | throw -L4_EINVAL; |
paul@0 | 251 | |
paul@0 | 252 | l4_uint32_t val = _regs[Port_data]; |
paul@0 | 253 | return (val >> _pin_shift(pin)) & 1; |
paul@0 | 254 | } |
paul@0 | 255 | |
paul@0 | 256 | // Return multiple pin values. |
paul@0 | 257 | |
paul@0 | 258 | unsigned |
paul@0 | 259 | Gpio_jz4730_chip::multi_get(unsigned offset) |
paul@0 | 260 | { |
paul@0 | 261 | _reg_offset_check(offset); |
paul@0 | 262 | return _regs[Port_data]; |
paul@0 | 263 | } |
paul@0 | 264 | |
paul@0 | 265 | // Set the value of a pin. |
paul@0 | 266 | |
paul@0 | 267 | void |
paul@0 | 268 | Gpio_jz4730_chip::set(unsigned pin, int value) |
paul@0 | 269 | { |
paul@0 | 270 | if (pin >= _nr_pins) |
paul@0 | 271 | throw -L4_EINVAL; |
paul@0 | 272 | |
paul@0 | 273 | if (value) |
paul@0 | 274 | _regs[Port_data] = _regs[Port_data] | _pin_bit(pin); |
paul@0 | 275 | else |
paul@0 | 276 | _regs[Port_data] = _regs[Port_data] & ~_pin_bit(pin); |
paul@0 | 277 | } |
paul@0 | 278 | |
paul@0 | 279 | // Set multiple pin values. |
paul@0 | 280 | |
paul@0 | 281 | void |
paul@0 | 282 | Gpio_jz4730_chip::multi_set(Pin_slice const &mask, unsigned data) |
paul@0 | 283 | { |
paul@0 | 284 | _reg_offset_check(mask.offset); |
paul@0 | 285 | _regs[Port_data] = (_regs[Port_data] & ~(mask.mask)) | data; |
paul@0 | 286 | } |
paul@0 | 287 | |
paul@0 | 288 | // Set a pin up with the given mode and value (if appropriate). |
paul@0 | 289 | |
paul@0 | 290 | void |
paul@0 | 291 | Gpio_jz4730_chip::setup(unsigned pin, unsigned mode, int value) |
paul@0 | 292 | { |
paul@0 | 293 | if (pin >= _nr_pins) |
paul@0 | 294 | throw -L4_EINVAL; |
paul@0 | 295 | |
paul@0 | 296 | config(pin, mode); |
paul@0 | 297 | |
paul@0 | 298 | if (mode == Output) |
paul@0 | 299 | set(pin, value); |
paul@0 | 300 | } |
paul@0 | 301 | |
paul@0 | 302 | // Configuration of a pin using the generic input/output/IRQ mode. |
paul@0 | 303 | |
paul@0 | 304 | void |
paul@0 | 305 | Gpio_jz4730_chip::config(unsigned pin, unsigned mode) |
paul@0 | 306 | { |
paul@0 | 307 | _config(_pin_bit(pin), mode); |
paul@0 | 308 | } |
paul@0 | 309 | |
paul@0 | 310 | void |
paul@0 | 311 | Gpio_jz4730_chip::_config(unsigned bitmap, unsigned mode) |
paul@0 | 312 | { |
paul@0 | 313 | uint32_t upper_mask, lower_mask; |
paul@0 | 314 | |
paul@0 | 315 | switch (mode) |
paul@0 | 316 | { |
paul@0 | 317 | case Input: |
paul@0 | 318 | case Irq: |
paul@188 | 319 | // Clear the direction flags. |
paul@188 | 320 | _regs[Port_direction] = _regs[Port_direction] & ~bitmap; |
paul@188 | 321 | |
paul@188 | 322 | // Clear the port function for the bits. |
paul@188 | 323 | _get_bitmaps(bitmap, 3, &upper_mask, &lower_mask); |
paul@188 | 324 | _regs[Port_function_upper] = (_regs[Port_function_upper] & ~upper_mask); |
paul@188 | 325 | _regs[Port_function_lower] = (_regs[Port_function_lower] & ~lower_mask); |
paul@188 | 326 | break; |
paul@0 | 327 | |
paul@0 | 328 | case Output: |
paul@188 | 329 | // Set the direction flags. |
paul@188 | 330 | _regs[Port_direction] = _regs[Port_direction] | bitmap; |
paul@0 | 331 | |
paul@0 | 332 | // Clear the port function for the bits. |
paul@0 | 333 | _get_bitmaps(bitmap, 3, &upper_mask, &lower_mask); |
paul@0 | 334 | _regs[Port_function_upper] = (_regs[Port_function_upper] & ~upper_mask); |
paul@0 | 335 | _regs[Port_function_lower] = (_regs[Port_function_lower] & ~lower_mask); |
paul@0 | 336 | break; |
paul@0 | 337 | |
paul@0 | 338 | default: |
paul@0 | 339 | break; |
paul@0 | 340 | } |
paul@0 | 341 | } |
paul@0 | 342 | |
paul@0 | 343 | // Pull-up configuration for a pin. |
paul@0 | 344 | |
paul@0 | 345 | void |
paul@0 | 346 | Gpio_jz4730_chip::config_pull(unsigned pin, unsigned mode) |
paul@0 | 347 | { |
paul@0 | 348 | if (pin >= _nr_pins) |
paul@0 | 349 | throw -L4_EINVAL; |
paul@0 | 350 | |
paul@0 | 351 | _config_pull(_pin_bit(pin), mode); |
paul@0 | 352 | } |
paul@0 | 353 | |
paul@0 | 354 | void |
paul@0 | 355 | Gpio_jz4730_chip::_config_pull(unsigned bitmap, unsigned mode) |
paul@0 | 356 | { |
paul@0 | 357 | switch (mode) |
paul@0 | 358 | { |
paul@0 | 359 | case Pull_none: |
paul@0 | 360 | _regs[Pull_enable] = _regs[Pull_enable] & ~bitmap; |
paul@0 | 361 | break; |
paul@0 | 362 | case Pull_up: |
paul@0 | 363 | _regs[Pull_enable] = _regs[Pull_enable] | bitmap; |
paul@0 | 364 | break; |
paul@0 | 365 | default: |
paul@0 | 366 | // Invalid pull-up/down mode for pin. |
paul@0 | 367 | throw -L4_EINVAL; |
paul@0 | 368 | } |
paul@0 | 369 | } |
paul@0 | 370 | |
paul@0 | 371 | // Pin function configuration. |
paul@0 | 372 | |
paul@0 | 373 | void |
paul@0 | 374 | Gpio_jz4730_chip::config_pad(unsigned pin, unsigned func, unsigned value) |
paul@0 | 375 | { |
paul@0 | 376 | if (pin >= _nr_pins) |
paul@0 | 377 | throw -L4_EINVAL; |
paul@0 | 378 | |
paul@0 | 379 | _config_pad(_pin_bit(pin), func, value); |
paul@0 | 380 | } |
paul@0 | 381 | |
paul@0 | 382 | void |
paul@0 | 383 | Gpio_jz4730_chip::_config_pad(unsigned bitmap, unsigned func, unsigned value) |
paul@0 | 384 | { |
paul@0 | 385 | uint32_t upper_mask = 0, lower_mask = 0, upper = 0, lower = 0; |
paul@0 | 386 | |
paul@0 | 387 | if (value > 3) |
paul@0 | 388 | throw -L4_EINVAL; |
paul@0 | 389 | |
paul@0 | 390 | switch (func) |
paul@0 | 391 | { |
paul@0 | 392 | case Hw::Gpio_chip::Function_alt: |
paul@0 | 393 | _get_bitmaps(bitmap, value, &upper, &lower); |
paul@188 | 394 | _get_bitmaps(bitmap, 3, &upper_mask, &lower_mask); |
paul@188 | 395 | _regs[Port_function_upper] = (_regs[Port_function_upper] & ~upper_mask) | upper; |
paul@188 | 396 | _regs[Port_function_lower] = (_regs[Port_function_lower] & ~lower_mask) | lower; |
paul@188 | 397 | break; |
paul@0 | 398 | |
paul@0 | 399 | case Hw::Gpio_chip::Function_gpio: |
paul@0 | 400 | _get_bitmaps(bitmap, 3, &upper_mask, &lower_mask); |
paul@188 | 401 | _regs[Port_function_upper] = _regs[Port_function_upper] & ~upper_mask; |
paul@188 | 402 | _regs[Port_function_lower] = _regs[Port_function_lower] & ~lower_mask; |
paul@0 | 403 | break; |
paul@0 | 404 | |
paul@0 | 405 | default: |
paul@0 | 406 | throw -L4_EINVAL; |
paul@0 | 407 | } |
paul@0 | 408 | } |
paul@0 | 409 | |
paul@0 | 410 | // Obtain a pin's configuration from a register in the supplied value. |
paul@0 | 411 | |
paul@0 | 412 | void |
paul@0 | 413 | Gpio_jz4730_chip::config_get(unsigned pin, unsigned reg, unsigned *value) |
paul@0 | 414 | { |
paul@0 | 415 | if (pin >= _nr_pins) |
paul@0 | 416 | throw -L4_EINVAL; |
paul@0 | 417 | |
paul@0 | 418 | *value = (_regs[reg] >> _pin_shift(pin)) & 1; |
paul@0 | 419 | } |
paul@0 | 420 | |
paul@188 | 421 | // Return function and function-specific configuration for a pin. |
paul@188 | 422 | |
paul@188 | 423 | void |
paul@188 | 424 | Gpio_jz4730_chip::config_pad_get(unsigned pin, unsigned *func, unsigned *value) |
paul@188 | 425 | { |
paul@188 | 426 | unsigned detect, direction, pin_function, interrupt; |
paul@188 | 427 | |
paul@188 | 428 | // Get the pin function using the awkward register pairing. |
paul@188 | 429 | |
paul@188 | 430 | _get_pin_value(pin, Port_function_upper, Port_function_lower, &pin_function); |
paul@188 | 431 | |
paul@188 | 432 | if (pin_function) |
paul@188 | 433 | { |
paul@188 | 434 | *func = Hw::Gpio_chip::Function_alt; |
paul@188 | 435 | *value = pin_function; |
paul@188 | 436 | return; |
paul@188 | 437 | } |
paul@188 | 438 | |
paul@188 | 439 | config_get(pin, Irq_enable, &interrupt); |
paul@188 | 440 | |
paul@188 | 441 | if (interrupt) |
paul@188 | 442 | { |
paul@188 | 443 | _get_pin_value(pin, Irq_detect_upper, Irq_detect_lower, &detect); |
paul@188 | 444 | |
paul@188 | 445 | *func = Hw::Gpio_chip::Function_irq; |
paul@188 | 446 | |
paul@188 | 447 | switch (detect) |
paul@188 | 448 | { |
paul@188 | 449 | case 0: *value = L4_IRQ_F_LEVEL_LOW; break; |
paul@188 | 450 | case 1: *value = L4_IRQ_F_LEVEL_HIGH; break; |
paul@188 | 451 | case 2: *value = L4_IRQ_F_NEG_EDGE; break; |
paul@188 | 452 | default: case 3: *value = L4_IRQ_F_POS_EDGE; break; |
paul@188 | 453 | } |
paul@188 | 454 | return; |
paul@188 | 455 | } |
paul@188 | 456 | |
paul@188 | 457 | config_get(pin, Port_direction, &direction); |
paul@188 | 458 | |
paul@188 | 459 | *func = Hw::Gpio_chip::Function_gpio; |
paul@188 | 460 | *value = direction ? Output : Input; |
paul@188 | 461 | } |
paul@188 | 462 | |
paul@188 | 463 | void |
paul@188 | 464 | Gpio_jz4730_chip::_get_pin_value(unsigned pin, uint32_t reg_upper, |
paul@188 | 465 | uint32_t reg_lower, unsigned *value) |
paul@188 | 466 | { |
paul@188 | 467 | uint8_t pin_out; |
paul@188 | 468 | |
paul@188 | 469 | if (pin >= _nr_pins) |
paul@188 | 470 | throw -L4_EINVAL; |
paul@188 | 471 | |
paul@188 | 472 | uint32_t reg = _select_bank_for_pin(reg_upper, reg_lower, pin, &pin_out); |
paul@188 | 473 | |
paul@188 | 474 | *value = (_regs[reg] & (3 << (pin_out << 1))) >> (pin_out << 1); |
paul@188 | 475 | } |
paul@188 | 476 | |
paul@0 | 477 | // Obtain an IRQ abstraction for a pin. |
paul@0 | 478 | |
paul@0 | 479 | Hw::Gpio_irq_pin * |
paul@0 | 480 | Gpio_jz4730_chip::get_irq(unsigned pin) |
paul@0 | 481 | { |
paul@0 | 482 | if (pin >= _nr_pins) |
paul@0 | 483 | throw -L4_EINVAL; |
paul@0 | 484 | |
paul@0 | 485 | return new Gpio_jz4730_irq_pin(pin, _regs); |
paul@0 | 486 | } |
paul@0 | 487 | |
paul@0 | 488 | // Pull-up function configuration for multiple pins. |
paul@0 | 489 | |
paul@0 | 490 | void |
paul@0 | 491 | Gpio_jz4730_chip::multi_config_pull(Pin_slice const &mask, unsigned mode) |
paul@0 | 492 | { |
paul@0 | 493 | _config_pull(mask.mask << mask.offset, mode); |
paul@0 | 494 | } |
paul@0 | 495 | |
paul@0 | 496 | // Pin function configuration for multiple pins. |
paul@0 | 497 | |
paul@0 | 498 | void |
paul@0 | 499 | Gpio_jz4730_chip::multi_config_pad(Pin_slice const &mask, unsigned func, unsigned val) |
paul@0 | 500 | { |
paul@0 | 501 | _config_pad(mask.mask << mask.offset, func, val); |
paul@0 | 502 | } |
paul@0 | 503 | |
paul@0 | 504 | // Set up multiple pins with the given mode. |
paul@0 | 505 | |
paul@0 | 506 | void |
paul@0 | 507 | Gpio_jz4730_chip::multi_setup(Pin_slice const &mask, unsigned mode, unsigned outvalues) |
paul@0 | 508 | { |
paul@0 | 509 | _config(mask.mask << mask.offset, mode); |
paul@0 | 510 | |
paul@0 | 511 | if (mode == Output) |
paul@0 | 512 | multi_set(mask, outvalues); |
paul@0 | 513 | } |
paul@0 | 514 | |
paul@0 | 515 | |
paul@0 | 516 | |
paul@0 | 517 | // C language interface functions. |
paul@0 | 518 | |
paul@0 | 519 | void *jz4730_gpio_init(l4_addr_t start, l4_addr_t end, unsigned pins) |
paul@0 | 520 | { |
paul@0 | 521 | return (void *) new Gpio_jz4730_chip(start, end, pins); |
paul@0 | 522 | } |
paul@0 | 523 | |
paul@0 | 524 | void jz4730_gpio_setup(void *gpio, unsigned pin, unsigned mode, int value) |
paul@0 | 525 | { |
paul@0 | 526 | static_cast<Gpio_jz4730_chip *>(gpio)->setup(pin, mode, value); |
paul@0 | 527 | } |
paul@0 | 528 | |
paul@0 | 529 | void jz4730_gpio_config_pull(void *gpio, unsigned pin, unsigned mode) |
paul@0 | 530 | { |
paul@0 | 531 | static_cast<Gpio_jz4730_chip *>(gpio)->config_pull(pin, mode); |
paul@0 | 532 | } |
paul@0 | 533 | |
paul@0 | 534 | void jz4730_gpio_config_pad(void *gpio, unsigned pin, unsigned func, unsigned value) |
paul@0 | 535 | { |
paul@0 | 536 | static_cast<Gpio_jz4730_chip *>(gpio)->config_pad(pin, func, value); |
paul@0 | 537 | } |
paul@0 | 538 | |
paul@0 | 539 | void jz4730_gpio_config_get(void *gpio, unsigned pin, unsigned reg, unsigned *value) |
paul@0 | 540 | { |
paul@0 | 541 | static_cast<Gpio_jz4730_chip *>(gpio)->config_get(pin, reg, value); |
paul@0 | 542 | } |
paul@0 | 543 | |
paul@188 | 544 | void jz4730_gpio_config_pad_get(void *gpio, unsigned pin, unsigned *func, unsigned *value) |
paul@188 | 545 | { |
paul@188 | 546 | static_cast<Gpio_jz4730_chip *>(gpio)->config_pad_get(pin, func, value); |
paul@188 | 547 | } |
paul@188 | 548 | |
paul@0 | 549 | void jz4730_gpio_multi_setup(void *gpio, Pin_slice const *mask, unsigned mode, unsigned outvalues) |
paul@0 | 550 | { |
paul@0 | 551 | static_cast<Gpio_jz4730_chip *>(gpio)->multi_setup(*mask, mode, outvalues); |
paul@0 | 552 | } |
paul@0 | 553 | |
paul@0 | 554 | void jz4730_gpio_multi_config_pull(void *gpio, Pin_slice const *mask, unsigned mode) |
paul@0 | 555 | { |
paul@0 | 556 | static_cast<Gpio_jz4730_chip *>(gpio)->multi_config_pull(*mask, mode); |
paul@0 | 557 | } |
paul@0 | 558 | |
paul@0 | 559 | void jz4730_gpio_multi_config_pad(void *gpio, Pin_slice const *mask, unsigned func, unsigned value) |
paul@0 | 560 | { |
paul@0 | 561 | static_cast<Gpio_jz4730_chip *>(gpio)->multi_config_pad(*mask, func, value); |
paul@0 | 562 | } |
paul@0 | 563 | |
paul@0 | 564 | void jz4730_gpio_multi_set(void *gpio, Pin_slice const *mask, unsigned data) |
paul@0 | 565 | { |
paul@0 | 566 | static_cast<Gpio_jz4730_chip *>(gpio)->multi_set(*mask, data); |
paul@0 | 567 | } |
paul@0 | 568 | |
paul@0 | 569 | unsigned jz4730_gpio_multi_get(void *gpio, unsigned offset) |
paul@0 | 570 | { |
paul@0 | 571 | return static_cast<Gpio_jz4730_chip *>(gpio)->multi_get(offset); |
paul@0 | 572 | } |
paul@0 | 573 | |
paul@0 | 574 | int jz4730_gpio_get(void *gpio, unsigned pin) |
paul@0 | 575 | { |
paul@0 | 576 | return static_cast<Gpio_jz4730_chip *>(gpio)->get(pin); |
paul@0 | 577 | } |
paul@0 | 578 | |
paul@0 | 579 | void jz4730_gpio_set(void *gpio, unsigned pin, int value) |
paul@0 | 580 | { |
paul@0 | 581 | static_cast<Gpio_jz4730_chip *>(gpio)->set(pin, value); |
paul@0 | 582 | } |
paul@0 | 583 | |
paul@0 | 584 | void *jz4730_gpio_get_irq(void *gpio, unsigned pin) |
paul@0 | 585 | { |
paul@0 | 586 | return (void *) static_cast<Gpio_jz4730_chip *>(gpio)->get_irq(pin); |
paul@0 | 587 | } |
paul@0 | 588 | |
paul@0 | 589 | bool jz4730_gpio_irq_set_mode(void *gpio_irq, unsigned mode) |
paul@0 | 590 | { |
paul@0 | 591 | return static_cast<Hw::Gpio_irq_pin *>(gpio_irq)->do_set_mode(mode); |
paul@0 | 592 | } |