paul@0 | 1 | /* |
paul@0 | 2 | * LCD configuration value definitions for the JZ4740 and related SoCs. |
paul@0 | 3 | * |
paul@31 | 4 | * Copyright (C) 2018 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software; you can redistribute it and/or |
paul@0 | 7 | * modify it under the terms of the GNU General Public License as |
paul@0 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 9 | * the License, or (at your option) any later version. |
paul@0 | 10 | * |
paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 14 | * GNU General Public License for more details. |
paul@0 | 15 | * |
paul@0 | 16 | * You should have received a copy of the GNU General Public License |
paul@0 | 17 | * along with this program; if not, write to the Free Software |
paul@0 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 19 | * Boston, MA 02110-1301, USA |
paul@0 | 20 | */ |
paul@0 | 21 | |
paul@0 | 22 | #pragma once |
paul@0 | 23 | |
paul@24 | 24 | enum Jz4740_lcd_config_bits |
paul@0 | 25 | { |
paul@0 | 26 | Jz4740_lcd_config_lcd_pin = 31, /* LCDPIN */ |
paul@0 | 27 | Jz4740_lcd_config_tv_pal_halfline = 30, /* JZ4780: TVEPEH */ |
paul@0 | 28 | Jz4740_lcd_config_desc_8_word = 28, /* JZ4780: NEWDES */ |
paul@0 | 29 | Jz4740_lcd_config_tv_enable = 26, /* JZ4780: TVEN */ |
paul@0 | 30 | Jz4740_lcd_config_underrun_recover = 25, /* JZ4780: RECOVER */ |
paul@0 | 31 | Jz4740_lcd_config_ps_disable = 23, /* PSM */ |
paul@0 | 32 | Jz4740_lcd_config_cls_disable = 22, /* CLSM */ |
paul@0 | 33 | Jz4740_lcd_config_spl_disable = 21, /* SPLM */ |
paul@0 | 34 | Jz4740_lcd_config_rev_disable = 20, /* REVM */ |
paul@0 | 35 | Jz4740_lcd_config_hsync_mod_disable = 19, /* HSYNM (hsync polarity choice) */ |
paul@0 | 36 | Jz4740_lcd_config_pclock_mod_disable = 18, /* PCLKM (dot/pixel clock polarity choice) */ |
paul@0 | 37 | Jz4740_lcd_config_data_inverse = 17, /* INVDAT (inverse output data) */ |
paul@0 | 38 | Jz4740_lcd_config_sync_input = 16, /* SYNDIR (hsync/vsync direction) */ |
paul@0 | 39 | Jz4740_lcd_config_ps_reset = 15, /* PSP */ |
paul@0 | 40 | Jz4740_lcd_config_cls_reset = 14, /* CLSP */ |
paul@0 | 41 | Jz4740_lcd_config_spl_reset = 13, /* SPLP */ |
paul@0 | 42 | Jz4740_lcd_config_rev_reset = 12, /* REVP */ |
paul@0 | 43 | Jz4740_lcd_config_hsync_active_low = 11, /* HSP (hsync polarity) */ |
paul@0 | 44 | Jz4740_lcd_config_pclock_fall_edge = 10, /* PCP (dot/pixel clock polarity) */ |
paul@0 | 45 | Jz4740_lcd_config_de_active_low = 9, /* DEP (data enable polarity) */ |
paul@0 | 46 | Jz4740_lcd_config_vsync_fall_edge = 8, /* VSP (vsync polarity) */ |
paul@0 | 47 | Jz4740_lcd_config_bpp = 6, /* 16/18/24bpp selection for generic TFT */ |
paul@0 | 48 | Jz4740_lcd_config_stn_pins = 4, /* PDW (STN pins utilisation) */ |
paul@0 | 49 | Jz4740_lcd_config_mode = 0, |
paul@0 | 50 | }; |
paul@0 | 51 | |
paul@24 | 52 | enum Jz4740_lcd_bpp_values |
paul@0 | 53 | { |
paul@0 | 54 | Jz4740_lcd_bpp_16 = 0, |
paul@0 | 55 | Jz4740_lcd_bpp_24 = 1, /* JZ4780 */ |
paul@0 | 56 | Jz4740_lcd_bpp_18 = 2, |
paul@0 | 57 | }; |
paul@0 | 58 | |
paul@24 | 59 | enum Jz4740_lcd_modes |
paul@0 | 60 | { |
paul@0 | 61 | Jz4740_lcd_mode_tft_generic = 0, /* parallel 16/18/24-bit panel */ |
paul@0 | 62 | Jz4740_lcd_mode_tft_sharp = 1, |
paul@0 | 63 | Jz4740_lcd_mode_tft_casio = 2, |
paul@0 | 64 | Jz4740_lcd_mode_tft_samsung = 3, |
paul@0 | 65 | Jz4740_lcd_mode_ccir656_nonint = 4, /* non-interlaced (TV out) */ |
paul@0 | 66 | Jz4740_lcd_mode_ccir656_int = 6, /* interlaced (TV out) */ |
paul@0 | 67 | Jz4740_lcd_mode_stn_single_colour = 8, /* single == one panel */ |
paul@0 | 68 | Jz4740_lcd_mode_stn_single_mono = 9, |
paul@0 | 69 | Jz4740_lcd_mode_stn_dual_colour = 10, /* dual == two panels */ |
paul@0 | 70 | Jz4740_lcd_mode_stn_dual_mono = 11, |
paul@0 | 71 | Jz4740_lcd_mode_tft_serial = 12, /* serial 8-bit panel */ |
paul@0 | 72 | Jz4740_lcd_mode_lcm = 13, /* JZ4780 */ |
paul@0 | 73 | }; |
paul@0 | 74 | |
paul@24 | 75 | enum Jz4740_lcd_config_values |
paul@0 | 76 | { |
paul@0 | 77 | Jz4740_lcd_de_positive = 0 << Jz4740_lcd_config_de_active_low, |
paul@0 | 78 | Jz4740_lcd_de_negative = 1 << Jz4740_lcd_config_de_active_low, |
paul@0 | 79 | Jz4740_lcd_pclock_positive = 0 << Jz4740_lcd_config_pclock_fall_edge, |
paul@0 | 80 | Jz4740_lcd_pclock_negative = 1 << Jz4740_lcd_config_pclock_fall_edge, |
paul@0 | 81 | Jz4740_lcd_hsync_positive = 0 << Jz4740_lcd_config_hsync_active_low, |
paul@0 | 82 | Jz4740_lcd_hsync_negative = 1 << Jz4740_lcd_config_hsync_active_low, |
paul@0 | 83 | Jz4740_lcd_vsync_positive = 0 << Jz4740_lcd_config_vsync_fall_edge, |
paul@0 | 84 | Jz4740_lcd_vsync_negative = 1 << Jz4740_lcd_config_vsync_fall_edge, |
paul@0 | 85 | }; |