paul@75 | 1 | /* |
paul@75 | 2 | * LCD peripheral support for the JZ4740 and related SoCs. |
paul@75 | 3 | * |
paul@75 | 4 | * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> |
paul@75 | 5 | * Copyright (C) 2015, 2016, 2017, 2018, |
paul@75 | 6 | * 2020 Paul Boddie <paul@boddie.org.uk> |
paul@75 | 7 | * |
paul@75 | 8 | * This program is free software; you can redistribute it and/or |
paul@75 | 9 | * modify it under the terms of the GNU General Public License as |
paul@75 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@75 | 11 | * the License, or (at your option) any later version. |
paul@75 | 12 | * |
paul@75 | 13 | * This program is distributed in the hope that it will be useful, |
paul@75 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@75 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@75 | 16 | * GNU General Public License for more details. |
paul@75 | 17 | * |
paul@75 | 18 | * You should have received a copy of the GNU General Public License |
paul@75 | 19 | * along with this program; if not, write to the Free Software |
paul@75 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@75 | 21 | * Boston, MA 02110-1301, USA |
paul@75 | 22 | */ |
paul@75 | 23 | |
paul@75 | 24 | #pragma once |
paul@75 | 25 | |
paul@75 | 26 | |
paul@75 | 27 | |
paul@75 | 28 | enum Regs : unsigned |
paul@75 | 29 | { |
paul@75 | 30 | Lcd_config = 0x000, // LCD_CFG |
paul@75 | 31 | Lcd_vsync = 0x004, // LCD_VSYNC |
paul@75 | 32 | Lcd_hsync = 0x008, // LCD_HSYNC |
paul@75 | 33 | Virtual_area = 0x00c, // LCD_VAT |
paul@75 | 34 | Display_hlimits = 0x010, // LCD_DAH |
paul@75 | 35 | Display_vlimits = 0x014, // LCD_DAV |
paul@75 | 36 | Lcd_ps = 0x018, // LCD_PS |
paul@75 | 37 | Lcd_cls = 0x01c, // LCD_CLS |
paul@75 | 38 | Lcd_spl = 0x020, // LCD_SPL |
paul@75 | 39 | Lcd_rev = 0x024, // LCD_REV |
paul@75 | 40 | Lcd_control = 0x030, // LCD_CTRL |
paul@75 | 41 | Lcd_status = 0x034, // LCD_STATE |
paul@75 | 42 | Lcd_irq_id = 0x038, // LCD_IID |
paul@75 | 43 | Desc_address_0 = 0x040, // LCD_DA0 |
paul@75 | 44 | Source_address_0 = 0x044, // LCD_SA0 |
paul@75 | 45 | Frame_id_0 = 0x048, // LCD_FID0 |
paul@75 | 46 | Command_0 = 0x04c, // LCD_CMD0 |
paul@75 | 47 | Counter_position_0 = 0x068, // LCD_CPOS0 |
paul@75 | 48 | Foreground_size_0 = 0x06c, // LCD_DESSIZE0 |
paul@75 | 49 | Desc_address_1 = 0x050, // LCD_DA1 |
paul@75 | 50 | Source_address_1 = 0x054, // LCD_SA1 |
paul@75 | 51 | Frame_id_1 = 0x058, // LCD_FID1 |
paul@75 | 52 | Command_1 = 0x05c, // LCD_CMD1 |
paul@75 | 53 | Counter_position_1 = 0x078, // LCD_CPOS1 |
paul@75 | 54 | Foreground_size_1 = 0x07c, // LCD_DESSIZE1 |
paul@75 | 55 | Rgb_control = 0x090, // LCD_RGBC (JZ4780) |
paul@88 | 56 | Alpha_levels = 0x118, // LCD_ALPHA (JZ4780) |
paul@75 | 57 | Priority_level = 0x2c0, // LCD_PCFG |
paul@75 | 58 | |
paul@75 | 59 | // OSD registers. |
paul@75 | 60 | |
paul@75 | 61 | Osd_config = 0x100, // LCD_OSDC |
paul@75 | 62 | Osd_control = 0x104, // LCD_OSDCTRL |
paul@75 | 63 | Osd_status = 0x108, // LCD_OSDS |
paul@75 | 64 | }; |
paul@75 | 65 | |
paul@75 | 66 | // Lcd_config descriptions. |
paul@75 | 67 | |
paul@75 | 68 | enum Config_values : unsigned |
paul@75 | 69 | { |
paul@75 | 70 | Config_stn_pins_mask = 0x3, |
paul@75 | 71 | Config_mode_mask = 0xf, |
paul@75 | 72 | }; |
paul@75 | 73 | |
paul@75 | 74 | // Field positions for registers employing two values, with the first typically |
paul@75 | 75 | // being the start value and the second being an end value. |
paul@75 | 76 | |
paul@75 | 77 | enum Value_pair_bits : unsigned |
paul@75 | 78 | { |
paul@75 | 79 | Value_first = 16, |
paul@75 | 80 | Value_second = 0, |
paul@75 | 81 | }; |
paul@75 | 82 | |
paul@75 | 83 | // Virtual area bits. |
paul@75 | 84 | |
paul@75 | 85 | enum Virtual_area_values : unsigned |
paul@75 | 86 | { |
paul@75 | 87 | Virtual_area_horizontal_size = Value_first, // sum of display and blank regions (dot/pixel clock periods) |
paul@75 | 88 | Virtual_area_vertical_size = Value_second, // sum of display and blank regions (line periods) |
paul@75 | 89 | }; |
paul@75 | 90 | |
paul@75 | 91 | // Lcd_control descriptions. |
paul@75 | 92 | |
paul@75 | 93 | enum Control_bits : unsigned |
paul@75 | 94 | { |
paul@75 | 95 | Control_pin_modify = 31, // PINMD (change pin usage from 15..0 to 17..10, 8..1) |
paul@75 | 96 | Control_burst_length = 28, // BST (burst length selection) |
paul@75 | 97 | Control_rgb_mode = 27, // RGB (RGB mode) |
paul@75 | 98 | Control_out_underrun = 26, // OFUP (output FIFO underrun protection) |
paul@75 | 99 | Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection) |
paul@75 | 100 | Control_palette_delay = 16, // PDD (load palette delay counter) |
paul@75 | 101 | Control_dac_loopback_test = 14, // DACTE (DAC loopback test) |
paul@75 | 102 | Control_frame_end_irq_enable = 13, // EOFM (end of frame interrupt enable) |
paul@75 | 103 | Control_frame_start_irq_enable = 12, // SOFM (start of frame interrupt enable) |
paul@75 | 104 | Control_out_underrun_irq_enable = 11, // OFUM (output FIFO underrun interrupt enable) |
paul@75 | 105 | Control_in0_underrun_irq_enable = 10, // IFUM0 (input FIFO 0 underrun interrupt enable) |
paul@75 | 106 | Control_in1_underrun_irq_enable = 9, // IFUM1 (input FIFO 1 underrun interrupt enable) |
paul@75 | 107 | Control_disabled_irq_enable = 8, // LDDM (LCD disable done interrupt enable) |
paul@75 | 108 | Control_quick_disabled_irq_enable = 7, // QDM (LCD quick disable done interrupt enable) |
paul@75 | 109 | Control_endian_select = 6, // BEDN (endian selection) |
paul@75 | 110 | Control_bit_order = 5, // PEDN (bit order in bytes) |
paul@75 | 111 | Control_disable = 4, // DIS (disable controller) |
paul@75 | 112 | Control_enable = 3, // ENA (enable controller) |
paul@75 | 113 | Control_bpp = 0, // BPP (bits per pixel) |
paul@75 | 114 | }; |
paul@75 | 115 | |
paul@75 | 116 | enum Burst_length_values : unsigned |
paul@75 | 117 | { |
paul@75 | 118 | Burst_length_4 = 0, // 4 word |
paul@75 | 119 | Burst_length_8 = 1, // 8 word |
paul@75 | 120 | Burst_length_16 = 2, // 16 word |
paul@75 | 121 | |
paul@75 | 122 | // JZ4780 extensions. |
paul@75 | 123 | |
paul@75 | 124 | Burst_length_32 = 3, // 32 word |
paul@75 | 125 | Burst_length_64 = 4, // 64 word |
paul@75 | 126 | Burst_length_mask = 0x7, |
paul@75 | 127 | }; |
paul@75 | 128 | |
paul@75 | 129 | enum Rgb_mode_values : unsigned |
paul@75 | 130 | { |
paul@75 | 131 | Rgb_mode_565 = 0, |
paul@75 | 132 | Rgb_mode_555 = 1, |
paul@75 | 133 | Rgb_mode_mask = 0x1, |
paul@75 | 134 | }; |
paul@75 | 135 | |
paul@75 | 136 | enum Frc_algorithm_values : unsigned |
paul@75 | 137 | { |
paul@75 | 138 | Frc_greyscales_16 = 0, |
paul@75 | 139 | Frc_greyscales_4 = 1, |
paul@75 | 140 | Frc_greyscales_2 = 2, |
paul@75 | 141 | Frc_greyscales_mask = 0x3, |
paul@75 | 142 | }; |
paul@75 | 143 | |
paul@75 | 144 | enum Control_bpp_values : unsigned |
paul@75 | 145 | { |
paul@75 | 146 | Control_bpp_1bpp = 0, |
paul@75 | 147 | Control_bpp_2bpp = 1, |
paul@75 | 148 | Control_bpp_4bpp = 2, |
paul@75 | 149 | Control_bpp_8bpp = 3, |
paul@75 | 150 | Control_bpp_15bpp = 4, |
paul@75 | 151 | Control_bpp_16bpp = 4, |
paul@75 | 152 | Control_bpp_18bpp = 5, |
paul@75 | 153 | Control_bpp_24bpp = 5, |
paul@75 | 154 | Control_bpp_24bpp_comp = 6, |
paul@75 | 155 | Control_bpp_30bpp = 7, |
paul@75 | 156 | Control_bpp_32bpp = 7, |
paul@75 | 157 | Control_bpp_mask = 0x7, |
paul@75 | 158 | }; |
paul@75 | 159 | |
paul@75 | 160 | // Command descriptions. |
paul@75 | 161 | |
paul@75 | 162 | enum Command_bits : unsigned |
paul@75 | 163 | { |
paul@75 | 164 | Command_frame_start_irq = 31, // SOFINT (start of frame interrupt) |
paul@75 | 165 | Command_frame_end_irq = 30, // EOFINT (end of frame interrupt) |
paul@75 | 166 | Command_lcm_command = 29, // JZ4780: CMD (LCM command/data via DMA0) |
paul@75 | 167 | Command_palette_buffer = 28, // PAL (descriptor references palette, not display data) |
paul@75 | 168 | Command_frame_compressed = 27, // JZ4780: COMPEN (16/24bpp compression enabled) |
paul@75 | 169 | Command_frame_enable = 26, // JZ4780: FRM_EN |
paul@75 | 170 | Command_field_even = 25, // JZ4780: FIELD_SEL (interlace even field) |
paul@75 | 171 | Command_16x16_block = 24, // JZ4780: 16x16BLOCK (fetch data by 16x16 block) |
paul@75 | 172 | Command_buffer_length = 0, // LEN |
paul@75 | 173 | }; |
paul@75 | 174 | |
paul@75 | 175 | enum Command_values : unsigned |
paul@75 | 176 | { |
paul@75 | 177 | Command_buffer_length_mask = 0x00ffffff, |
paul@75 | 178 | }; |
paul@75 | 179 | |
paul@75 | 180 | // Status descriptions. |
paul@75 | 181 | |
paul@75 | 182 | enum Status_bits : unsigned |
paul@75 | 183 | { |
paul@75 | 184 | Status_frame_end_irq = 5, |
paul@75 | 185 | Status_frame_start_irq = 4, |
paul@75 | 186 | Status_out_underrun_irq = 3, |
paul@75 | 187 | Status_in0_underrun_irq = 2, |
paul@75 | 188 | Status_in1_underrun_irq = 1, |
paul@75 | 189 | Status_disabled = 0, |
paul@75 | 190 | }; |
paul@75 | 191 | |
paul@75 | 192 | // OSD configuration bits (JZ4780). |
paul@75 | 193 | |
paul@75 | 194 | enum Osd_config_bits : unsigned |
paul@75 | 195 | { |
paul@75 | 196 | Osd_config_fg1_pixel_alpha_enable = 17, |
paul@75 | 197 | Osd_config_fg1_frame_start_irq_enable = 15, |
paul@75 | 198 | Osd_config_fg1_frame_end_irq_enable = 14, |
paul@75 | 199 | Osd_config_fg0_frame_start_irq_enable = 11, |
paul@75 | 200 | Osd_config_fg0_frame_end_irq_enable = 10, |
paul@75 | 201 | Osd_config_fg1_enable = 4, |
paul@75 | 202 | Osd_config_fg0_enable = 3, |
paul@75 | 203 | Osd_config_alpha_enable = 2, |
paul@75 | 204 | Osd_config_fg0_pixel_alpha_enable = 1, |
paul@75 | 205 | Osd_config_enable = 0, |
paul@75 | 206 | }; |
paul@75 | 207 | |
paul@75 | 208 | enum Osd_control_bits : unsigned |
paul@75 | 209 | { |
paul@75 | 210 | Osd_control_ipu_clock_enable = 15, |
paul@75 | 211 | }; |
paul@75 | 212 | |
paul@75 | 213 | // RGB control (JZ4780). |
paul@75 | 214 | |
paul@75 | 215 | enum Rgb_control_bits : unsigned |
paul@75 | 216 | { |
paul@75 | 217 | Rgb_data_padded = 15, // RGBDM |
paul@75 | 218 | Rgb_padding_mode = 14, // DMM |
paul@75 | 219 | Rgb_422 = 8, // 422 |
paul@75 | 220 | Rgb_format_enable = 7, // RGBFMT |
paul@75 | 221 | Rgb_odd_line = 4, // OddRGB |
paul@75 | 222 | Rgb_even_line = 0, // EvenRGB |
paul@75 | 223 | }; |
paul@75 | 224 | |
paul@75 | 225 | enum Rgb_control_values : unsigned |
paul@75 | 226 | { |
paul@75 | 227 | Rgb_padding_end = 0U << Rgb_padding_mode, |
paul@75 | 228 | Rgb_padding_start = 1U << Rgb_padding_mode, |
paul@75 | 229 | Rgb_odd_line_rgb = 0U << Rgb_odd_line, |
paul@75 | 230 | Rgb_odd_line_rbg = 1U << Rgb_odd_line, |
paul@75 | 231 | Rgb_odd_line_grb = 2U << Rgb_odd_line, |
paul@75 | 232 | Rgb_odd_line_gbr = 3U << Rgb_odd_line, |
paul@75 | 233 | Rgb_odd_line_brg = 4U << Rgb_odd_line, |
paul@75 | 234 | Rgb_odd_line_bgr = 5U << Rgb_odd_line, |
paul@75 | 235 | Rgb_even_line_rgb = 0U << Rgb_even_line, |
paul@75 | 236 | Rgb_even_line_rbg = 1U << Rgb_even_line, |
paul@75 | 237 | Rgb_even_line_grb = 2U << Rgb_even_line, |
paul@75 | 238 | Rgb_even_line_gbr = 3U << Rgb_even_line, |
paul@75 | 239 | Rgb_even_line_brg = 4U << Rgb_even_line, |
paul@75 | 240 | Rgb_even_line_bgr = 5U << Rgb_even_line, |
paul@75 | 241 | }; |
paul@75 | 242 | |
paul@75 | 243 | // Alpha levels (JZ4780). |
paul@75 | 244 | |
paul@75 | 245 | enum Alpha_levels_bits : unsigned |
paul@75 | 246 | { |
paul@75 | 247 | Alpha_level_fg1 = 8, |
paul@75 | 248 | Alpha_level_fg0 = 0, |
paul@75 | 249 | }; |
paul@75 | 250 | |
paul@75 | 251 | enum Alpha_levels_values : unsigned |
paul@75 | 252 | { |
paul@75 | 253 | Alpha_level_fg1_mask = 0x0000ff00, |
paul@75 | 254 | Alpha_level_fg0_mask = 0x000000ff, |
paul@75 | 255 | }; |
paul@75 | 256 | |
paul@75 | 257 | // Priority level. |
paul@75 | 258 | |
paul@75 | 259 | enum Priority_level_bits : unsigned |
paul@75 | 260 | { |
paul@75 | 261 | Priority_mode = 31, |
paul@75 | 262 | Priority_highest_burst = 28, |
paul@75 | 263 | Priority_threshold2 = 18, |
paul@75 | 264 | Priority_threshold1 = 9, |
paul@75 | 265 | Priority_threshold0 = 0, |
paul@75 | 266 | }; |
paul@75 | 267 | |
paul@75 | 268 | enum Priority_level_values : unsigned |
paul@75 | 269 | { |
paul@75 | 270 | Priority_mode_dynamic = 0U << Priority_mode, |
paul@75 | 271 | Priority_mode_arbiter = 1U << Priority_mode, |
paul@75 | 272 | }; |
paul@75 | 273 | |
paul@75 | 274 | enum Priority_burst_values : unsigned |
paul@75 | 275 | { |
paul@75 | 276 | Priority_burst_4 = 0, |
paul@75 | 277 | Priority_burst_8 = 1, |
paul@75 | 278 | Priority_burst_16 = 2, |
paul@75 | 279 | Priority_burst_32 = 3, |
paul@75 | 280 | Priority_burst_64 = 4, |
paul@75 | 281 | Priority_burst_16_cont = 5, |
paul@75 | 282 | Priority_burst_disable = 7, |
paul@75 | 283 | }; |
paul@75 | 284 | |
paul@75 | 285 | // Position descriptor member. |
paul@75 | 286 | |
paul@75 | 287 | enum Position_bits : unsigned |
paul@75 | 288 | { |
paul@75 | 289 | Position_bpp = 27, |
paul@75 | 290 | Position_premultiply_lcd = 26, |
paul@75 | 291 | Position_coefficient = 24, |
paul@75 | 292 | Position_y_position = 12, |
paul@75 | 293 | Position_x_position = 0, |
paul@75 | 294 | }; |
paul@75 | 295 | |
paul@75 | 296 | enum Position_values : unsigned |
paul@75 | 297 | { |
paul@75 | 298 | Position_bpp_15_16bpp = 4, |
paul@75 | 299 | Position_bpp_18_24bpp = 5, |
paul@75 | 300 | Position_bpp_30bpp = 7, |
paul@75 | 301 | }; |