paul@160 | 1 | /* |
paul@160 | 2 | * Clock and power management. This exposes the combined functionality |
paul@160 | 3 | * provided by the X1600 and related SoCs. The power management |
paul@160 | 4 | * functionality could be exposed using a separate driver. |
paul@160 | 5 | * |
paul@160 | 6 | * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@160 | 7 | * |
paul@160 | 8 | * This program is free software; you can redistribute it and/or |
paul@160 | 9 | * modify it under the terms of the GNU General Public License as |
paul@160 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@160 | 11 | * the License, or (at your option) any later version. |
paul@160 | 12 | * |
paul@160 | 13 | * This program is distributed in the hope that it will be useful, |
paul@160 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@160 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@160 | 16 | * GNU General Public License for more details. |
paul@160 | 17 | * |
paul@160 | 18 | * You should have received a copy of the GNU General Public License |
paul@160 | 19 | * along with this program; if not, write to the Free Software |
paul@160 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@160 | 21 | * Boston, MA 02110-1301, USA |
paul@160 | 22 | */ |
paul@160 | 23 | |
paul@160 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@160 | 25 | #include "cpm-x1600.h" |
paul@160 | 26 | #include <math.h> |
paul@161 | 27 | #include <stdio.h> |
paul@160 | 28 | |
paul@160 | 29 | |
paul@160 | 30 | |
paul@161 | 31 | // Register locations. |
paul@161 | 32 | |
paul@160 | 33 | enum Regs : unsigned |
paul@160 | 34 | { |
paul@160 | 35 | Clock_control = 0x000, // CPCCR |
paul@160 | 36 | Low_power_control = 0x004, // LCR |
paul@160 | 37 | Clock_gate0 = 0x020, // CLKGR0 |
paul@160 | 38 | Clock_gate1 = 0x028, // CLKGR1 |
paul@160 | 39 | Sleep_control = 0x024, // OPCR (oscillator and power control) |
paul@160 | 40 | Clock_status = 0x0d4, // CPCSR |
paul@167 | 41 | Divider_ddr = 0x02c, // DDRCDR |
paul@167 | 42 | Divider_mac = 0x054, // MACCDR |
paul@167 | 43 | Divider0_i2s0 = 0x060, // I2SCDR |
paul@167 | 44 | Divider1_i2s0 = 0x070, // I2S1CDR |
paul@167 | 45 | Divider_lcd = 0x064, // LPCDR |
paul@167 | 46 | Divider_msc0 = 0x068, // MSC0CDR |
paul@167 | 47 | Divider_msc1 = 0x0a4, // MSC1CDR |
paul@167 | 48 | Divider_sfc = 0x074, // SFCCDR |
paul@167 | 49 | Divider_ssi = 0x05c, // SSICDR |
paul@167 | 50 | Divider_cim = 0x078, // CIMCDR |
paul@167 | 51 | Divider_pwm = 0x06c, // PWMCDR |
paul@167 | 52 | Divider_can0 = 0x0a0, // CAN0CDR |
paul@167 | 53 | Divider_can1 = 0x0a8, // CAN1CDR |
paul@167 | 54 | Divider_cdbus = 0x0ac, // CDBUSCDR |
paul@167 | 55 | Divider_macphy0 = 0x0e4, // MPHY0C |
paul@160 | 56 | Cpm_interrupt = 0x0b0, // CPM_INTR |
paul@160 | 57 | Cpm_interrupt_en = 0x0b4, // CPM_INTRE |
paul@160 | 58 | Cpm_swi = 0x0bc, // CPM_SFTINT |
paul@160 | 59 | Ddr_gate = 0x0d0, // DRCG |
paul@160 | 60 | Cpm_scratch_prot = 0x038, // CPSPPR |
paul@160 | 61 | Cpm_scratch = 0x034, // CPSPR |
paul@160 | 62 | Usb_param_control0 = 0x03c, // USBPCR |
paul@160 | 63 | Usb_reset_detect = 0x040, // USBRDT |
paul@160 | 64 | Usb_vbus_jitter = 0x044, // USBVBFIL |
paul@160 | 65 | Usb_param_control1 = 0x048, // USBPCR1 |
paul@160 | 66 | Pll_control = 0x00c, // CPPCR |
paul@160 | 67 | Pll_control_A = 0x010, // CPAPCR |
paul@160 | 68 | Pll_control_M = 0x014, // CPMPCR |
paul@160 | 69 | Pll_control_E = 0x018, // CPEPCR |
paul@160 | 70 | Pll_fraction_A = 0x084, // CPAPACR |
paul@160 | 71 | Pll_fraction_M = 0x088, // CPMPACR |
paul@160 | 72 | Pll_fraction_E = 0x08c, // CPEPACR |
paul@160 | 73 | }; |
paul@160 | 74 | |
paul@161 | 75 | enum Clock_source_values : unsigned |
paul@160 | 76 | { |
paul@161 | 77 | Source_mME_main = 0, |
paul@161 | 78 | Source_mME_pll_M = 1, |
paul@161 | 79 | Source_mME_pll_E = 2, |
paul@160 | 80 | |
paul@161 | 81 | // Special value |
paul@160 | 82 | |
paul@161 | 83 | Source_mask = 0x3, |
paul@160 | 84 | }; |
paul@160 | 85 | |
paul@160 | 86 | |
paul@160 | 87 | |
paul@166 | 88 | // Register field abstraction. |
paul@166 | 89 | |
paul@166 | 90 | class Field |
paul@166 | 91 | { |
paul@166 | 92 | uint32_t reg; |
paul@166 | 93 | uint32_t mask; |
paul@166 | 94 | uint8_t bit; |
paul@166 | 95 | bool defined; |
paul@166 | 96 | |
paul@166 | 97 | public: |
paul@166 | 98 | explicit Field() |
paul@166 | 99 | : defined(false) |
paul@166 | 100 | { |
paul@166 | 101 | } |
paul@166 | 102 | |
paul@166 | 103 | explicit Field(uint32_t reg, uint32_t mask, uint32_t bit) |
paul@166 | 104 | : reg(reg), mask(mask), bit(bit), defined(true) |
paul@166 | 105 | { |
paul@166 | 106 | } |
paul@166 | 107 | |
paul@166 | 108 | uint32_t get_field(Cpm_regs ®s); |
paul@166 | 109 | void set_field(Cpm_regs ®s, uint32_t value); |
paul@166 | 110 | bool is_defined() { return defined; } |
paul@166 | 111 | }; |
paul@166 | 112 | |
paul@166 | 113 | // Undefined fields. |
paul@166 | 114 | |
paul@166 | 115 | Field Source_undefined, Gate_undefined, Change_enable_undefined, Busy_undefined, Divider_undefined; |
paul@166 | 116 | |
paul@166 | 117 | |
paul@166 | 118 | |
paul@169 | 119 | // Clock sources. |
paul@169 | 120 | |
paul@169 | 121 | class Mux |
paul@169 | 122 | { |
paul@169 | 123 | int _num_inputs; |
paul@169 | 124 | enum Clock_identifiers *_inputs; |
paul@169 | 125 | |
paul@169 | 126 | public: |
paul@169 | 127 | explicit Mux(int num_inputs = 0, enum Clock_identifiers inputs[] = NULL) |
paul@169 | 128 | : _num_inputs(num_inputs), _inputs(inputs) |
paul@169 | 129 | { |
paul@169 | 130 | } |
paul@169 | 131 | |
paul@169 | 132 | int get_number() { return _num_inputs; } |
paul@169 | 133 | enum Clock_identifiers get_input(int num); |
paul@169 | 134 | }; |
paul@169 | 135 | |
paul@169 | 136 | // Undefined sources. |
paul@169 | 137 | |
paul@169 | 138 | Mux Mux_undefined; |
paul@169 | 139 | |
paul@169 | 140 | |
paul@169 | 141 | |
paul@165 | 142 | // Common clock abstraction. |
paul@165 | 143 | |
paul@165 | 144 | class Clock_base |
paul@165 | 145 | { |
paul@169 | 146 | Mux _inputs; |
paul@166 | 147 | Field _source; |
paul@165 | 148 | |
paul@165 | 149 | public: |
paul@169 | 150 | explicit Clock_base(Mux inputs, |
paul@166 | 151 | Field source = Source_undefined) |
paul@169 | 152 | : _inputs(inputs), _source(source) |
paul@165 | 153 | { |
paul@165 | 154 | } |
paul@165 | 155 | |
paul@165 | 156 | // Clock control. |
paul@165 | 157 | |
paul@165 | 158 | virtual int have_clock(Cpm_regs ®s); |
paul@165 | 159 | virtual void start_clock(Cpm_regs ®s); |
paul@165 | 160 | virtual void stop_clock(Cpm_regs ®s); |
paul@165 | 161 | |
paul@165 | 162 | // Clock divider. |
paul@165 | 163 | |
paul@165 | 164 | virtual uint32_t get_divider(Cpm_regs ®s); |
paul@165 | 165 | virtual void set_divider(Cpm_regs ®s, uint32_t division); |
paul@165 | 166 | |
paul@165 | 167 | // Clock source. |
paul@165 | 168 | |
paul@165 | 169 | virtual uint8_t get_source(Cpm_regs ®s); |
paul@165 | 170 | virtual void set_source(Cpm_regs ®s, uint8_t source); |
paul@165 | 171 | |
paul@165 | 172 | // Clock source frequency. |
paul@165 | 173 | |
paul@165 | 174 | virtual uint32_t get_source_frequency(Cpm_regs ®s); |
paul@165 | 175 | |
paul@165 | 176 | // Output frequency. |
paul@165 | 177 | |
paul@165 | 178 | virtual uint32_t get_frequency(Cpm_regs ®s); |
paul@165 | 179 | }; |
paul@165 | 180 | |
paul@165 | 181 | |
paul@165 | 182 | |
paul@165 | 183 | // PLL descriptions. |
paul@165 | 184 | |
paul@165 | 185 | class Pll : public Clock_base |
paul@165 | 186 | { |
paul@168 | 187 | Field _enable, _stable, _bypass; |
paul@168 | 188 | Field _multiplier, _input_division, _output_division0, _output_division1; |
paul@165 | 189 | |
paul@165 | 190 | public: |
paul@169 | 191 | explicit Pll(Mux inputs, |
paul@168 | 192 | Field enable, Field stable, Field bypass, |
paul@168 | 193 | Field multiplier, Field input_division, |
paul@168 | 194 | Field output_division0, Field output_division1) |
paul@169 | 195 | : Clock_base(inputs), |
paul@168 | 196 | _enable(enable), _stable(stable), _bypass(bypass), |
paul@168 | 197 | _multiplier(multiplier), _input_division(input_division), |
paul@168 | 198 | _output_division0(output_division0), _output_division1(output_division1) |
paul@165 | 199 | { |
paul@165 | 200 | } |
paul@165 | 201 | |
paul@165 | 202 | // PLL_specific control. |
paul@165 | 203 | |
paul@165 | 204 | int have_pll(Cpm_regs ®s); |
paul@165 | 205 | int pll_enabled(Cpm_regs ®s); |
paul@165 | 206 | int pll_bypassed(Cpm_regs ®s); |
paul@165 | 207 | |
paul@165 | 208 | // Clock control. |
paul@165 | 209 | |
paul@165 | 210 | int have_clock(Cpm_regs ®s); |
paul@165 | 211 | void start_clock(Cpm_regs ®s); |
paul@165 | 212 | void stop_clock(Cpm_regs ®s); |
paul@165 | 213 | |
paul@165 | 214 | // General frequency modifiers. |
paul@165 | 215 | |
paul@165 | 216 | uint16_t get_multiplier(Cpm_regs ®s); |
paul@165 | 217 | void set_multiplier(Cpm_regs ®s, uint16_t multiplier); |
paul@165 | 218 | uint8_t get_input_division(Cpm_regs ®s); |
paul@165 | 219 | void set_input_division(Cpm_regs ®s, uint8_t divider); |
paul@165 | 220 | uint8_t get_output_division(Cpm_regs ®s); |
paul@165 | 221 | void set_output_division(Cpm_regs ®s, uint8_t divider); |
paul@165 | 222 | |
paul@165 | 223 | // PLL output frequency. |
paul@165 | 224 | |
paul@165 | 225 | uint32_t get_frequency(Cpm_regs ®s); |
paul@165 | 226 | |
paul@165 | 227 | // Other operations. |
paul@165 | 228 | |
paul@165 | 229 | void set_pll_parameters(Cpm_regs ®s, uint16_t multiplier, |
paul@165 | 230 | uint8_t in_divider, uint8_t out_divider); |
paul@165 | 231 | }; |
paul@165 | 232 | |
paul@165 | 233 | |
paul@165 | 234 | |
paul@161 | 235 | // Clock descriptions. |
paul@161 | 236 | |
paul@165 | 237 | class Clock : public Clock_base |
paul@161 | 238 | { |
paul@166 | 239 | Field _gate, _change_enable, _busy, _divider; |
paul@161 | 240 | |
paul@165 | 241 | // Clock control. |
paul@161 | 242 | |
paul@165 | 243 | void change_disable(Cpm_regs ®s); |
paul@165 | 244 | void change_enable(Cpm_regs ®s); |
paul@165 | 245 | void wait_busy(Cpm_regs ®s); |
paul@161 | 246 | |
paul@165 | 247 | public: |
paul@169 | 248 | explicit Clock(Mux inputs = Mux_undefined, |
paul@166 | 249 | Field source = Source_undefined, |
paul@166 | 250 | Field gate = Gate_undefined, |
paul@166 | 251 | Field change_enable = Change_enable_undefined, |
paul@166 | 252 | Field busy = Busy_undefined, |
paul@166 | 253 | Field divider = Divider_undefined) |
paul@169 | 254 | : Clock_base(inputs, source), |
paul@166 | 255 | _gate(gate), _change_enable(change_enable), _busy(busy), _divider(divider) |
paul@165 | 256 | { |
paul@165 | 257 | } |
paul@161 | 258 | |
paul@165 | 259 | // Clock control. |
paul@161 | 260 | |
paul@165 | 261 | int have_clock(Cpm_regs ®s); |
paul@165 | 262 | void start_clock(Cpm_regs ®s); |
paul@165 | 263 | void stop_clock(Cpm_regs ®s); |
paul@161 | 264 | |
paul@165 | 265 | // Clock divider. |
paul@161 | 266 | |
paul@165 | 267 | uint32_t get_divider(Cpm_regs ®s); |
paul@165 | 268 | void set_divider(Cpm_regs ®s, uint32_t division); |
paul@161 | 269 | |
paul@165 | 270 | // Clock source. |
paul@161 | 271 | |
paul@165 | 272 | void set_source(Cpm_regs ®s, uint8_t source); |
paul@161 | 273 | }; |
paul@161 | 274 | |
paul@161 | 275 | |
paul@161 | 276 | |
paul@167 | 277 | // Register field definitions. |
paul@167 | 278 | |
paul@168 | 279 | Field Clock_source_main (Clock_control, 3, 30); // SEL_SRC (output to SCLK_A) |
paul@168 | 280 | Field Clock_source_cpu (Clock_control, 3, 28); // SEL_CPLL (output to CCLK) |
paul@168 | 281 | Field Clock_source_hclock0 (Clock_control, 3, 26); // SEL_H0PLL (output to AHB0) |
paul@168 | 282 | Field Clock_source_hclock2 (Clock_control, 3, 24); // SEL_H2PLL (output to AHB2) |
paul@168 | 283 | Field Clock_source_can0 (Divider_can0, 3, 30); // CA0CS |
paul@168 | 284 | Field Clock_source_can1 (Divider_can1, 3, 30); // CA1CS |
paul@168 | 285 | Field Clock_source_cdbus (Divider_cdbus, 3, 30); // CDCS |
paul@168 | 286 | Field Clock_source_cim (Divider_cim, 3, 30); // CIMPCS |
paul@168 | 287 | Field Clock_source_ddr (Divider_ddr, 3, 30); // DCS |
paul@168 | 288 | Field Clock_source_i2s (Divider0_i2s0, 1, 31); // I2PCS |
paul@168 | 289 | Field Clock_source_lcd (Divider_lcd, 3, 30); // LPCS |
paul@168 | 290 | Field Clock_source_mac (Divider_mac, 3, 30); // MACPCS |
paul@168 | 291 | Field Clock_source_msc0 (Divider_msc0, 3, 30); // MPCS |
paul@168 | 292 | Field Clock_source_msc1 (Divider_msc1, 3, 30); // MPCS |
paul@168 | 293 | Field Clock_source_pwm (Divider_pwm, 3, 30); // PWMPCS |
paul@168 | 294 | Field Clock_source_sfc (Divider_sfc, 3, 30); // SFCS |
paul@168 | 295 | Field Clock_source_ssi (Divider_ssi, 3, 30); // SPCS |
paul@167 | 296 | |
paul@167 | 297 | Field Clock_busy_cpu (Clock_status, 1, 0); |
paul@167 | 298 | Field Clock_busy_ddr (Divider_ddr, 1, 28); |
paul@167 | 299 | Field Clock_busy_mac (Divider_mac, 1, 28); |
paul@167 | 300 | Field Clock_busy_lcd (Divider_lcd, 1, 28); |
paul@167 | 301 | Field Clock_busy_msc0 (Divider_msc0, 1, 28); |
paul@167 | 302 | Field Clock_busy_msc1 (Divider_msc1, 1, 28); |
paul@167 | 303 | Field Clock_busy_sfc (Divider_sfc, 1, 28); |
paul@167 | 304 | Field Clock_busy_ssi (Divider_ssi, 1, 28); |
paul@167 | 305 | Field Clock_busy_cim (Divider_cim, 1, 28); |
paul@167 | 306 | Field Clock_busy_pwm (Divider_pwm, 1, 28); |
paul@167 | 307 | Field Clock_busy_can0 (Divider_can0, 1, 28); |
paul@167 | 308 | Field Clock_busy_can1 (Divider_can1, 1, 28); |
paul@167 | 309 | Field Clock_busy_cdbus (Divider_cdbus, 1, 28); |
paul@167 | 310 | |
paul@167 | 311 | Field Clock_change_enable_cpu (Clock_control, 1, 22); |
paul@167 | 312 | Field Clock_change_enable_ahb0 (Clock_control, 1, 21); |
paul@167 | 313 | Field Clock_change_enable_ahb2 (Clock_control, 1, 20); |
paul@167 | 314 | Field Clock_change_enable_ddr (Divider_ddr, 1, 29); |
paul@167 | 315 | Field Clock_change_enable_mac (Divider_mac, 1, 29); |
paul@167 | 316 | Field Clock_change_enable_i2s (Divider0_i2s0, 1, 29); |
paul@167 | 317 | Field Clock_change_enable_lcd (Divider_lcd, 1, 29); |
paul@167 | 318 | Field Clock_change_enable_msc0 (Divider_msc0, 1, 29); |
paul@167 | 319 | Field Clock_change_enable_msc1 (Divider_msc1, 1, 29); |
paul@167 | 320 | Field Clock_change_enable_sfc (Divider_sfc, 1, 29); |
paul@167 | 321 | Field Clock_change_enable_ssi (Divider_ssi, 1, 29); |
paul@167 | 322 | Field Clock_change_enable_cim (Divider_cim, 1, 29); |
paul@167 | 323 | Field Clock_change_enable_pwm (Divider_pwm, 1, 29); |
paul@167 | 324 | Field Clock_change_enable_can0 (Divider_can0, 1, 29); |
paul@167 | 325 | Field Clock_change_enable_can1 (Divider_can1, 1, 29); |
paul@167 | 326 | Field Clock_change_enable_cdbus (Divider_cdbus, 1, 29); |
paul@167 | 327 | |
paul@168 | 328 | Field Clock_divider_can0 (Divider_can0, 0xff, 0); // CAN0CDR |
paul@168 | 329 | Field Clock_divider_can1 (Divider_can1, 0xff, 0); // CAN1CDR |
paul@168 | 330 | Field Clock_divider_cdbus (Divider_cdbus, 0xff, 0); // CDBUSCDR |
paul@168 | 331 | Field Clock_divider_cim (Divider_cim, 0xff, 0); // CIMCDR |
paul@168 | 332 | Field Clock_divider_cpu (Clock_control, 0x0f, 0); // CDIV |
paul@168 | 333 | Field Clock_divider_ddr (Divider_ddr, 0x0f, 0); // DDRCDR |
paul@168 | 334 | Field Clock_divider_hclock0 (Clock_control, 0x0f, 8); // H0DIV (fast AHB peripherals) |
paul@168 | 335 | Field Clock_divider_hclock2 (Clock_control, 0x0f, 12); // H2DIV (fast AHB peripherals) |
paul@168 | 336 | Field Clock_divider_l2cache (Clock_control, 0x0f, 4); // L2CDIV |
paul@168 | 337 | Field Clock_divider_lcd (Divider_lcd, 0xff, 0); // LPCDR |
paul@168 | 338 | Field Clock_divider_mac (Divider_mac, 0xff, 0); // MACCDR |
paul@168 | 339 | Field Clock_divider_msc0 (Divider_msc0, 0xff, 0); // MSC0CDR |
paul@168 | 340 | Field Clock_divider_msc1 (Divider_msc1, 0xff, 0); // MSC1CDR |
paul@168 | 341 | Field Clock_divider_pclock (Clock_control, 0x0f, 16); // PDIV (slow APB peripherals) |
paul@168 | 342 | Field Clock_divider_pwm (Divider_pwm, 0x0f, 0); // PWMCDR |
paul@168 | 343 | Field Clock_divider_sfc (Divider_sfc, 0xff, 0); // SFCCDR |
paul@168 | 344 | Field Clock_divider_ssi (Divider_ssi, 0xff, 0); // SSICDR |
paul@167 | 345 | |
paul@168 | 346 | Field Clock_gate_main (Clock_control, 1, 23); // GATE_SCLKA |
paul@168 | 347 | Field Clock_gate_ddr (Clock_gate0, 1, 31); // DDR |
paul@168 | 348 | Field Clock_gate_ahb0 (Clock_gate0, 1, 29); // AHB0 |
paul@168 | 349 | Field Clock_gate_apb0 (Clock_gate0, 1, 28); // APB0 |
paul@168 | 350 | Field Clock_gate_rtc (Clock_gate0, 1, 27); // RTC |
paul@168 | 351 | Field Clock_gate_aes (Clock_gate0, 1, 24); // AES |
paul@168 | 352 | Field Clock_gate_lcd_pixel (Clock_gate0, 1, 23); // LCD |
paul@168 | 353 | Field Clock_gate_cim (Clock_gate0, 1, 22); // CIM |
paul@168 | 354 | Field Clock_gate_dma (Clock_gate0, 1, 21); // PDMA |
paul@168 | 355 | Field Clock_gate_ost (Clock_gate0, 1, 20); // OST |
paul@168 | 356 | Field Clock_gate_ssi0 (Clock_gate0, 1, 19); // SSI0 |
paul@168 | 357 | Field Clock_gate_timer (Clock_gate0, 1, 18); // TCU |
paul@168 | 358 | Field Clock_gate_dtrng (Clock_gate0, 1, 17); // DTRNG |
paul@168 | 359 | Field Clock_gate_uart2 (Clock_gate0, 1, 16); // UART2 |
paul@168 | 360 | Field Clock_gate_uart1 (Clock_gate0, 1, 15); // UART1 |
paul@168 | 361 | Field Clock_gate_uart0 (Clock_gate0, 1, 14); // UART0 |
paul@168 | 362 | Field Clock_gate_sadc (Clock_gate0, 1, 13); // SADC |
paul@168 | 363 | Field Clock_gate_audio (Clock_gate0, 1, 11); // AUDIO |
paul@168 | 364 | Field Clock_gate_ssi_slv (Clock_gate0, 1, 10); // SSI_SLV |
paul@168 | 365 | Field Clock_gate_i2c1 (Clock_gate0, 1, 8); // I2C1 |
paul@168 | 366 | Field Clock_gate_i2c0 (Clock_gate0, 1, 7); // I2C0 |
paul@168 | 367 | Field Clock_gate_msc1 (Clock_gate0, 1, 5); // MSC1 |
paul@168 | 368 | Field Clock_gate_msc0 (Clock_gate0, 1, 4); // MSC0 |
paul@168 | 369 | Field Clock_gate_otg (Clock_gate0, 1, 3); // OTG |
paul@168 | 370 | Field Clock_gate_sfc (Clock_gate0, 1, 2); // SFC |
paul@168 | 371 | Field Clock_gate_efuse (Clock_gate0, 1, 1); // EFUSE |
paul@168 | 372 | Field Clock_gate_nemc (Clock_gate0, 1, 0); // NEMC |
paul@168 | 373 | Field Clock_gate_arb (Clock_gate1, 1, 30); // ARB |
paul@168 | 374 | Field Clock_gate_mipi_csi (Clock_gate1, 1, 28); // MIPI_CSI |
paul@168 | 375 | Field Clock_gate_intc (Clock_gate1, 1, 26); // INTC |
paul@168 | 376 | Field Clock_gate_gmac0 (Clock_gate1, 1, 23); // GMAC0 |
paul@168 | 377 | Field Clock_gate_uart3 (Clock_gate1, 1, 16); // UART3 |
paul@168 | 378 | Field Clock_gate_i2s0_tx (Clock_gate1, 1, 9); // I2S0_dev_tclk |
paul@168 | 379 | Field Clock_gate_i2s0_rx (Clock_gate1, 1, 8); // I2S0_dev_rclk |
paul@168 | 380 | Field Clock_gate_hash (Clock_gate1, 1, 6); // HASH |
paul@168 | 381 | Field Clock_gate_pwm (Clock_gate1, 1, 5); // PWM |
paul@168 | 382 | Field Clock_gate_cdbus (Clock_gate1, 1, 2); // CDBUS |
paul@168 | 383 | Field Clock_gate_can1 (Clock_gate1, 1, 1); // CAN1 |
paul@168 | 384 | Field Clock_gate_can0 (Clock_gate1, 1, 0); // CAN0 |
paul@168 | 385 | |
paul@168 | 386 | Field Pll_enable_A (Pll_control_A, 1, 0); // APLLEN |
paul@168 | 387 | Field Pll_enable_E (Pll_control_E, 1, 0); // EPLLEN |
paul@168 | 388 | Field Pll_enable_M (Pll_control_M, 1, 0); // MPLLEN |
paul@168 | 389 | |
paul@168 | 390 | Field Pll_stable_A (Pll_control_A, 1, 3); // APLL_ON |
paul@168 | 391 | Field Pll_stable_E (Pll_control_E, 1, 3); // EPLL_ON |
paul@168 | 392 | Field Pll_stable_M (Pll_control_M, 1, 3); // MPLL_ON |
paul@168 | 393 | |
paul@168 | 394 | Field Pll_bypass_A (Pll_control_A, 1, 30); // APLL_BP |
paul@168 | 395 | Field Pll_bypass_E (Pll_control_E, 1, 26); // EPLL_BP |
paul@168 | 396 | Field Pll_bypass_M (Pll_control_M, 1, 28); // MPLL_BP |
paul@168 | 397 | |
paul@168 | 398 | Field Pll_multiplier_A (Pll_control_A, 0x1fff, 20); // APLLM |
paul@168 | 399 | Field Pll_multiplier_E (Pll_control_E, 0x1fff, 20); // EPLLM |
paul@168 | 400 | Field Pll_multiplier_M (Pll_control_M, 0x1fff, 20); // MPLLM |
paul@168 | 401 | |
paul@168 | 402 | Field Pll_input_division_A (Pll_control_A, 0x3f, 14); // APLLN |
paul@168 | 403 | Field Pll_input_division_E (Pll_control_E, 0x3f, 14); // EPLLN |
paul@168 | 404 | Field Pll_input_division_M (Pll_control_M, 0x3f, 14); // MPLLN |
paul@168 | 405 | |
paul@168 | 406 | Field Pll_output_division1_A (Pll_control_A, 0x07, 11); // APLLOD1 |
paul@168 | 407 | Field Pll_output_division1_E (Pll_control_E, 0x07, 11); // EPLLOD1 |
paul@168 | 408 | Field Pll_output_division1_M (Pll_control_M, 0x07, 11); // MPLLOD1 |
paul@168 | 409 | |
paul@168 | 410 | Field Pll_output_division0_A (Pll_control_A, 0x07, 8); // APLLOD0 |
paul@168 | 411 | Field Pll_output_division0_E (Pll_control_E, 0x07, 8); // EPLLOD0 |
paul@168 | 412 | Field Pll_output_division0_M (Pll_control_M, 0x07, 8); // MPLLOD0 |
paul@167 | 413 | |
paul@167 | 414 | |
paul@167 | 415 | |
paul@169 | 416 | // Multiplexer instances. |
paul@169 | 417 | |
paul@169 | 418 | #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__}) |
paul@169 | 419 | |
paul@169 | 420 | Mux mux_external(1, Clocks(Clock_external)); |
paul@169 | 421 | |
paul@169 | 422 | Mux mux_core(3, Clocks(Clock_none, Clock_main, Clock_pll_M)); |
paul@169 | 423 | |
paul@169 | 424 | Mux mux_bus(4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)); |
paul@169 | 425 | |
paul@169 | 426 | Mux mux_dev(3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)); |
paul@169 | 427 | |
paul@169 | 428 | Mux mux_pclock(1, Clocks(Clock_pclock)); |
paul@169 | 429 | |
paul@169 | 430 | Mux mux_ahb2_apb(1, Clocks(Clock_ahb2_apb)); |
paul@169 | 431 | |
paul@169 | 432 | Mux mux_i2s(2, Clocks(Clock_main, Clock_pll_E)); |
paul@169 | 433 | |
paul@169 | 434 | |
paul@169 | 435 | |
paul@165 | 436 | // Clock instances. |
paul@165 | 437 | |
paul@169 | 438 | Clock clock_ahb2_apb(mux_core, Clock_source_hclock2); |
paul@165 | 439 | |
paul@165 | 440 | Clock clock_aic_bitclk; |
paul@165 | 441 | |
paul@165 | 442 | Clock clock_aic_pclk; |
paul@165 | 443 | |
paul@169 | 444 | Clock clock_can0(mux_bus, |
paul@167 | 445 | Clock_source_can0, |
paul@167 | 446 | Clock_gate_can0, |
paul@167 | 447 | Clock_change_enable_can0, |
paul@167 | 448 | Clock_busy_can0, |
paul@167 | 449 | Clock_divider_can0); |
paul@165 | 450 | |
paul@169 | 451 | Clock clock_can1(mux_bus, |
paul@167 | 452 | Clock_source_can1, |
paul@167 | 453 | Clock_gate_can1, |
paul@167 | 454 | Clock_change_enable_can1, |
paul@167 | 455 | Clock_busy_can1, |
paul@167 | 456 | Clock_divider_can1); |
paul@165 | 457 | |
paul@169 | 458 | Clock clock_cdbus(mux_dev, |
paul@167 | 459 | Clock_source_cdbus, |
paul@167 | 460 | Clock_gate_cdbus, |
paul@167 | 461 | Clock_change_enable_cdbus, |
paul@167 | 462 | Clock_busy_cdbus, |
paul@167 | 463 | Clock_divider_cdbus); |
paul@165 | 464 | |
paul@169 | 465 | Clock clock_cim(mux_dev, |
paul@167 | 466 | Clock_source_cim, |
paul@167 | 467 | Clock_gate_cim, |
paul@167 | 468 | Clock_change_enable_cim, |
paul@167 | 469 | Clock_busy_cim, |
paul@167 | 470 | Clock_divider_cim); |
paul@165 | 471 | |
paul@169 | 472 | Clock clock_cpu(mux_core, |
paul@167 | 473 | Clock_source_cpu, |
paul@166 | 474 | Gate_undefined, |
paul@167 | 475 | Clock_change_enable_cpu, |
paul@167 | 476 | Clock_busy_cpu, |
paul@167 | 477 | Clock_divider_cpu); |
paul@165 | 478 | |
paul@169 | 479 | Clock clock_ddr(mux_core, |
paul@167 | 480 | Clock_source_ddr, |
paul@167 | 481 | Clock_gate_ddr, |
paul@167 | 482 | Clock_change_enable_ddr, |
paul@167 | 483 | Clock_busy_ddr, |
paul@167 | 484 | Clock_divider_ddr); |
paul@165 | 485 | |
paul@169 | 486 | Clock clock_dma(mux_pclock, Source_undefined, Clock_gate_dma); |
paul@165 | 487 | |
paul@165 | 488 | Clock clock_emac; |
paul@165 | 489 | |
paul@165 | 490 | Clock clock_external; |
paul@165 | 491 | |
paul@169 | 492 | Clock clock_hclock0(mux_core, |
paul@167 | 493 | Clock_source_hclock0, |
paul@167 | 494 | Clock_gate_ahb0, |
paul@167 | 495 | Clock_change_enable_ahb0, |
paul@166 | 496 | Busy_undefined, |
paul@167 | 497 | Clock_divider_hclock0); |
paul@165 | 498 | |
paul@169 | 499 | Clock clock_hclock2(mux_ahb2_apb, |
paul@166 | 500 | Source_undefined, |
paul@167 | 501 | Clock_gate_apb0, |
paul@167 | 502 | Clock_change_enable_ahb2, |
paul@166 | 503 | Busy_undefined, |
paul@167 | 504 | Clock_divider_hclock2); |
paul@165 | 505 | |
paul@165 | 506 | Clock clock_hdmi; |
paul@165 | 507 | |
paul@169 | 508 | Clock clock_i2c(mux_pclock, |
paul@166 | 509 | Source_undefined, |
paul@167 | 510 | Clock_gate_i2c0); |
paul@165 | 511 | |
paul@169 | 512 | Clock clock_i2c0(mux_pclock, |
paul@166 | 513 | Source_undefined, |
paul@167 | 514 | Clock_gate_i2c0); |
paul@165 | 515 | |
paul@169 | 516 | Clock clock_i2c1(mux_pclock, |
paul@166 | 517 | Source_undefined, |
paul@167 | 518 | Clock_gate_i2c1); |
paul@165 | 519 | |
paul@165 | 520 | Clock clock_i2s; |
paul@165 | 521 | |
paul@169 | 522 | Clock clock_i2s0_rx(mux_i2s, |
paul@167 | 523 | Clock_source_i2s, |
paul@167 | 524 | Clock_gate_i2s0_rx, |
paul@167 | 525 | Clock_change_enable_i2s); |
paul@165 | 526 | |
paul@169 | 527 | Clock clock_i2s0_tx(mux_i2s, |
paul@167 | 528 | Clock_source_i2s, |
paul@167 | 529 | Clock_gate_i2s0_tx, |
paul@167 | 530 | Clock_change_enable_i2s); |
paul@165 | 531 | |
paul@165 | 532 | Clock clock_kbc; |
paul@165 | 533 | |
paul@165 | 534 | Clock clock_lcd; |
paul@165 | 535 | |
paul@169 | 536 | Clock clock_lcd_pixel(mux_dev, |
paul@167 | 537 | Clock_source_lcd, |
paul@167 | 538 | Clock_gate_lcd_pixel, |
paul@167 | 539 | Clock_change_enable_lcd, |
paul@167 | 540 | Clock_busy_lcd, |
paul@167 | 541 | Clock_divider_lcd); |
paul@165 | 542 | |
paul@169 | 543 | Clock clock_mac(mux_dev, |
paul@167 | 544 | Clock_source_mac, |
paul@167 | 545 | Clock_gate_gmac0, |
paul@167 | 546 | Clock_change_enable_mac, |
paul@167 | 547 | Clock_busy_mac, |
paul@167 | 548 | Clock_divider_mac); |
paul@165 | 549 | |
paul@169 | 550 | Clock clock_main(mux_core, |
paul@167 | 551 | Clock_source_main, |
paul@167 | 552 | Clock_gate_main); |
paul@165 | 553 | |
paul@169 | 554 | Clock clock_msc(mux_dev, |
paul@167 | 555 | Clock_source_msc0, |
paul@167 | 556 | Clock_gate_msc0, |
paul@167 | 557 | Clock_change_enable_msc0, |
paul@167 | 558 | Clock_busy_msc0, |
paul@167 | 559 | Clock_divider_msc0); |
paul@165 | 560 | |
paul@169 | 561 | Clock clock_msc0(mux_dev, |
paul@167 | 562 | Clock_source_msc0, |
paul@167 | 563 | Clock_gate_msc0, |
paul@167 | 564 | Clock_change_enable_msc0, |
paul@167 | 565 | Clock_busy_msc0, |
paul@167 | 566 | Clock_divider_msc0); |
paul@165 | 567 | |
paul@169 | 568 | Clock clock_msc1(mux_dev, |
paul@167 | 569 | Clock_source_msc1, |
paul@167 | 570 | Clock_gate_msc1, |
paul@167 | 571 | Clock_change_enable_msc1, |
paul@167 | 572 | Clock_busy_msc1, |
paul@167 | 573 | Clock_divider_msc1); |
paul@165 | 574 | |
paul@165 | 575 | Clock clock_none; |
paul@161 | 576 | |
paul@169 | 577 | Clock clock_pclock(mux_ahb2_apb, |
paul@166 | 578 | Source_undefined, |
paul@167 | 579 | Clock_gate_apb0, |
paul@166 | 580 | Change_enable_undefined, |
paul@166 | 581 | Busy_undefined, |
paul@167 | 582 | Clock_divider_pclock); |
paul@165 | 583 | |
paul@169 | 584 | Pll clock_pll_A(mux_external, |
paul@168 | 585 | Pll_enable_A, Pll_stable_A, Pll_bypass_A, |
paul@168 | 586 | Pll_multiplier_A, Pll_input_division_A, |
paul@168 | 587 | Pll_output_division0_A, Pll_output_division1_A); |
paul@165 | 588 | |
paul@169 | 589 | Pll clock_pll_E(mux_external, |
paul@168 | 590 | Pll_enable_E, Pll_stable_E, Pll_bypass_E, |
paul@168 | 591 | Pll_multiplier_E, Pll_input_division_E, |
paul@168 | 592 | Pll_output_division0_E, Pll_output_division1_E); |
paul@165 | 593 | |
paul@169 | 594 | Pll clock_pll_M(mux_external, |
paul@168 | 595 | Pll_enable_M, Pll_stable_M, Pll_bypass_M, |
paul@168 | 596 | Pll_multiplier_M, Pll_input_division_M, |
paul@168 | 597 | Pll_output_division0_M, Pll_output_division1_M); |
paul@165 | 598 | |
paul@169 | 599 | Clock clock_pwm(mux_dev, |
paul@167 | 600 | Clock_source_pwm, |
paul@167 | 601 | Clock_gate_pwm, |
paul@167 | 602 | Clock_change_enable_pwm, |
paul@167 | 603 | Clock_busy_pwm, |
paul@167 | 604 | Clock_divider_pwm); |
paul@165 | 605 | |
paul@169 | 606 | Clock clock_pwm0(mux_dev, |
paul@167 | 607 | Clock_source_pwm, |
paul@167 | 608 | Clock_gate_pwm, |
paul@167 | 609 | Clock_change_enable_pwm, |
paul@167 | 610 | Clock_busy_pwm, |
paul@167 | 611 | Clock_divider_pwm); |
paul@165 | 612 | |
paul@165 | 613 | Clock clock_pwm1; |
paul@165 | 614 | |
paul@165 | 615 | Clock clock_scc; |
paul@165 | 616 | |
paul@169 | 617 | Clock clock_sfc(mux_dev, |
paul@167 | 618 | Clock_source_sfc, |
paul@167 | 619 | Clock_gate_sfc, |
paul@167 | 620 | Clock_change_enable_sfc, |
paul@167 | 621 | Clock_busy_sfc, |
paul@167 | 622 | Clock_divider_sfc); |
paul@165 | 623 | |
paul@165 | 624 | Clock clock_smb0; |
paul@165 | 625 | |
paul@165 | 626 | Clock clock_smb1; |
paul@165 | 627 | |
paul@165 | 628 | Clock clock_smb2; |
paul@165 | 629 | |
paul@165 | 630 | Clock clock_smb3; |
paul@165 | 631 | |
paul@165 | 632 | Clock clock_smb4; |
paul@165 | 633 | |
paul@169 | 634 | Clock clock_ssi(mux_dev, |
paul@167 | 635 | Clock_source_ssi, |
paul@167 | 636 | Clock_gate_ssi0, |
paul@167 | 637 | Clock_change_enable_ssi, |
paul@167 | 638 | Clock_busy_ssi, |
paul@167 | 639 | Clock_divider_ssi); |
paul@165 | 640 | |
paul@169 | 641 | Clock clock_timer(mux_pclock, Source_undefined, Clock_gate_timer); |
paul@165 | 642 | |
paul@169 | 643 | Clock clock_uart0(mux_external, Source_undefined, Clock_gate_uart0); |
paul@165 | 644 | |
paul@169 | 645 | Clock clock_uart1(mux_external, Source_undefined, Clock_gate_uart1); |
paul@165 | 646 | |
paul@169 | 647 | Clock clock_uart2(mux_external, Source_undefined, Clock_gate_uart2); |
paul@165 | 648 | |
paul@169 | 649 | Clock clock_uart3(mux_external, Source_undefined, Clock_gate_uart3); |
paul@165 | 650 | |
paul@165 | 651 | Clock clock_udc; |
paul@165 | 652 | |
paul@165 | 653 | Clock clock_uhc; |
paul@165 | 654 | |
paul@165 | 655 | Clock clock_uprt; |
paul@165 | 656 | |
paul@165 | 657 | |
paul@165 | 658 | |
paul@165 | 659 | // Clock register. |
paul@165 | 660 | |
paul@165 | 661 | static Clock_base *clocks[Clock_identifier_count] = { |
paul@165 | 662 | &clock_ahb2_apb, |
paul@165 | 663 | &clock_aic_bitclk, |
paul@165 | 664 | &clock_aic_pclk, |
paul@165 | 665 | &clock_can0, |
paul@165 | 666 | &clock_can1, |
paul@165 | 667 | &clock_cdbus, |
paul@165 | 668 | &clock_cim, |
paul@165 | 669 | &clock_cpu, |
paul@165 | 670 | &clock_ddr, |
paul@165 | 671 | &clock_dma, |
paul@165 | 672 | &clock_emac, |
paul@165 | 673 | &clock_external, |
paul@165 | 674 | &clock_hclock0, |
paul@165 | 675 | &clock_hclock2, |
paul@165 | 676 | &clock_hdmi, |
paul@165 | 677 | &clock_i2c, |
paul@165 | 678 | &clock_i2c0, |
paul@165 | 679 | &clock_i2c1, |
paul@165 | 680 | &clock_i2s, |
paul@165 | 681 | &clock_i2s0_rx, |
paul@165 | 682 | &clock_i2s0_tx, |
paul@165 | 683 | &clock_kbc, |
paul@165 | 684 | &clock_lcd, |
paul@165 | 685 | &clock_lcd_pixel, |
paul@165 | 686 | &clock_mac, |
paul@165 | 687 | &clock_main, |
paul@165 | 688 | &clock_msc, |
paul@165 | 689 | &clock_msc0, |
paul@165 | 690 | &clock_msc1, |
paul@165 | 691 | &clock_none, |
paul@165 | 692 | &clock_pclock, |
paul@165 | 693 | &clock_pll_A, |
paul@165 | 694 | &clock_pll_E, |
paul@165 | 695 | &clock_pll_M, |
paul@165 | 696 | &clock_pwm, |
paul@165 | 697 | &clock_pwm0, |
paul@165 | 698 | &clock_pwm1, |
paul@165 | 699 | &clock_scc, |
paul@165 | 700 | &clock_sfc, |
paul@165 | 701 | &clock_smb0, |
paul@165 | 702 | &clock_smb1, |
paul@165 | 703 | &clock_smb2, |
paul@165 | 704 | &clock_smb3, |
paul@165 | 705 | &clock_smb4, |
paul@165 | 706 | &clock_ssi, |
paul@165 | 707 | &clock_timer, |
paul@165 | 708 | &clock_uart0, |
paul@165 | 709 | &clock_uart1, |
paul@165 | 710 | &clock_uart2, |
paul@165 | 711 | &clock_uart3, |
paul@165 | 712 | &clock_udc, |
paul@165 | 713 | &clock_uhc, |
paul@165 | 714 | &clock_uprt, |
paul@165 | 715 | }; |
paul@165 | 716 | |
paul@165 | 717 | |
paul@165 | 718 | |
paul@165 | 719 | // Register access. |
paul@165 | 720 | |
paul@165 | 721 | Cpm_regs::Cpm_regs(l4_addr_t addr, uint32_t exclk_freq) |
paul@165 | 722 | : exclk_freq(exclk_freq) |
paul@161 | 723 | { |
paul@165 | 724 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@161 | 725 | } |
paul@161 | 726 | |
paul@165 | 727 | // Utility methods. |
paul@165 | 728 | |
paul@165 | 729 | uint32_t |
paul@165 | 730 | Cpm_regs::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@165 | 731 | { |
paul@165 | 732 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@165 | 733 | } |
paul@165 | 734 | |
paul@165 | 735 | void |
paul@165 | 736 | Cpm_regs::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@165 | 737 | { |
paul@165 | 738 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@165 | 739 | } |
paul@165 | 740 | |
paul@165 | 741 | |
paul@165 | 742 | |
paul@166 | 743 | // Field methods. |
paul@166 | 744 | |
paul@166 | 745 | uint32_t |
paul@166 | 746 | Field::get_field(Cpm_regs ®s) |
paul@166 | 747 | { |
paul@166 | 748 | if (defined) |
paul@166 | 749 | return regs.get_field(reg, mask, bit); |
paul@166 | 750 | else |
paul@166 | 751 | return 0; |
paul@166 | 752 | } |
paul@166 | 753 | |
paul@166 | 754 | void |
paul@166 | 755 | Field::set_field(Cpm_regs ®s, uint32_t value) |
paul@166 | 756 | { |
paul@166 | 757 | if (defined) |
paul@166 | 758 | regs.set_field(reg, mask, bit, value); |
paul@166 | 759 | } |
paul@166 | 760 | |
paul@166 | 761 | |
paul@166 | 762 | |
paul@169 | 763 | // Clock sources. |
paul@169 | 764 | |
paul@169 | 765 | enum Clock_identifiers |
paul@169 | 766 | Mux::get_input(int num) |
paul@169 | 767 | { |
paul@169 | 768 | if (num < _num_inputs) |
paul@169 | 769 | return _inputs[num]; |
paul@169 | 770 | else |
paul@169 | 771 | return Clock_undefined; |
paul@169 | 772 | } |
paul@169 | 773 | |
paul@169 | 774 | |
paul@169 | 775 | |
paul@165 | 776 | // Clock control. |
paul@165 | 777 | |
paul@165 | 778 | int |
paul@165 | 779 | Clock_base::have_clock(Cpm_regs ®s) |
paul@165 | 780 | { |
paul@165 | 781 | (void) regs; |
paul@165 | 782 | return true; |
paul@165 | 783 | } |
paul@165 | 784 | |
paul@165 | 785 | void |
paul@165 | 786 | Clock_base::start_clock(Cpm_regs ®s) |
paul@165 | 787 | { |
paul@165 | 788 | (void) regs; |
paul@165 | 789 | } |
paul@165 | 790 | |
paul@165 | 791 | void |
paul@165 | 792 | Clock_base::stop_clock(Cpm_regs ®s) |
paul@165 | 793 | { |
paul@165 | 794 | (void) regs; |
paul@165 | 795 | } |
paul@165 | 796 | |
paul@165 | 797 | // Default divider. |
paul@165 | 798 | |
paul@165 | 799 | uint32_t |
paul@165 | 800 | Clock_base::get_divider(Cpm_regs ®s) |
paul@165 | 801 | { |
paul@165 | 802 | (void) regs; |
paul@165 | 803 | return 1; |
paul@165 | 804 | } |
paul@165 | 805 | |
paul@165 | 806 | void |
paul@165 | 807 | Clock_base::set_divider(Cpm_regs ®s, uint32_t division) |
paul@165 | 808 | { |
paul@165 | 809 | (void) regs; |
paul@165 | 810 | (void) division; |
paul@165 | 811 | } |
paul@165 | 812 | |
paul@165 | 813 | // Clock sources. |
paul@165 | 814 | |
paul@165 | 815 | uint8_t |
paul@165 | 816 | Clock_base::get_source(Cpm_regs ®s) |
paul@165 | 817 | { |
paul@166 | 818 | if (_source.is_defined()) |
paul@166 | 819 | return _source.get_field(regs); |
paul@165 | 820 | else |
paul@165 | 821 | return 0; |
paul@165 | 822 | } |
paul@165 | 823 | |
paul@165 | 824 | void |
paul@165 | 825 | Clock_base::set_source(Cpm_regs ®s, uint8_t source) |
paul@165 | 826 | { |
paul@170 | 827 | if (!_source.is_defined()) |
paul@165 | 828 | return; |
paul@165 | 829 | |
paul@166 | 830 | _source.set_field(regs, source); |
paul@165 | 831 | } |
paul@165 | 832 | |
paul@165 | 833 | // Clock source frequencies. |
paul@165 | 834 | |
paul@165 | 835 | uint32_t |
paul@165 | 836 | Clock_base::get_source_frequency(Cpm_regs ®s) |
paul@165 | 837 | { |
paul@165 | 838 | // Return the external clock frequency without any input clock. |
paul@165 | 839 | |
paul@169 | 840 | if (_inputs.get_number() == 0) |
paul@165 | 841 | return regs.exclk_freq; |
paul@165 | 842 | |
paul@165 | 843 | // Clocks with one source yield that input frequency. |
paul@165 | 844 | |
paul@169 | 845 | else if (_inputs.get_number() == 1) |
paul@169 | 846 | return clocks[_inputs.get_input(0)]->get_frequency(regs); |
paul@165 | 847 | |
paul@165 | 848 | // With multiple sources, obtain the selected source for the clock. |
paul@165 | 849 | |
paul@165 | 850 | uint8_t source = get_source(regs); |
paul@169 | 851 | enum Clock_identifiers input = _inputs.get_input(source); |
paul@165 | 852 | |
paul@165 | 853 | // Return the frequency of the source. |
paul@165 | 854 | |
paul@169 | 855 | if (input != Clock_undefined) |
paul@169 | 856 | return clocks[input]->get_frequency(regs); |
paul@165 | 857 | else |
paul@165 | 858 | return 0; |
paul@165 | 859 | } |
paul@165 | 860 | |
paul@165 | 861 | // Output clock frequencies. |
paul@165 | 862 | |
paul@165 | 863 | uint32_t |
paul@165 | 864 | Clock_base::get_frequency(Cpm_regs ®s) |
paul@165 | 865 | { |
paul@165 | 866 | return get_source_frequency(regs) / get_divider(regs); |
paul@165 | 867 | } |
paul@165 | 868 | |
paul@165 | 869 | |
paul@165 | 870 | |
paul@165 | 871 | // PLL-specific control. |
paul@165 | 872 | |
paul@165 | 873 | int |
paul@165 | 874 | Pll::have_pll(Cpm_regs ®s) |
paul@165 | 875 | { |
paul@168 | 876 | return _stable.get_field(regs); |
paul@165 | 877 | } |
paul@165 | 878 | |
paul@165 | 879 | int |
paul@165 | 880 | Pll::pll_enabled(Cpm_regs ®s) |
paul@165 | 881 | { |
paul@168 | 882 | return _enable.get_field(regs); |
paul@165 | 883 | } |
paul@165 | 884 | |
paul@165 | 885 | int |
paul@165 | 886 | Pll::pll_bypassed(Cpm_regs ®s) |
paul@165 | 887 | { |
paul@168 | 888 | return _bypass.get_field(regs); |
paul@165 | 889 | } |
paul@165 | 890 | |
paul@165 | 891 | // Clock control. |
paul@165 | 892 | |
paul@165 | 893 | int |
paul@165 | 894 | Pll::have_clock(Cpm_regs ®s) |
paul@165 | 895 | { |
paul@165 | 896 | return have_pll(regs) && pll_enabled(regs); |
paul@165 | 897 | } |
paul@165 | 898 | |
paul@165 | 899 | void |
paul@165 | 900 | Pll::start_clock(Cpm_regs ®s) |
paul@165 | 901 | { |
paul@168 | 902 | _enable.set_field(regs, 1); |
paul@165 | 903 | while (!have_pll(regs)); |
paul@165 | 904 | } |
paul@165 | 905 | |
paul@165 | 906 | void |
paul@165 | 907 | Pll::stop_clock(Cpm_regs ®s) |
paul@161 | 908 | { |
paul@168 | 909 | _enable.set_field(regs, 0); |
paul@165 | 910 | while (have_pll(regs)); |
paul@165 | 911 | } |
paul@165 | 912 | |
paul@165 | 913 | // Feedback (13-bit) multiplier. |
paul@165 | 914 | |
paul@165 | 915 | uint16_t |
paul@165 | 916 | Pll::get_multiplier(Cpm_regs ®s) |
paul@165 | 917 | { |
paul@168 | 918 | return _multiplier.get_field(regs) + 1; |
paul@165 | 919 | } |
paul@165 | 920 | |
paul@165 | 921 | void |
paul@165 | 922 | Pll::set_multiplier(Cpm_regs ®s, uint16_t multiplier) |
paul@165 | 923 | { |
paul@168 | 924 | _multiplier.set_field(regs, multiplier - 1); |
paul@165 | 925 | } |
paul@165 | 926 | |
paul@165 | 927 | // Input (6-bit) divider. |
paul@165 | 928 | |
paul@165 | 929 | uint8_t |
paul@165 | 930 | Pll::get_input_division(Cpm_regs ®s) |
paul@165 | 931 | { |
paul@168 | 932 | return _input_division.get_field(regs) + 1; |
paul@165 | 933 | } |
paul@165 | 934 | |
paul@165 | 935 | void |
paul@165 | 936 | Pll::set_input_division(Cpm_regs ®s, uint8_t divider) |
paul@165 | 937 | { |
paul@168 | 938 | _input_division.set_field(regs, divider - 1); |
paul@165 | 939 | } |
paul@165 | 940 | |
paul@165 | 941 | // Output (dual 3-bit) dividers. |
paul@165 | 942 | |
paul@165 | 943 | uint8_t |
paul@165 | 944 | Pll::get_output_division(Cpm_regs ®s) |
paul@165 | 945 | { |
paul@168 | 946 | uint8_t d0 = _output_division0.get_field(regs); |
paul@168 | 947 | uint8_t d1 = _output_division1.get_field(regs); |
paul@165 | 948 | |
paul@165 | 949 | return d0 * d1; |
paul@165 | 950 | } |
paul@165 | 951 | |
paul@165 | 952 | void |
paul@165 | 953 | Pll::set_output_division(Cpm_regs ®s, uint8_t divider) |
paul@165 | 954 | { |
paul@165 | 955 | // Assert 1 as a minimum. |
paul@165 | 956 | // Divider 0 must be less than or equal to divider 1. |
paul@165 | 957 | |
paul@165 | 958 | uint8_t d0 = (uint8_t) floor(sqrt(divider ? divider : 1)); |
paul@165 | 959 | uint8_t d1 = divider / d0; |
paul@165 | 960 | |
paul@168 | 961 | _output_division0.set_field(regs, d0); |
paul@168 | 962 | _output_division1.set_field(regs, d1); |
paul@165 | 963 | } |
paul@165 | 964 | |
paul@165 | 965 | uint32_t |
paul@165 | 966 | Pll::get_frequency(Cpm_regs ®s) |
paul@165 | 967 | { |
paul@165 | 968 | // Test for PLL enable and not PLL bypass. |
paul@165 | 969 | |
paul@165 | 970 | if (pll_enabled(regs)) |
paul@165 | 971 | { |
paul@165 | 972 | if (!pll_bypassed(regs)) |
paul@165 | 973 | return (get_source_frequency(regs) * get_multiplier(regs)) / |
paul@165 | 974 | (get_input_division(regs) * get_output_division(regs)); |
paul@165 | 975 | else |
paul@165 | 976 | return get_source_frequency(regs); |
paul@165 | 977 | } |
paul@165 | 978 | else |
paul@165 | 979 | return 0; |
paul@165 | 980 | } |
paul@165 | 981 | |
paul@165 | 982 | void |
paul@165 | 983 | Pll::set_pll_parameters(Cpm_regs ®s, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@165 | 984 | { |
paul@165 | 985 | set_multiplier(regs, multiplier); |
paul@165 | 986 | set_input_division(regs, in_divider); |
paul@165 | 987 | set_output_division(regs, out_divider); |
paul@161 | 988 | |
paul@165 | 989 | if (pll_enabled(regs) && !pll_bypassed(regs)) |
paul@165 | 990 | while (!have_pll(regs)); |
paul@165 | 991 | } |
paul@165 | 992 | |
paul@165 | 993 | |
paul@165 | 994 | |
paul@165 | 995 | // Clock control. |
paul@165 | 996 | |
paul@165 | 997 | void |
paul@165 | 998 | Clock::change_disable(Cpm_regs ®s) |
paul@165 | 999 | { |
paul@166 | 1000 | if (_change_enable.is_defined()) |
paul@166 | 1001 | _change_enable.set_field(regs, 0); |
paul@165 | 1002 | } |
paul@165 | 1003 | |
paul@165 | 1004 | void |
paul@165 | 1005 | Clock::change_enable(Cpm_regs ®s) |
paul@165 | 1006 | { |
paul@166 | 1007 | if (_change_enable.is_defined()) |
paul@166 | 1008 | _change_enable.set_field(regs, 1); |
paul@165 | 1009 | } |
paul@165 | 1010 | |
paul@165 | 1011 | int |
paul@165 | 1012 | Clock::have_clock(Cpm_regs ®s) |
paul@165 | 1013 | { |
paul@166 | 1014 | if (_gate.is_defined()) |
paul@166 | 1015 | return !_gate.get_field(regs); |
paul@165 | 1016 | else |
paul@165 | 1017 | return true; |
paul@165 | 1018 | } |
paul@165 | 1019 | |
paul@165 | 1020 | void |
paul@165 | 1021 | Clock::start_clock(Cpm_regs ®s) |
paul@165 | 1022 | { |
paul@166 | 1023 | if (_gate.is_defined()) |
paul@166 | 1024 | _gate.set_field(regs, 0); |
paul@165 | 1025 | } |
paul@165 | 1026 | |
paul@165 | 1027 | void |
paul@165 | 1028 | Clock::stop_clock(Cpm_regs ®s) |
paul@165 | 1029 | { |
paul@166 | 1030 | if (_gate.is_defined()) |
paul@166 | 1031 | _gate.set_field(regs, 1); |
paul@165 | 1032 | } |
paul@165 | 1033 | |
paul@165 | 1034 | void |
paul@165 | 1035 | Clock::wait_busy(Cpm_regs ®s) |
paul@165 | 1036 | { |
paul@166 | 1037 | if (_busy.is_defined()) |
paul@166 | 1038 | while (_busy.get_field(regs)); |
paul@165 | 1039 | } |
paul@165 | 1040 | |
paul@165 | 1041 | |
paul@165 | 1042 | |
paul@165 | 1043 | // Clock dividers. |
paul@165 | 1044 | |
paul@165 | 1045 | uint32_t |
paul@165 | 1046 | Clock::get_divider(Cpm_regs ®s) |
paul@165 | 1047 | { |
paul@166 | 1048 | if (_divider.is_defined()) |
paul@166 | 1049 | return _divider.get_field(regs) + 1; |
paul@165 | 1050 | else |
paul@165 | 1051 | return 1; |
paul@165 | 1052 | } |
paul@165 | 1053 | |
paul@165 | 1054 | void |
paul@165 | 1055 | Clock::set_divider(Cpm_regs ®s, uint32_t division) |
paul@165 | 1056 | { |
paul@170 | 1057 | if (!_divider.is_defined()) |
paul@165 | 1058 | return; |
paul@165 | 1059 | |
paul@165 | 1060 | change_enable(regs); |
paul@166 | 1061 | _divider.set_field(regs, division - 1); |
paul@165 | 1062 | wait_busy(regs); |
paul@165 | 1063 | change_disable(regs); |
paul@165 | 1064 | } |
paul@165 | 1065 | |
paul@165 | 1066 | void |
paul@165 | 1067 | Clock::set_source(Cpm_regs ®s, uint8_t source) |
paul@165 | 1068 | { |
paul@165 | 1069 | change_enable(regs); |
paul@165 | 1070 | Clock_base::set_source(regs, source); |
paul@165 | 1071 | wait_busy(regs); |
paul@165 | 1072 | change_disable(regs); |
paul@161 | 1073 | } |
paul@161 | 1074 | |
paul@161 | 1075 | |
paul@161 | 1076 | |
paul@160 | 1077 | // If implemented as a Hw::Device, various properties would be |
paul@160 | 1078 | // initialised in the constructor and obtained from the device tree |
paul@160 | 1079 | // definitions. |
paul@160 | 1080 | |
paul@160 | 1081 | Cpm_x1600_chip::Cpm_x1600_chip(l4_addr_t addr, uint32_t exclk_freq) |
paul@165 | 1082 | : _cpm_regs(addr, exclk_freq) |
paul@160 | 1083 | { |
paul@160 | 1084 | // add_cid("cpm"); |
paul@160 | 1085 | // add_cid("cpm-x1600"); |
paul@165 | 1086 | // register_property("exclk_freq", &exclk_freq); |
paul@161 | 1087 | } |
paul@160 | 1088 | |
paul@161 | 1089 | int |
paul@161 | 1090 | Cpm_x1600_chip::have_clock(enum Clock_identifiers clock) |
paul@161 | 1091 | { |
paul@165 | 1092 | return clocks[clock]->have_clock(_cpm_regs); |
paul@161 | 1093 | } |
paul@161 | 1094 | |
paul@161 | 1095 | void |
paul@161 | 1096 | Cpm_x1600_chip::start_clock(enum Clock_identifiers clock) |
paul@160 | 1097 | { |
paul@165 | 1098 | clocks[clock]->start_clock(_cpm_regs); |
paul@161 | 1099 | } |
paul@161 | 1100 | |
paul@161 | 1101 | void |
paul@161 | 1102 | Cpm_x1600_chip::stop_clock(enum Clock_identifiers clock) |
paul@161 | 1103 | { |
paul@165 | 1104 | clocks[clock]->stop_clock(_cpm_regs); |
paul@160 | 1105 | } |
paul@160 | 1106 | |
paul@161 | 1107 | uint32_t |
paul@161 | 1108 | Cpm_x1600_chip::get_divider(enum Clock_identifiers clock) |
paul@160 | 1109 | { |
paul@165 | 1110 | return clocks[clock]->get_divider(_cpm_regs); |
paul@160 | 1111 | } |
paul@160 | 1112 | |
paul@161 | 1113 | void |
paul@161 | 1114 | Cpm_x1600_chip::set_divider(enum Clock_identifiers clock, uint32_t division) |
paul@160 | 1115 | { |
paul@165 | 1116 | clocks[clock]->set_divider(_cpm_regs, division); |
paul@160 | 1117 | } |
paul@160 | 1118 | |
paul@160 | 1119 | uint8_t |
paul@161 | 1120 | Cpm_x1600_chip::get_source(enum Clock_identifiers clock) |
paul@160 | 1121 | { |
paul@165 | 1122 | return clocks[clock]->get_source(_cpm_regs); |
paul@160 | 1123 | } |
paul@160 | 1124 | |
paul@160 | 1125 | void |
paul@161 | 1126 | Cpm_x1600_chip::set_source(enum Clock_identifiers clock, uint8_t source) |
paul@160 | 1127 | { |
paul@165 | 1128 | clocks[clock]->set_source(_cpm_regs, source); |
paul@160 | 1129 | } |
paul@160 | 1130 | |
paul@161 | 1131 | uint32_t |
paul@161 | 1132 | Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock) |
paul@160 | 1133 | { |
paul@165 | 1134 | return clocks[clock]->get_source_frequency(_cpm_regs); |
paul@160 | 1135 | } |
paul@160 | 1136 | |
paul@160 | 1137 | uint32_t |
paul@160 | 1138 | Cpm_x1600_chip::get_frequency(enum Clock_identifiers clock) |
paul@160 | 1139 | { |
paul@165 | 1140 | return clocks[clock]->get_frequency(_cpm_regs); |
paul@160 | 1141 | } |
paul@160 | 1142 | |
paul@160 | 1143 | void |
paul@160 | 1144 | Cpm_x1600_chip::set_frequency(enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 1145 | { |
paul@160 | 1146 | switch (clock) |
paul@160 | 1147 | { |
paul@160 | 1148 | // The pixel frequency is based on the selected clock source (SCLK_A, MPLL or |
paul@160 | 1149 | // EPLL). |
paul@160 | 1150 | |
paul@160 | 1151 | case Clock_lcd_pixel: |
paul@165 | 1152 | { |
paul@160 | 1153 | |
paul@160 | 1154 | // Switch to the MPLL and attempt to set the divider. |
paul@160 | 1155 | |
paul@165 | 1156 | Clock_base *lcd = clocks[Clock_lcd_pixel]; |
paul@165 | 1157 | Clock_base *pll = clocks[Clock_pll_M]; |
paul@165 | 1158 | |
paul@165 | 1159 | lcd->set_source(_cpm_regs, Source_mME_pll_M); |
paul@165 | 1160 | pll->start_clock(_cpm_regs); |
paul@165 | 1161 | lcd->set_divider(_cpm_regs, lcd->get_source_frequency(_cpm_regs) / frequency); |
paul@160 | 1162 | break; |
paul@165 | 1163 | } |
paul@160 | 1164 | |
paul@160 | 1165 | default: |
paul@160 | 1166 | break; |
paul@160 | 1167 | } |
paul@160 | 1168 | } |
paul@160 | 1169 | |
paul@165 | 1170 | void |
paul@165 | 1171 | Cpm_x1600_chip::set_pll_parameters(enum Clock_identifiers clock, uint16_t multiplier, |
paul@165 | 1172 | uint8_t in_divider, uint8_t out_divider) |
paul@165 | 1173 | { |
paul@165 | 1174 | Pll *pll = dynamic_cast<Pll *>(clocks[clock]); |
paul@165 | 1175 | |
paul@165 | 1176 | pll->set_pll_parameters(_cpm_regs, multiplier, in_divider, out_divider); |
paul@165 | 1177 | } |
paul@165 | 1178 | |
paul@160 | 1179 | |
paul@160 | 1180 | |
paul@160 | 1181 | // C language interface functions. |
paul@160 | 1182 | |
paul@160 | 1183 | void |
paul@160 | 1184 | *x1600_cpm_init(l4_addr_t cpm_base) |
paul@160 | 1185 | { |
paul@160 | 1186 | /* Initialise the clock and power management peripheral with the |
paul@160 | 1187 | register memory region and a 24MHz EXCLK frequency. */ |
paul@160 | 1188 | |
paul@160 | 1189 | return (void *) new Cpm_x1600_chip(cpm_base, 24000000); |
paul@160 | 1190 | } |
paul@160 | 1191 | |
paul@160 | 1192 | int |
paul@160 | 1193 | x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1194 | { |
paul@160 | 1195 | return static_cast<Cpm_x1600_chip *>(cpm)->have_clock(clock); |
paul@160 | 1196 | } |
paul@160 | 1197 | |
paul@160 | 1198 | void |
paul@160 | 1199 | x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1200 | { |
paul@160 | 1201 | static_cast<Cpm_x1600_chip *>(cpm)->start_clock(clock); |
paul@160 | 1202 | } |
paul@160 | 1203 | |
paul@160 | 1204 | void |
paul@160 | 1205 | x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1206 | { |
paul@160 | 1207 | static_cast<Cpm_x1600_chip *>(cpm)->stop_clock(clock); |
paul@160 | 1208 | } |
paul@160 | 1209 | |
paul@161 | 1210 | uint32_t |
paul@161 | 1211 | x1600_cpm_get_divider(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1212 | { |
paul@161 | 1213 | return static_cast<Cpm_x1600_chip *>(cpm)->get_divider(clock); |
paul@160 | 1214 | } |
paul@160 | 1215 | |
paul@161 | 1216 | void |
paul@161 | 1217 | x1600_cpm_set_divider(void *cpm, enum Clock_identifiers clock, uint32_t divider) |
paul@160 | 1218 | { |
paul@161 | 1219 | return static_cast<Cpm_x1600_chip *>(cpm)->set_divider(clock, divider); |
paul@160 | 1220 | } |
paul@160 | 1221 | |
paul@160 | 1222 | uint8_t |
paul@161 | 1223 | x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1224 | { |
paul@161 | 1225 | return static_cast<Cpm_x1600_chip *>(cpm)->get_source(clock); |
paul@160 | 1226 | } |
paul@160 | 1227 | |
paul@160 | 1228 | void |
paul@161 | 1229 | x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source) |
paul@160 | 1230 | { |
paul@161 | 1231 | static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source); |
paul@160 | 1232 | } |
paul@160 | 1233 | |
paul@160 | 1234 | uint32_t |
paul@161 | 1235 | x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1236 | { |
paul@161 | 1237 | return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock); |
paul@160 | 1238 | } |
paul@160 | 1239 | |
paul@160 | 1240 | uint32_t |
paul@160 | 1241 | x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) |
paul@160 | 1242 | { |
paul@160 | 1243 | return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock); |
paul@160 | 1244 | } |
paul@160 | 1245 | |
paul@160 | 1246 | void |
paul@160 | 1247 | x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) |
paul@160 | 1248 | { |
paul@160 | 1249 | static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency); |
paul@160 | 1250 | } |
paul@160 | 1251 | |
paul@160 | 1252 | void |
paul@160 | 1253 | x1600_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider) |
paul@160 | 1254 | { |
paul@165 | 1255 | static_cast<Cpm_x1600_chip *>(cpm)->set_pll_parameters(Clock_pll_M, multiplier, in_divider, out_divider); |
paul@160 | 1256 | } |