paul@173 | 1 | /* |
paul@173 | 2 | * Common clock functionality. |
paul@173 | 3 | * |
paul@173 | 4 | * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> |
paul@173 | 5 | * |
paul@173 | 6 | * This program is free software; you can redistribute it and/or |
paul@173 | 7 | * modify it under the terms of the GNU General Public License as |
paul@173 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@173 | 9 | * the License, or (at your option) any later version. |
paul@173 | 10 | * |
paul@173 | 11 | * This program is distributed in the hope that it will be useful, |
paul@173 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@173 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@173 | 14 | * GNU General Public License for more details. |
paul@173 | 15 | * |
paul@173 | 16 | * You should have received a copy of the GNU General Public License |
paul@173 | 17 | * along with this program; if not, write to the Free Software |
paul@173 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@173 | 19 | * Boston, MA 02110-1301, USA |
paul@173 | 20 | */ |
paul@173 | 21 | |
paul@173 | 22 | #include <l4/devices/hw_mmio_register_block.h> |
paul@173 | 23 | |
paul@173 | 24 | #include "cpm-common.h" |
paul@173 | 25 | #include <math.h> |
paul@185 | 26 | #include <stdio.h> |
paul@173 | 27 | |
paul@173 | 28 | |
paul@173 | 29 | |
paul@173 | 30 | // Register access. |
paul@173 | 31 | |
paul@173 | 32 | Cpm_regs::Cpm_regs(l4_addr_t addr, Clock_base *clocks[], |
paul@173 | 33 | uint32_t exclk_freq) |
paul@173 | 34 | : _clocks(clocks), exclk_freq(exclk_freq) |
paul@173 | 35 | { |
paul@173 | 36 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@173 | 37 | } |
paul@173 | 38 | |
paul@173 | 39 | // Utility methods. |
paul@173 | 40 | |
paul@173 | 41 | uint32_t |
paul@173 | 42 | Cpm_regs::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@173 | 43 | { |
paul@173 | 44 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@173 | 45 | } |
paul@173 | 46 | |
paul@173 | 47 | void |
paul@173 | 48 | Cpm_regs::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@173 | 49 | { |
paul@173 | 50 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@173 | 51 | } |
paul@173 | 52 | |
paul@173 | 53 | Clock_base * |
paul@173 | 54 | Cpm_regs::get_clock(int num) |
paul@173 | 55 | { |
paul@173 | 56 | return _clocks[num]; |
paul@173 | 57 | } |
paul@173 | 58 | |
paul@173 | 59 | |
paul@173 | 60 | |
paul@173 | 61 | // Field methods. |
paul@173 | 62 | |
paul@173 | 63 | uint32_t |
paul@173 | 64 | Field::get_field(Cpm_regs ®s) |
paul@173 | 65 | { |
paul@173 | 66 | if (defined) |
paul@173 | 67 | return regs.get_field(reg, mask, bit); |
paul@173 | 68 | else |
paul@173 | 69 | return 0; |
paul@173 | 70 | } |
paul@173 | 71 | |
paul@173 | 72 | void |
paul@173 | 73 | Field::set_field(Cpm_regs ®s, uint32_t value) |
paul@173 | 74 | { |
paul@173 | 75 | if (defined) |
paul@173 | 76 | regs.set_field(reg, mask, bit, value); |
paul@173 | 77 | } |
paul@173 | 78 | |
paul@173 | 79 | // Undefined field. |
paul@173 | 80 | |
paul@173 | 81 | Field Field::undefined; |
paul@173 | 82 | |
paul@173 | 83 | |
paul@173 | 84 | |
paul@173 | 85 | // Clock sources. |
paul@173 | 86 | |
paul@173 | 87 | enum Clock_identifiers |
paul@173 | 88 | Mux::get_input(int num) |
paul@173 | 89 | { |
paul@173 | 90 | if (num < _num_inputs) |
paul@173 | 91 | return _inputs[num]; |
paul@173 | 92 | else |
paul@173 | 93 | return Clock_undefined; |
paul@173 | 94 | } |
paul@173 | 95 | |
paul@173 | 96 | // Clock sources. |
paul@173 | 97 | |
paul@173 | 98 | uint8_t |
paul@173 | 99 | Source::get_source(Cpm_regs ®s) |
paul@173 | 100 | { |
paul@173 | 101 | if (_source.is_defined()) |
paul@173 | 102 | return _source.get_field(regs); |
paul@173 | 103 | else |
paul@173 | 104 | return 0; |
paul@173 | 105 | } |
paul@173 | 106 | |
paul@173 | 107 | void |
paul@173 | 108 | Source::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 109 | { |
paul@173 | 110 | if (!_source.is_defined()) |
paul@173 | 111 | return; |
paul@173 | 112 | |
paul@173 | 113 | _source.set_field(regs, source); |
paul@173 | 114 | } |
paul@173 | 115 | |
paul@185 | 116 | enum Clock_identifiers |
paul@185 | 117 | Source::get_source_clock(Cpm_regs ®s) |
paul@185 | 118 | { |
paul@185 | 119 | return get_input(get_number() == 1 ? 0 : get_source(regs)); |
paul@185 | 120 | } |
paul@185 | 121 | |
paul@185 | 122 | void |
paul@185 | 123 | Source::set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock) |
paul@185 | 124 | { |
paul@185 | 125 | for (int source = 0; source < _inputs.get_number(); source++) |
paul@185 | 126 | if (get_input(source) == clock) |
paul@185 | 127 | _source.set_field(regs, source); |
paul@185 | 128 | } |
paul@185 | 129 | |
paul@173 | 130 | // Clock source frequencies. |
paul@173 | 131 | |
paul@173 | 132 | uint32_t |
paul@173 | 133 | Source::get_frequency(Cpm_regs ®s) |
paul@173 | 134 | { |
paul@185 | 135 | enum Clock_identifiers input = get_source_clock(regs); |
paul@173 | 136 | |
paul@173 | 137 | if (input != Clock_undefined) |
paul@173 | 138 | return regs.get_clock(input)->get_frequency(regs); |
paul@173 | 139 | else |
paul@173 | 140 | return 0; |
paul@173 | 141 | } |
paul@173 | 142 | |
paul@173 | 143 | |
paul@173 | 144 | |
paul@175 | 145 | // Clock control. |
paul@175 | 146 | |
paul@175 | 147 | Control_base::~Control_base() |
paul@175 | 148 | { |
paul@175 | 149 | } |
paul@175 | 150 | |
paul@175 | 151 | void |
paul@175 | 152 | Control_base::change_disable(Cpm_regs ®s) |
paul@175 | 153 | { |
paul@175 | 154 | (void) regs; |
paul@175 | 155 | } |
paul@175 | 156 | |
paul@175 | 157 | void |
paul@175 | 158 | Control_base::change_enable(Cpm_regs ®s) |
paul@175 | 159 | { |
paul@175 | 160 | (void) regs; |
paul@175 | 161 | } |
paul@175 | 162 | |
paul@175 | 163 | int |
paul@175 | 164 | Control::have_clock(Cpm_regs ®s) |
paul@175 | 165 | { |
paul@175 | 166 | if (_gate.is_defined()) |
paul@175 | 167 | return !_gate.get_field(regs); |
paul@175 | 168 | else |
paul@175 | 169 | return true; |
paul@175 | 170 | } |
paul@175 | 171 | |
paul@175 | 172 | void |
paul@175 | 173 | Control::start_clock(Cpm_regs ®s) |
paul@175 | 174 | { |
paul@175 | 175 | if (_gate.is_defined()) |
paul@175 | 176 | _gate.set_field(regs, 0); |
paul@175 | 177 | } |
paul@175 | 178 | |
paul@175 | 179 | void |
paul@175 | 180 | Control::stop_clock(Cpm_regs ®s) |
paul@175 | 181 | { |
paul@175 | 182 | if (_gate.is_defined()) |
paul@175 | 183 | _gate.set_field(regs, 1); |
paul@175 | 184 | } |
paul@175 | 185 | |
paul@175 | 186 | void |
paul@175 | 187 | Control::wait_busy(Cpm_regs ®s) |
paul@175 | 188 | { |
paul@175 | 189 | if (_busy.is_defined()) |
paul@175 | 190 | while (_busy.get_field(regs)); |
paul@175 | 191 | } |
paul@175 | 192 | |
paul@175 | 193 | void |
paul@175 | 194 | Control::change_disable(Cpm_regs ®s) |
paul@175 | 195 | { |
paul@175 | 196 | if (_change_enable.is_defined()) |
paul@175 | 197 | _change_enable.set_field(regs, 0); |
paul@175 | 198 | } |
paul@175 | 199 | |
paul@175 | 200 | void |
paul@175 | 201 | Control::change_enable(Cpm_regs ®s) |
paul@175 | 202 | { |
paul@175 | 203 | if (_change_enable.is_defined()) |
paul@175 | 204 | _change_enable.set_field(regs, 1); |
paul@175 | 205 | } |
paul@175 | 206 | |
paul@175 | 207 | |
paul@175 | 208 | |
paul@175 | 209 | // PLL-specific control. |
paul@175 | 210 | |
paul@175 | 211 | int |
paul@175 | 212 | Control_pll::have_pll(Cpm_regs ®s) |
paul@175 | 213 | { |
paul@175 | 214 | return _stable.get_field(regs); |
paul@175 | 215 | } |
paul@175 | 216 | |
paul@175 | 217 | int |
paul@175 | 218 | Control_pll::pll_enabled(Cpm_regs ®s) |
paul@175 | 219 | { |
paul@175 | 220 | return _enable.get_field(regs); |
paul@175 | 221 | } |
paul@175 | 222 | |
paul@175 | 223 | int |
paul@175 | 224 | Control_pll::pll_bypassed(Cpm_regs ®s) |
paul@175 | 225 | { |
paul@175 | 226 | return _bypass.get_field(regs); |
paul@175 | 227 | } |
paul@175 | 228 | |
paul@175 | 229 | // Clock control. |
paul@175 | 230 | |
paul@175 | 231 | int |
paul@175 | 232 | Control_pll::have_clock(Cpm_regs ®s) |
paul@175 | 233 | { |
paul@175 | 234 | return have_pll(regs) && pll_enabled(regs); |
paul@175 | 235 | } |
paul@175 | 236 | |
paul@175 | 237 | void |
paul@175 | 238 | Control_pll::start_clock(Cpm_regs ®s) |
paul@175 | 239 | { |
paul@175 | 240 | _enable.set_field(regs, 1); |
paul@175 | 241 | while (!have_pll(regs)); |
paul@175 | 242 | } |
paul@175 | 243 | |
paul@175 | 244 | void |
paul@175 | 245 | Control_pll::stop_clock(Cpm_regs ®s) |
paul@175 | 246 | { |
paul@175 | 247 | _enable.set_field(regs, 0); |
paul@175 | 248 | while (have_pll(regs)); |
paul@175 | 249 | } |
paul@175 | 250 | |
paul@175 | 251 | void |
paul@175 | 252 | Control_pll::wait_busy(Cpm_regs ®s) |
paul@175 | 253 | { |
paul@175 | 254 | if (pll_enabled(regs) && !pll_bypassed(regs)) |
paul@175 | 255 | while (!have_pll(regs)); |
paul@175 | 256 | } |
paul@175 | 257 | |
paul@175 | 258 | |
paul@175 | 259 | |
paul@174 | 260 | // Clock dividers. |
paul@174 | 261 | |
paul@175 | 262 | Divider_base::~Divider_base() |
paul@175 | 263 | { |
paul@175 | 264 | } |
paul@175 | 265 | |
paul@175 | 266 | |
paul@175 | 267 | |
paul@174 | 268 | uint32_t |
paul@174 | 269 | Divider::get_divider(Cpm_regs ®s) |
paul@174 | 270 | { |
paul@174 | 271 | if (_divider.is_defined()) |
paul@174 | 272 | return _divider.get_field(regs) + 1; |
paul@174 | 273 | else |
paul@174 | 274 | return 1; |
paul@174 | 275 | } |
paul@174 | 276 | |
paul@174 | 277 | void |
paul@175 | 278 | Divider::set_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 279 | { |
paul@174 | 280 | if (_divider.is_defined()) |
paul@175 | 281 | _divider.set_field(regs, divider - 1); |
paul@174 | 282 | } |
paul@174 | 283 | |
paul@174 | 284 | // Output clock frequencies. |
paul@174 | 285 | |
paul@174 | 286 | uint32_t |
paul@174 | 287 | Divider::get_frequency(Cpm_regs ®s, uint32_t source_frequency) |
paul@174 | 288 | { |
paul@174 | 289 | return source_frequency / get_divider(regs); |
paul@174 | 290 | } |
paul@174 | 291 | |
paul@178 | 292 | int |
paul@178 | 293 | Divider::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 294 | { |
paul@178 | 295 | parameters[0] = get_divider(regs); |
paul@178 | 296 | return 1; |
paul@178 | 297 | } |
paul@178 | 298 | |
paul@185 | 299 | int |
paul@185 | 300 | Divider::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@178 | 301 | { |
paul@185 | 302 | if (num_parameters) |
paul@185 | 303 | { |
paul@185 | 304 | set_divider(regs, parameters[0]); |
paul@185 | 305 | return 1; |
paul@185 | 306 | } |
paul@185 | 307 | |
paul@185 | 308 | return 0; |
paul@178 | 309 | } |
paul@178 | 310 | |
paul@174 | 311 | |
paul@174 | 312 | |
paul@174 | 313 | // Feedback (13-bit) multiplier. |
paul@174 | 314 | |
paul@175 | 315 | uint32_t |
paul@174 | 316 | Divider_pll::get_multiplier(Cpm_regs ®s) |
paul@174 | 317 | { |
paul@174 | 318 | return _multiplier.get_field(regs) + 1; |
paul@174 | 319 | } |
paul@174 | 320 | |
paul@174 | 321 | void |
paul@175 | 322 | Divider_pll::set_multiplier(Cpm_regs ®s, uint32_t multiplier) |
paul@174 | 323 | { |
paul@174 | 324 | _multiplier.set_field(regs, multiplier - 1); |
paul@174 | 325 | } |
paul@174 | 326 | |
paul@174 | 327 | // Input (6-bit) divider. |
paul@174 | 328 | |
paul@175 | 329 | uint32_t |
paul@175 | 330 | Divider_pll::get_input_divider(Cpm_regs ®s) |
paul@174 | 331 | { |
paul@175 | 332 | return _input_divider.get_field(regs) + 1; |
paul@174 | 333 | } |
paul@174 | 334 | |
paul@174 | 335 | void |
paul@175 | 336 | Divider_pll::set_input_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 337 | { |
paul@175 | 338 | _input_divider.set_field(regs, divider - 1); |
paul@174 | 339 | } |
paul@174 | 340 | |
paul@174 | 341 | // Output (dual 3-bit) dividers. |
paul@174 | 342 | |
paul@175 | 343 | uint32_t |
paul@175 | 344 | Divider_pll::get_output_divider(Cpm_regs ®s) |
paul@174 | 345 | { |
paul@175 | 346 | uint32_t d0 = _output_divider0.get_field(regs); |
paul@175 | 347 | uint32_t d1 = _output_divider1.get_field(regs); |
paul@174 | 348 | |
paul@174 | 349 | return d0 * d1; |
paul@174 | 350 | } |
paul@174 | 351 | |
paul@174 | 352 | void |
paul@175 | 353 | Divider_pll::set_output_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 354 | { |
paul@174 | 355 | // Assert 1 as a minimum. |
paul@174 | 356 | // Divider 0 must be less than or equal to divider 1. |
paul@174 | 357 | |
paul@175 | 358 | uint32_t d0 = (uint32_t) floor(sqrt(divider ? divider : 1)); |
paul@175 | 359 | uint32_t d1 = divider / d0; |
paul@174 | 360 | |
paul@175 | 361 | _output_divider0.set_field(regs, d0); |
paul@175 | 362 | _output_divider1.set_field(regs, d1); |
paul@174 | 363 | } |
paul@174 | 364 | |
paul@174 | 365 | uint32_t |
paul@174 | 366 | Divider_pll::get_frequency(Cpm_regs ®s, uint32_t source_frequency) |
paul@174 | 367 | { |
paul@174 | 368 | return (source_frequency * get_multiplier(regs)) / |
paul@175 | 369 | (get_input_divider(regs) * get_output_divider(regs)); |
paul@174 | 370 | } |
paul@174 | 371 | |
paul@178 | 372 | int |
paul@178 | 373 | Divider_pll::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@174 | 374 | { |
paul@178 | 375 | parameters[0] = get_multiplier(regs); |
paul@178 | 376 | parameters[1] = get_input_divider(regs); |
paul@178 | 377 | parameters[2] = get_output_divider(regs); |
paul@178 | 378 | return 3; |
paul@178 | 379 | } |
paul@178 | 380 | |
paul@185 | 381 | int |
paul@185 | 382 | Divider_pll::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@178 | 383 | { |
paul@185 | 384 | if (num_parameters > 2) |
paul@185 | 385 | { |
paul@185 | 386 | set_multiplier(regs, parameters[0]); |
paul@185 | 387 | set_input_divider(regs, parameters[1]); |
paul@185 | 388 | set_output_divider(regs, parameters[2]); |
paul@185 | 389 | |
paul@185 | 390 | return 3; |
paul@185 | 391 | } |
paul@185 | 392 | |
paul@185 | 393 | return 0; |
paul@174 | 394 | } |
paul@174 | 395 | |
paul@174 | 396 | |
paul@174 | 397 | |
paul@175 | 398 | // I2S clock divider. |
paul@175 | 399 | |
paul@175 | 400 | uint32_t |
paul@175 | 401 | Divider_i2s::get_multiplier(Cpm_regs ®s) |
paul@175 | 402 | { |
paul@175 | 403 | return _multiplier.get_field(regs); |
paul@175 | 404 | } |
paul@175 | 405 | |
paul@175 | 406 | uint32_t |
paul@178 | 407 | Divider_i2s::get_divider_N(Cpm_regs ®s) |
paul@178 | 408 | { |
paul@178 | 409 | return _divider_N.get_field(regs); |
paul@178 | 410 | } |
paul@178 | 411 | |
paul@178 | 412 | uint32_t |
paul@175 | 413 | Divider_i2s::get_divider_D(Cpm_regs ®s) |
paul@175 | 414 | { |
paul@175 | 415 | return _divider_D.get_field(regs); |
paul@175 | 416 | } |
paul@175 | 417 | |
paul@175 | 418 | uint32_t |
paul@175 | 419 | Divider_i2s::get_frequency(Cpm_regs ®s, uint32_t source_frequency) |
paul@175 | 420 | { |
paul@175 | 421 | return (source_frequency * get_multiplier(regs)) / |
paul@175 | 422 | (get_divider_N(regs) * get_divider_D(regs)); |
paul@175 | 423 | } |
paul@175 | 424 | |
paul@178 | 425 | int |
paul@178 | 426 | Divider_i2s::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 427 | { |
paul@178 | 428 | parameters[0] = get_multiplier(regs); |
paul@178 | 429 | parameters[1] = get_divider_N(regs); |
paul@178 | 430 | parameters[2] = get_divider_D(regs); |
paul@178 | 431 | return 3; |
paul@178 | 432 | } |
paul@178 | 433 | |
paul@185 | 434 | int |
paul@185 | 435 | Divider_i2s::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@175 | 436 | { |
paul@185 | 437 | if (num_parameters == 1) |
paul@185 | 438 | { |
paul@185 | 439 | // Set automatic N and D value calculation if only one parameter is given. |
paul@185 | 440 | |
paul@185 | 441 | _auto_N.set_field(regs, 0); |
paul@185 | 442 | _auto_D.set_field(regs, 0); |
paul@185 | 443 | _multiplier.set_field(regs, parameters[0]); |
paul@185 | 444 | |
paul@185 | 445 | return 1; |
paul@185 | 446 | } |
paul@185 | 447 | else if (num_parameters > 1) |
paul@185 | 448 | { |
paul@185 | 449 | // Test for N < 2M. |
paul@178 | 450 | |
paul@185 | 451 | if (parameters[1] < 2 * parameters[0]) |
paul@185 | 452 | return 0; |
paul@185 | 453 | |
paul@185 | 454 | // Set automatic D value calculation if only two parameters are given. |
paul@185 | 455 | |
paul@185 | 456 | _auto_N.set_field(regs, 1); |
paul@185 | 457 | _auto_D.set_field(regs, (num_parameters == 2) ? 0 : 1); |
paul@175 | 458 | |
paul@185 | 459 | _multiplier.set_field(regs, parameters[0]); |
paul@185 | 460 | _divider_N.set_field(regs, parameters[1]); |
paul@185 | 461 | |
paul@185 | 462 | // Set D explicitly if given. |
paul@185 | 463 | |
paul@185 | 464 | if (num_parameters > 2) |
paul@185 | 465 | _divider_D.set_field(regs, parameters[2]); |
paul@185 | 466 | |
paul@185 | 467 | return num_parameters; |
paul@185 | 468 | } |
paul@185 | 469 | |
paul@185 | 470 | return 0; |
paul@175 | 471 | } |
paul@175 | 472 | |
paul@175 | 473 | |
paul@175 | 474 | |
paul@175 | 475 | // Clock interface. |
paul@175 | 476 | |
paul@175 | 477 | Clock_base::~Clock_base() |
paul@175 | 478 | { |
paul@175 | 479 | } |
paul@175 | 480 | |
paul@175 | 481 | |
paul@175 | 482 | |
paul@175 | 483 | // Null clock. |
paul@173 | 484 | |
paul@173 | 485 | int |
paul@175 | 486 | Clock_null::have_clock(Cpm_regs ®s) |
paul@175 | 487 | { |
paul@175 | 488 | (void) regs; |
paul@175 | 489 | return false; |
paul@175 | 490 | } |
paul@175 | 491 | |
paul@175 | 492 | void |
paul@175 | 493 | Clock_null::start_clock(Cpm_regs ®s) |
paul@175 | 494 | { |
paul@175 | 495 | (void) regs; |
paul@175 | 496 | } |
paul@175 | 497 | |
paul@175 | 498 | void |
paul@175 | 499 | Clock_null::stop_clock(Cpm_regs ®s) |
paul@175 | 500 | { |
paul@175 | 501 | (void) regs; |
paul@175 | 502 | } |
paul@175 | 503 | |
paul@175 | 504 | // Output clock frequencies. |
paul@175 | 505 | |
paul@175 | 506 | uint32_t |
paul@175 | 507 | Clock_null::get_frequency(Cpm_regs ®s) |
paul@175 | 508 | { |
paul@175 | 509 | (void) regs; |
paul@175 | 510 | return 0; |
paul@175 | 511 | } |
paul@175 | 512 | |
paul@175 | 513 | |
paul@175 | 514 | |
paul@175 | 515 | // Passive clock. |
paul@175 | 516 | |
paul@175 | 517 | int |
paul@175 | 518 | Clock_passive::have_clock(Cpm_regs ®s) |
paul@173 | 519 | { |
paul@173 | 520 | (void) regs; |
paul@173 | 521 | return true; |
paul@173 | 522 | } |
paul@173 | 523 | |
paul@173 | 524 | void |
paul@175 | 525 | Clock_passive::start_clock(Cpm_regs ®s) |
paul@173 | 526 | { |
paul@173 | 527 | (void) regs; |
paul@173 | 528 | } |
paul@173 | 529 | |
paul@173 | 530 | void |
paul@175 | 531 | Clock_passive::stop_clock(Cpm_regs ®s) |
paul@173 | 532 | { |
paul@173 | 533 | (void) regs; |
paul@173 | 534 | } |
paul@173 | 535 | |
paul@175 | 536 | // Output clock frequencies. |
paul@173 | 537 | |
paul@173 | 538 | uint32_t |
paul@175 | 539 | Clock_passive::get_frequency(Cpm_regs ®s) |
paul@173 | 540 | { |
paul@175 | 541 | // NOTE: Return the external clock frequency. |
paul@175 | 542 | |
paul@175 | 543 | return regs.exclk_freq; |
paul@175 | 544 | } |
paul@175 | 545 | |
paul@175 | 546 | |
paul@175 | 547 | |
paul@175 | 548 | // Clock control. |
paul@175 | 549 | |
paul@175 | 550 | int |
paul@179 | 551 | Clock_controlled::have_clock(Cpm_regs ®s) |
paul@175 | 552 | { |
paul@175 | 553 | return _get_control().have_clock(regs); |
paul@173 | 554 | } |
paul@173 | 555 | |
paul@173 | 556 | void |
paul@179 | 557 | Clock_controlled::start_clock(Cpm_regs ®s) |
paul@173 | 558 | { |
paul@175 | 559 | _get_control().start_clock(regs); |
paul@175 | 560 | } |
paul@175 | 561 | |
paul@175 | 562 | void |
paul@179 | 563 | Clock_controlled::stop_clock(Cpm_regs ®s) |
paul@175 | 564 | { |
paul@175 | 565 | _get_control().stop_clock(regs); |
paul@173 | 566 | } |
paul@173 | 567 | |
paul@179 | 568 | |
paul@179 | 569 | |
paul@179 | 570 | // Active clock interface. |
paul@179 | 571 | |
paul@179 | 572 | Clock_active::~Clock_active() |
paul@179 | 573 | { |
paul@179 | 574 | } |
paul@179 | 575 | |
paul@173 | 576 | // Clock sources. |
paul@173 | 577 | |
paul@173 | 578 | uint8_t |
paul@175 | 579 | Clock_active::get_source(Cpm_regs ®s) |
paul@173 | 580 | { |
paul@173 | 581 | return _source.get_source(regs); |
paul@173 | 582 | } |
paul@173 | 583 | |
paul@173 | 584 | void |
paul@175 | 585 | Clock_active::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 586 | { |
paul@175 | 587 | _get_control().change_enable(regs); |
paul@173 | 588 | _source.set_source(regs, source); |
paul@175 | 589 | _get_control().wait_busy(regs); |
paul@175 | 590 | _get_control().change_disable(regs); |
paul@173 | 591 | } |
paul@173 | 592 | |
paul@185 | 593 | enum Clock_identifiers |
paul@185 | 594 | Clock_active::get_source_clock(Cpm_regs ®s) |
paul@185 | 595 | { |
paul@185 | 596 | return _source.get_source_clock(regs); |
paul@185 | 597 | } |
paul@185 | 598 | |
paul@185 | 599 | void |
paul@185 | 600 | Clock_active::set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock) |
paul@185 | 601 | { |
paul@185 | 602 | _source.set_source_clock(regs, clock); |
paul@185 | 603 | } |
paul@185 | 604 | |
paul@173 | 605 | // Clock source frequencies. |
paul@173 | 606 | |
paul@173 | 607 | uint32_t |
paul@175 | 608 | Clock_active::get_source_frequency(Cpm_regs ®s) |
paul@173 | 609 | { |
paul@173 | 610 | return _source.get_frequency(regs); |
paul@173 | 611 | } |
paul@173 | 612 | |
paul@173 | 613 | // Output clock frequencies. |
paul@173 | 614 | |
paul@173 | 615 | uint32_t |
paul@175 | 616 | Clock_active::get_frequency(Cpm_regs ®s) |
paul@173 | 617 | { |
paul@174 | 618 | return get_source_frequency(regs); |
paul@173 | 619 | } |
paul@173 | 620 | |
paul@173 | 621 | |
paul@173 | 622 | |
paul@175 | 623 | // Divided clock interface. |
paul@173 | 624 | |
paul@183 | 625 | Clock_divided_base::~Clock_divided_base() |
paul@173 | 626 | { |
paul@173 | 627 | } |
paul@173 | 628 | |
paul@175 | 629 | // Output clock frequencies. |
paul@173 | 630 | |
paul@175 | 631 | uint32_t |
paul@183 | 632 | Clock_divided_base::get_frequency(Cpm_regs ®s) |
paul@173 | 633 | { |
paul@175 | 634 | return _get_divider().get_frequency(regs, get_source_frequency(regs)); |
paul@173 | 635 | } |
paul@173 | 636 | |
paul@178 | 637 | int |
paul@183 | 638 | Clock_divided_base::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 639 | { |
paul@178 | 640 | return _get_divider().get_parameters(regs, parameters); |
paul@178 | 641 | } |
paul@178 | 642 | |
paul@185 | 643 | int |
paul@185 | 644 | Clock_divided_base::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) |
paul@178 | 645 | { |
paul@181 | 646 | _get_control().change_enable(regs); |
paul@185 | 647 | int n = _get_divider().set_parameters(regs, num_parameters, parameters); |
paul@178 | 648 | _get_control().wait_busy(regs); |
paul@181 | 649 | _get_control().change_disable(regs); |
paul@185 | 650 | |
paul@185 | 651 | return n; |
paul@178 | 652 | } |
paul@178 | 653 | |
paul@175 | 654 | |
paul@175 | 655 | |
paul@180 | 656 | // PLL functionality. |
paul@175 | 657 | |
paul@175 | 658 | Pll::~Pll() |
paul@173 | 659 | { |
paul@173 | 660 | } |
paul@173 | 661 | |
paul@173 | 662 | uint32_t |
paul@173 | 663 | Pll::get_frequency(Cpm_regs ®s) |
paul@173 | 664 | { |
paul@185 | 665 | if (!_control.pll_bypassed(regs)) |
paul@185 | 666 | return _divider.get_frequency(regs, get_source_frequency(regs)); |
paul@173 | 667 | else |
paul@185 | 668 | return get_source_frequency(regs); |
paul@173 | 669 | } |