paul@173 | 1 | /* |
paul@173 | 2 | * Common clock functionality. |
paul@173 | 3 | * |
paul@173 | 4 | * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> |
paul@173 | 5 | * |
paul@173 | 6 | * This program is free software; you can redistribute it and/or |
paul@173 | 7 | * modify it under the terms of the GNU General Public License as |
paul@173 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@173 | 9 | * the License, or (at your option) any later version. |
paul@173 | 10 | * |
paul@173 | 11 | * This program is distributed in the hope that it will be useful, |
paul@173 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@173 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@173 | 14 | * GNU General Public License for more details. |
paul@173 | 15 | * |
paul@173 | 16 | * You should have received a copy of the GNU General Public License |
paul@173 | 17 | * along with this program; if not, write to the Free Software |
paul@173 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@173 | 19 | * Boston, MA 02110-1301, USA |
paul@173 | 20 | */ |
paul@173 | 21 | |
paul@173 | 22 | #include <l4/devices/hw_mmio_register_block.h> |
paul@173 | 23 | |
paul@173 | 24 | #include "cpm-common.h" |
paul@173 | 25 | #include <math.h> |
paul@173 | 26 | |
paul@173 | 27 | |
paul@173 | 28 | |
paul@173 | 29 | // Register access. |
paul@173 | 30 | |
paul@173 | 31 | Cpm_regs::Cpm_regs(l4_addr_t addr, Clock_base *clocks[], |
paul@173 | 32 | uint32_t exclk_freq) |
paul@173 | 33 | : _clocks(clocks), exclk_freq(exclk_freq) |
paul@173 | 34 | { |
paul@173 | 35 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@173 | 36 | } |
paul@173 | 37 | |
paul@173 | 38 | // Utility methods. |
paul@173 | 39 | |
paul@173 | 40 | uint32_t |
paul@173 | 41 | Cpm_regs::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@173 | 42 | { |
paul@173 | 43 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@173 | 44 | } |
paul@173 | 45 | |
paul@173 | 46 | void |
paul@173 | 47 | Cpm_regs::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@173 | 48 | { |
paul@173 | 49 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@173 | 50 | } |
paul@173 | 51 | |
paul@173 | 52 | Clock_base * |
paul@173 | 53 | Cpm_regs::get_clock(int num) |
paul@173 | 54 | { |
paul@173 | 55 | return _clocks[num]; |
paul@173 | 56 | } |
paul@173 | 57 | |
paul@173 | 58 | |
paul@173 | 59 | |
paul@173 | 60 | // Field methods. |
paul@173 | 61 | |
paul@173 | 62 | uint32_t |
paul@173 | 63 | Field::get_field(Cpm_regs ®s) |
paul@173 | 64 | { |
paul@173 | 65 | if (defined) |
paul@173 | 66 | return regs.get_field(reg, mask, bit); |
paul@173 | 67 | else |
paul@173 | 68 | return 0; |
paul@173 | 69 | } |
paul@173 | 70 | |
paul@173 | 71 | void |
paul@173 | 72 | Field::set_field(Cpm_regs ®s, uint32_t value) |
paul@173 | 73 | { |
paul@173 | 74 | if (defined) |
paul@173 | 75 | regs.set_field(reg, mask, bit, value); |
paul@173 | 76 | } |
paul@173 | 77 | |
paul@173 | 78 | // Undefined field. |
paul@173 | 79 | |
paul@173 | 80 | Field Field::undefined; |
paul@173 | 81 | |
paul@173 | 82 | |
paul@173 | 83 | |
paul@173 | 84 | // Clock sources. |
paul@173 | 85 | |
paul@173 | 86 | enum Clock_identifiers |
paul@173 | 87 | Mux::get_input(int num) |
paul@173 | 88 | { |
paul@173 | 89 | if (num < _num_inputs) |
paul@173 | 90 | return _inputs[num]; |
paul@173 | 91 | else |
paul@173 | 92 | return Clock_undefined; |
paul@173 | 93 | } |
paul@173 | 94 | |
paul@173 | 95 | // Clock sources. |
paul@173 | 96 | |
paul@173 | 97 | uint8_t |
paul@173 | 98 | Source::get_source(Cpm_regs ®s) |
paul@173 | 99 | { |
paul@173 | 100 | if (_source.is_defined()) |
paul@173 | 101 | return _source.get_field(regs); |
paul@173 | 102 | else |
paul@173 | 103 | return 0; |
paul@173 | 104 | } |
paul@173 | 105 | |
paul@173 | 106 | void |
paul@173 | 107 | Source::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 108 | { |
paul@173 | 109 | if (!_source.is_defined()) |
paul@173 | 110 | return; |
paul@173 | 111 | |
paul@173 | 112 | _source.set_field(regs, source); |
paul@173 | 113 | } |
paul@173 | 114 | |
paul@173 | 115 | // Clock source frequencies. |
paul@173 | 116 | |
paul@173 | 117 | uint32_t |
paul@173 | 118 | Source::get_frequency(Cpm_regs ®s) |
paul@173 | 119 | { |
paul@173 | 120 | // Clocks with one source yield that input frequency. |
paul@173 | 121 | |
paul@175 | 122 | if (get_number() == 1) |
paul@173 | 123 | return regs.get_clock(get_input(0))->get_frequency(regs); |
paul@173 | 124 | |
paul@173 | 125 | // With multiple sources, obtain the selected source for the clock. |
paul@173 | 126 | |
paul@173 | 127 | uint8_t source = get_source(regs); |
paul@173 | 128 | enum Clock_identifiers input = get_input(source); |
paul@173 | 129 | |
paul@173 | 130 | // Return the frequency of the source. |
paul@173 | 131 | |
paul@173 | 132 | if (input != Clock_undefined) |
paul@173 | 133 | return regs.get_clock(input)->get_frequency(regs); |
paul@173 | 134 | else |
paul@173 | 135 | return 0; |
paul@173 | 136 | } |
paul@173 | 137 | |
paul@173 | 138 | |
paul@173 | 139 | |
paul@175 | 140 | // Clock control. |
paul@175 | 141 | |
paul@175 | 142 | Control_base::~Control_base() |
paul@175 | 143 | { |
paul@175 | 144 | } |
paul@175 | 145 | |
paul@175 | 146 | void |
paul@175 | 147 | Control_base::change_disable(Cpm_regs ®s) |
paul@175 | 148 | { |
paul@175 | 149 | (void) regs; |
paul@175 | 150 | } |
paul@175 | 151 | |
paul@175 | 152 | void |
paul@175 | 153 | Control_base::change_enable(Cpm_regs ®s) |
paul@175 | 154 | { |
paul@175 | 155 | (void) regs; |
paul@175 | 156 | } |
paul@175 | 157 | |
paul@175 | 158 | int |
paul@175 | 159 | Control::have_clock(Cpm_regs ®s) |
paul@175 | 160 | { |
paul@175 | 161 | if (_gate.is_defined()) |
paul@175 | 162 | return !_gate.get_field(regs); |
paul@175 | 163 | else |
paul@175 | 164 | return true; |
paul@175 | 165 | } |
paul@175 | 166 | |
paul@175 | 167 | void |
paul@175 | 168 | Control::start_clock(Cpm_regs ®s) |
paul@175 | 169 | { |
paul@175 | 170 | if (_gate.is_defined()) |
paul@175 | 171 | _gate.set_field(regs, 0); |
paul@175 | 172 | } |
paul@175 | 173 | |
paul@175 | 174 | void |
paul@175 | 175 | Control::stop_clock(Cpm_regs ®s) |
paul@175 | 176 | { |
paul@175 | 177 | if (_gate.is_defined()) |
paul@175 | 178 | _gate.set_field(regs, 1); |
paul@175 | 179 | } |
paul@175 | 180 | |
paul@175 | 181 | void |
paul@175 | 182 | Control::wait_busy(Cpm_regs ®s) |
paul@175 | 183 | { |
paul@175 | 184 | if (_busy.is_defined()) |
paul@175 | 185 | while (_busy.get_field(regs)); |
paul@175 | 186 | } |
paul@175 | 187 | |
paul@175 | 188 | void |
paul@175 | 189 | Control::change_disable(Cpm_regs ®s) |
paul@175 | 190 | { |
paul@175 | 191 | if (_change_enable.is_defined()) |
paul@175 | 192 | _change_enable.set_field(regs, 0); |
paul@175 | 193 | } |
paul@175 | 194 | |
paul@175 | 195 | void |
paul@175 | 196 | Control::change_enable(Cpm_regs ®s) |
paul@175 | 197 | { |
paul@175 | 198 | if (_change_enable.is_defined()) |
paul@175 | 199 | _change_enable.set_field(regs, 1); |
paul@175 | 200 | } |
paul@175 | 201 | |
paul@175 | 202 | |
paul@175 | 203 | |
paul@175 | 204 | // PLL-specific control. |
paul@175 | 205 | |
paul@175 | 206 | int |
paul@175 | 207 | Control_pll::have_pll(Cpm_regs ®s) |
paul@175 | 208 | { |
paul@175 | 209 | return _stable.get_field(regs); |
paul@175 | 210 | } |
paul@175 | 211 | |
paul@175 | 212 | int |
paul@175 | 213 | Control_pll::pll_enabled(Cpm_regs ®s) |
paul@175 | 214 | { |
paul@175 | 215 | return _enable.get_field(regs); |
paul@175 | 216 | } |
paul@175 | 217 | |
paul@175 | 218 | int |
paul@175 | 219 | Control_pll::pll_bypassed(Cpm_regs ®s) |
paul@175 | 220 | { |
paul@175 | 221 | return _bypass.get_field(regs); |
paul@175 | 222 | } |
paul@175 | 223 | |
paul@175 | 224 | // Clock control. |
paul@175 | 225 | |
paul@175 | 226 | int |
paul@175 | 227 | Control_pll::have_clock(Cpm_regs ®s) |
paul@175 | 228 | { |
paul@175 | 229 | return have_pll(regs) && pll_enabled(regs); |
paul@175 | 230 | } |
paul@175 | 231 | |
paul@175 | 232 | void |
paul@175 | 233 | Control_pll::start_clock(Cpm_regs ®s) |
paul@175 | 234 | { |
paul@175 | 235 | _enable.set_field(regs, 1); |
paul@175 | 236 | while (!have_pll(regs)); |
paul@175 | 237 | } |
paul@175 | 238 | |
paul@175 | 239 | void |
paul@175 | 240 | Control_pll::stop_clock(Cpm_regs ®s) |
paul@175 | 241 | { |
paul@175 | 242 | _enable.set_field(regs, 0); |
paul@175 | 243 | while (have_pll(regs)); |
paul@175 | 244 | } |
paul@175 | 245 | |
paul@175 | 246 | void |
paul@175 | 247 | Control_pll::wait_busy(Cpm_regs ®s) |
paul@175 | 248 | { |
paul@175 | 249 | if (pll_enabled(regs) && !pll_bypassed(regs)) |
paul@175 | 250 | while (!have_pll(regs)); |
paul@175 | 251 | } |
paul@175 | 252 | |
paul@175 | 253 | |
paul@175 | 254 | |
paul@174 | 255 | // Clock dividers. |
paul@174 | 256 | |
paul@175 | 257 | Divider_base::~Divider_base() |
paul@175 | 258 | { |
paul@175 | 259 | } |
paul@175 | 260 | |
paul@175 | 261 | |
paul@175 | 262 | |
paul@174 | 263 | uint32_t |
paul@174 | 264 | Divider::get_divider(Cpm_regs ®s) |
paul@174 | 265 | { |
paul@174 | 266 | if (_divider.is_defined()) |
paul@174 | 267 | return _divider.get_field(regs) + 1; |
paul@174 | 268 | else |
paul@174 | 269 | return 1; |
paul@174 | 270 | } |
paul@174 | 271 | |
paul@174 | 272 | void |
paul@175 | 273 | Divider::set_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 274 | { |
paul@174 | 275 | if (_divider.is_defined()) |
paul@175 | 276 | _divider.set_field(regs, divider - 1); |
paul@174 | 277 | } |
paul@174 | 278 | |
paul@174 | 279 | // Output clock frequencies. |
paul@174 | 280 | |
paul@174 | 281 | uint32_t |
paul@174 | 282 | Divider::get_frequency(Cpm_regs ®s, uint32_t source_frequency) |
paul@174 | 283 | { |
paul@174 | 284 | return source_frequency / get_divider(regs); |
paul@174 | 285 | } |
paul@174 | 286 | |
paul@178 | 287 | int |
paul@178 | 288 | Divider::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 289 | { |
paul@178 | 290 | parameters[0] = get_divider(regs); |
paul@178 | 291 | return 1; |
paul@178 | 292 | } |
paul@178 | 293 | |
paul@178 | 294 | void |
paul@178 | 295 | Divider::set_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 296 | { |
paul@178 | 297 | set_divider(regs, parameters[0]); |
paul@178 | 298 | } |
paul@178 | 299 | |
paul@174 | 300 | |
paul@174 | 301 | |
paul@174 | 302 | // Feedback (13-bit) multiplier. |
paul@174 | 303 | |
paul@175 | 304 | uint32_t |
paul@174 | 305 | Divider_pll::get_multiplier(Cpm_regs ®s) |
paul@174 | 306 | { |
paul@174 | 307 | return _multiplier.get_field(regs) + 1; |
paul@174 | 308 | } |
paul@174 | 309 | |
paul@174 | 310 | void |
paul@175 | 311 | Divider_pll::set_multiplier(Cpm_regs ®s, uint32_t multiplier) |
paul@174 | 312 | { |
paul@174 | 313 | _multiplier.set_field(regs, multiplier - 1); |
paul@174 | 314 | } |
paul@174 | 315 | |
paul@174 | 316 | // Input (6-bit) divider. |
paul@174 | 317 | |
paul@175 | 318 | uint32_t |
paul@175 | 319 | Divider_pll::get_input_divider(Cpm_regs ®s) |
paul@174 | 320 | { |
paul@175 | 321 | return _input_divider.get_field(regs) + 1; |
paul@174 | 322 | } |
paul@174 | 323 | |
paul@174 | 324 | void |
paul@175 | 325 | Divider_pll::set_input_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 326 | { |
paul@175 | 327 | _input_divider.set_field(regs, divider - 1); |
paul@174 | 328 | } |
paul@174 | 329 | |
paul@174 | 330 | // Output (dual 3-bit) dividers. |
paul@174 | 331 | |
paul@175 | 332 | uint32_t |
paul@175 | 333 | Divider_pll::get_output_divider(Cpm_regs ®s) |
paul@174 | 334 | { |
paul@175 | 335 | uint32_t d0 = _output_divider0.get_field(regs); |
paul@175 | 336 | uint32_t d1 = _output_divider1.get_field(regs); |
paul@174 | 337 | |
paul@174 | 338 | return d0 * d1; |
paul@174 | 339 | } |
paul@174 | 340 | |
paul@174 | 341 | void |
paul@175 | 342 | Divider_pll::set_output_divider(Cpm_regs ®s, uint32_t divider) |
paul@174 | 343 | { |
paul@174 | 344 | // Assert 1 as a minimum. |
paul@174 | 345 | // Divider 0 must be less than or equal to divider 1. |
paul@174 | 346 | |
paul@175 | 347 | uint32_t d0 = (uint32_t) floor(sqrt(divider ? divider : 1)); |
paul@175 | 348 | uint32_t d1 = divider / d0; |
paul@174 | 349 | |
paul@175 | 350 | _output_divider0.set_field(regs, d0); |
paul@175 | 351 | _output_divider1.set_field(regs, d1); |
paul@174 | 352 | } |
paul@174 | 353 | |
paul@174 | 354 | uint32_t |
paul@174 | 355 | Divider_pll::get_frequency(Cpm_regs ®s, uint32_t source_frequency) |
paul@174 | 356 | { |
paul@174 | 357 | return (source_frequency * get_multiplier(regs)) / |
paul@175 | 358 | (get_input_divider(regs) * get_output_divider(regs)); |
paul@174 | 359 | } |
paul@174 | 360 | |
paul@178 | 361 | int |
paul@178 | 362 | Divider_pll::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@174 | 363 | { |
paul@178 | 364 | parameters[0] = get_multiplier(regs); |
paul@178 | 365 | parameters[1] = get_input_divider(regs); |
paul@178 | 366 | parameters[2] = get_output_divider(regs); |
paul@178 | 367 | return 3; |
paul@178 | 368 | } |
paul@178 | 369 | |
paul@178 | 370 | void |
paul@178 | 371 | Divider_pll::set_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 372 | { |
paul@178 | 373 | set_multiplier(regs, parameters[0]); |
paul@178 | 374 | set_input_divider(regs, parameters[1]); |
paul@178 | 375 | set_output_divider(regs, parameters[2]); |
paul@174 | 376 | } |
paul@174 | 377 | |
paul@174 | 378 | |
paul@174 | 379 | |
paul@175 | 380 | // I2S clock divider. |
paul@175 | 381 | |
paul@175 | 382 | uint32_t |
paul@175 | 383 | Divider_i2s::get_multiplier(Cpm_regs ®s) |
paul@175 | 384 | { |
paul@175 | 385 | return _multiplier.get_field(regs); |
paul@175 | 386 | } |
paul@175 | 387 | |
paul@175 | 388 | uint32_t |
paul@178 | 389 | Divider_i2s::get_divider_N(Cpm_regs ®s) |
paul@178 | 390 | { |
paul@178 | 391 | return _divider_N.get_field(regs); |
paul@178 | 392 | } |
paul@178 | 393 | |
paul@178 | 394 | uint32_t |
paul@175 | 395 | Divider_i2s::get_divider_D(Cpm_regs ®s) |
paul@175 | 396 | { |
paul@175 | 397 | return _divider_D.get_field(regs); |
paul@175 | 398 | } |
paul@175 | 399 | |
paul@175 | 400 | uint32_t |
paul@175 | 401 | Divider_i2s::get_frequency(Cpm_regs ®s, uint32_t source_frequency) |
paul@175 | 402 | { |
paul@175 | 403 | return (source_frequency * get_multiplier(regs)) / |
paul@175 | 404 | (get_divider_N(regs) * get_divider_D(regs)); |
paul@175 | 405 | } |
paul@175 | 406 | |
paul@178 | 407 | int |
paul@178 | 408 | Divider_i2s::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 409 | { |
paul@178 | 410 | parameters[0] = get_multiplier(regs); |
paul@178 | 411 | parameters[1] = get_divider_N(regs); |
paul@178 | 412 | parameters[2] = get_divider_D(regs); |
paul@178 | 413 | return 3; |
paul@178 | 414 | } |
paul@178 | 415 | |
paul@175 | 416 | void |
paul@178 | 417 | Divider_i2s::set_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@175 | 418 | { |
paul@178 | 419 | // Test for N < 2M. |
paul@178 | 420 | |
paul@178 | 421 | if (parameters[1] < 2 * parameters[0] ) |
paul@175 | 422 | return; |
paul@175 | 423 | |
paul@178 | 424 | _multiplier.set_field(regs, parameters[0]); |
paul@178 | 425 | _divider_N.set_field(regs, parameters[1]); |
paul@178 | 426 | _divider_D.set_field(regs, parameters[2]); |
paul@175 | 427 | } |
paul@175 | 428 | |
paul@175 | 429 | |
paul@175 | 430 | |
paul@175 | 431 | // Clock interface. |
paul@175 | 432 | |
paul@175 | 433 | Clock_base::~Clock_base() |
paul@175 | 434 | { |
paul@175 | 435 | } |
paul@175 | 436 | |
paul@175 | 437 | |
paul@175 | 438 | |
paul@175 | 439 | // Null clock. |
paul@173 | 440 | |
paul@173 | 441 | int |
paul@175 | 442 | Clock_null::have_clock(Cpm_regs ®s) |
paul@175 | 443 | { |
paul@175 | 444 | (void) regs; |
paul@175 | 445 | return false; |
paul@175 | 446 | } |
paul@175 | 447 | |
paul@175 | 448 | void |
paul@175 | 449 | Clock_null::start_clock(Cpm_regs ®s) |
paul@175 | 450 | { |
paul@175 | 451 | (void) regs; |
paul@175 | 452 | } |
paul@175 | 453 | |
paul@175 | 454 | void |
paul@175 | 455 | Clock_null::stop_clock(Cpm_regs ®s) |
paul@175 | 456 | { |
paul@175 | 457 | (void) regs; |
paul@175 | 458 | } |
paul@175 | 459 | |
paul@175 | 460 | // Output clock frequencies. |
paul@175 | 461 | |
paul@175 | 462 | uint32_t |
paul@175 | 463 | Clock_null::get_frequency(Cpm_regs ®s) |
paul@175 | 464 | { |
paul@175 | 465 | (void) regs; |
paul@175 | 466 | return 0; |
paul@175 | 467 | } |
paul@175 | 468 | |
paul@175 | 469 | |
paul@175 | 470 | |
paul@175 | 471 | // Passive clock. |
paul@175 | 472 | |
paul@175 | 473 | int |
paul@175 | 474 | Clock_passive::have_clock(Cpm_regs ®s) |
paul@173 | 475 | { |
paul@173 | 476 | (void) regs; |
paul@173 | 477 | return true; |
paul@173 | 478 | } |
paul@173 | 479 | |
paul@173 | 480 | void |
paul@175 | 481 | Clock_passive::start_clock(Cpm_regs ®s) |
paul@173 | 482 | { |
paul@173 | 483 | (void) regs; |
paul@173 | 484 | } |
paul@173 | 485 | |
paul@173 | 486 | void |
paul@175 | 487 | Clock_passive::stop_clock(Cpm_regs ®s) |
paul@173 | 488 | { |
paul@173 | 489 | (void) regs; |
paul@173 | 490 | } |
paul@173 | 491 | |
paul@175 | 492 | // Output clock frequencies. |
paul@173 | 493 | |
paul@173 | 494 | uint32_t |
paul@175 | 495 | Clock_passive::get_frequency(Cpm_regs ®s) |
paul@173 | 496 | { |
paul@175 | 497 | // NOTE: Return the external clock frequency. |
paul@175 | 498 | |
paul@175 | 499 | return regs.exclk_freq; |
paul@175 | 500 | } |
paul@175 | 501 | |
paul@175 | 502 | |
paul@175 | 503 | |
paul@175 | 504 | // Clock control. |
paul@175 | 505 | |
paul@175 | 506 | int |
paul@179 | 507 | Clock_controlled::have_clock(Cpm_regs ®s) |
paul@175 | 508 | { |
paul@175 | 509 | return _get_control().have_clock(regs); |
paul@173 | 510 | } |
paul@173 | 511 | |
paul@173 | 512 | void |
paul@179 | 513 | Clock_controlled::start_clock(Cpm_regs ®s) |
paul@173 | 514 | { |
paul@175 | 515 | _get_control().start_clock(regs); |
paul@175 | 516 | } |
paul@175 | 517 | |
paul@175 | 518 | void |
paul@179 | 519 | Clock_controlled::stop_clock(Cpm_regs ®s) |
paul@175 | 520 | { |
paul@175 | 521 | _get_control().stop_clock(regs); |
paul@173 | 522 | } |
paul@173 | 523 | |
paul@179 | 524 | |
paul@179 | 525 | |
paul@179 | 526 | // Active clock interface. |
paul@179 | 527 | |
paul@179 | 528 | Clock_active::~Clock_active() |
paul@179 | 529 | { |
paul@179 | 530 | } |
paul@179 | 531 | |
paul@173 | 532 | // Clock sources. |
paul@173 | 533 | |
paul@173 | 534 | uint8_t |
paul@175 | 535 | Clock_active::get_source(Cpm_regs ®s) |
paul@173 | 536 | { |
paul@173 | 537 | return _source.get_source(regs); |
paul@173 | 538 | } |
paul@173 | 539 | |
paul@173 | 540 | void |
paul@175 | 541 | Clock_active::set_source(Cpm_regs ®s, uint8_t source) |
paul@173 | 542 | { |
paul@175 | 543 | _get_control().change_enable(regs); |
paul@173 | 544 | _source.set_source(regs, source); |
paul@175 | 545 | _get_control().wait_busy(regs); |
paul@175 | 546 | _get_control().change_disable(regs); |
paul@173 | 547 | } |
paul@173 | 548 | |
paul@173 | 549 | // Clock source frequencies. |
paul@173 | 550 | |
paul@173 | 551 | uint32_t |
paul@175 | 552 | Clock_active::get_source_frequency(Cpm_regs ®s) |
paul@173 | 553 | { |
paul@173 | 554 | return _source.get_frequency(regs); |
paul@173 | 555 | } |
paul@173 | 556 | |
paul@173 | 557 | // Output clock frequencies. |
paul@173 | 558 | |
paul@173 | 559 | uint32_t |
paul@175 | 560 | Clock_active::get_frequency(Cpm_regs ®s) |
paul@173 | 561 | { |
paul@174 | 562 | return get_source_frequency(regs); |
paul@173 | 563 | } |
paul@173 | 564 | |
paul@173 | 565 | |
paul@173 | 566 | |
paul@175 | 567 | // Divided clock interface. |
paul@173 | 568 | |
paul@183 | 569 | Clock_divided_base::~Clock_divided_base() |
paul@173 | 570 | { |
paul@173 | 571 | } |
paul@173 | 572 | |
paul@175 | 573 | // Output clock frequencies. |
paul@173 | 574 | |
paul@175 | 575 | uint32_t |
paul@183 | 576 | Clock_divided_base::get_frequency(Cpm_regs ®s) |
paul@173 | 577 | { |
paul@175 | 578 | return _get_divider().get_frequency(regs, get_source_frequency(regs)); |
paul@173 | 579 | } |
paul@173 | 580 | |
paul@178 | 581 | int |
paul@183 | 582 | Clock_divided_base::get_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 583 | { |
paul@178 | 584 | return _get_divider().get_parameters(regs, parameters); |
paul@178 | 585 | } |
paul@178 | 586 | |
paul@178 | 587 | void |
paul@183 | 588 | Clock_divided_base::set_parameters(Cpm_regs ®s, uint32_t parameters[]) |
paul@178 | 589 | { |
paul@181 | 590 | _get_control().change_enable(regs); |
paul@178 | 591 | _get_divider().set_parameters(regs, parameters); |
paul@178 | 592 | _get_control().wait_busy(regs); |
paul@181 | 593 | _get_control().change_disable(regs); |
paul@178 | 594 | } |
paul@178 | 595 | |
paul@175 | 596 | |
paul@175 | 597 | |
paul@180 | 598 | // PLL functionality. |
paul@175 | 599 | |
paul@175 | 600 | Pll::~Pll() |
paul@173 | 601 | { |
paul@173 | 602 | } |
paul@173 | 603 | |
paul@173 | 604 | uint32_t |
paul@173 | 605 | Pll::get_frequency(Cpm_regs ®s) |
paul@173 | 606 | { |
paul@175 | 607 | if (have_clock(regs)) |
paul@173 | 608 | { |
paul@175 | 609 | if (!_control.pll_bypassed(regs)) |
paul@174 | 610 | return _divider.get_frequency(regs, get_source_frequency(regs)); |
paul@173 | 611 | else |
paul@173 | 612 | return get_source_frequency(regs); |
paul@173 | 613 | } |
paul@173 | 614 | else |
paul@173 | 615 | return 0; |
paul@173 | 616 | } |