paul@0 | 1 | /* |
paul@0 | 2 | * GPIO driver for Ingenic JZ4780. |
paul@0 | 3 | * (See below for additional copyright and licensing notices.) |
paul@0 | 4 | * |
paul@188 | 5 | * Copyright (C) 2017, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 6 | * |
paul@0 | 7 | * This program is free software; you can redistribute it and/or |
paul@0 | 8 | * modify it under the terms of the GNU General Public License as |
paul@0 | 9 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 10 | * the License, or (at your option) any later version. |
paul@0 | 11 | * |
paul@0 | 12 | * This program is distributed in the hope that it will be useful, |
paul@0 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 15 | * GNU General Public License for more details. |
paul@0 | 16 | * |
paul@0 | 17 | * You should have received a copy of the GNU General Public License |
paul@0 | 18 | * along with this program; if not, write to the Free Software |
paul@0 | 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 20 | * Boston, MA 02110-1301, USA |
paul@0 | 21 | * |
paul@0 | 22 | * |
paul@0 | 23 | * Subject to other copyrights, being derived from the bcm2835.cc and |
paul@0 | 24 | * omap.cc GPIO driver implementations. |
paul@0 | 25 | * |
paul@0 | 26 | * This file is part of TUD:OS and distributed under the terms of the |
paul@0 | 27 | * GNU General Public License 2. |
paul@0 | 28 | * Please see the COPYING-GPL-2 file for details. |
paul@0 | 29 | */ |
paul@0 | 30 | |
paul@0 | 31 | #include <l4/sys/icu.h> |
paul@0 | 32 | #include <l4/util/util.h> |
paul@0 | 33 | #include <l4/devices/hw_mmio_register_block.h> |
paul@0 | 34 | |
paul@0 | 35 | #include "gpio-jz4780.h" |
paul@0 | 36 | |
paul@0 | 37 | /* |
paul@0 | 38 | GPIO register offsets (x in A..F). |
paul@0 | 39 | |
paul@0 | 40 | Register summary: |
paul@0 | 41 | |
paul@0 | 42 | PxINT 0 (function/GPIO) 1 (interrupt) |
paul@0 | 43 | PxMSK 0 (function) 1 (GPIO) 0 (IRQ enable)/1 (IRQ disable) |
paul@0 | 44 | PxPAT1 0 (function 0/1) 1 (function 2/3) 0 (output) 1 (input) 0 (level trigger) 1 (edge trigger) |
paul@0 | 45 | PxPAT0 0 (function 0) 0 (function 2) 0 (output value 0) 0 (low level) 0 (falling edge) |
paul@0 | 46 | 1 (function 1) 1 (function 3) 1 (output value 1) 1 (high level) 1 (rising edge) |
paul@0 | 47 | */ |
paul@0 | 48 | |
paul@0 | 49 | enum Regs |
paul@188 | 50 | { |
paul@0 | 51 | Pin_level = 0x000, // PxPIN (read-only) |
paul@188 | 52 | |
paul@0 | 53 | Port_int = 0x010, // PxINT |
paul@0 | 54 | Port_int_set = 0x014, // PxINTS |
paul@0 | 55 | Port_int_clear = 0x018, // PxINTC |
paul@188 | 56 | |
paul@0 | 57 | Irq_mask = 0x020, // PxMSK (for PxINT == 1) |
paul@0 | 58 | Irq_mask_set = 0x024, // PxMSKS |
paul@0 | 59 | Irq_mask_clear = 0x028, // PxMSKC |
paul@0 | 60 | Port_gpio = 0x020, // PxMSK (for PxINT == 0) |
paul@0 | 61 | Port_gpio_set = 0x024, // PxMSKS |
paul@0 | 62 | Port_gpio_clear = 0x028, // PxMSKC |
paul@188 | 63 | |
paul@0 | 64 | Port_trigger = 0x030, // PxPAT1 (for PxINT == 1) |
paul@0 | 65 | Port_trigger_set = 0x034, // PxPAT1S |
paul@0 | 66 | Port_trigger_clear = 0x038, // PxPAT1C |
paul@0 | 67 | Port_dir = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 1) |
paul@0 | 68 | Port_dir_set = 0x034, // PxPAT1S |
paul@0 | 69 | Port_dir_clear = 0x038, // PxPAT1C |
paul@0 | 70 | Port_group1 = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 0) |
paul@0 | 71 | Port_group1_set = 0x034, // PxPAT1S |
paul@0 | 72 | Port_group1_clear = 0x038, // PxPAT1C |
paul@188 | 73 | |
paul@0 | 74 | Port_level = 0x040, // PxPAT0 (for PxINT == 1) |
paul@0 | 75 | Port_level_set = 0x044, // PxPAT0S |
paul@0 | 76 | Port_level_clear = 0x048, // PxPAT0C |
paul@0 | 77 | Port_data = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 1, PxPAT1 == 0) |
paul@0 | 78 | Port_data_set = 0x044, // PxPAT0S |
paul@0 | 79 | Port_data_clear = 0x048, // PxPAT0C |
paul@0 | 80 | Port_group0 = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 0) |
paul@0 | 81 | Port_group0_set = 0x044, // PxPAT0S |
paul@0 | 82 | Port_group0_clear = 0x048, // PxPAT0C |
paul@188 | 83 | |
paul@0 | 84 | Irq_flag = 0x050, // PxFLG (read-only) |
paul@0 | 85 | Irq_flag_clear = 0x058, // PxFLGC |
paul@188 | 86 | |
paul@0 | 87 | Pull_disable = 0x070, // PxPE |
paul@0 | 88 | Pull_disable_set = 0x074, // PxPES |
paul@0 | 89 | Pull_disable_clear = 0x078, // PxPEC |
paul@0 | 90 | }; |
paul@0 | 91 | |
paul@0 | 92 | |
paul@0 | 93 | |
paul@285 | 94 | // JZ4780 pull-up/down configuration. |
paul@285 | 95 | |
paul@285 | 96 | static struct gpio_port gpio_ports[] = { |
paul@285 | 97 | {0x3fff00ff, 0x00000000}, |
paul@285 | 98 | {0xfff0f3fc, 0x000f0c03}, |
paul@285 | 99 | {0x0fffffff, 0x00000000}, |
paul@285 | 100 | {0xffff4fff, 0x0000b000}, |
paul@285 | 101 | {0xf0fff37c, 0x00000483}, |
paul@285 | 102 | {0x7fa7f00f, 0x00580ff0}, |
paul@285 | 103 | }; |
paul@285 | 104 | |
paul@285 | 105 | |
paul@285 | 106 | |
paul@0 | 107 | // IRQ control for each GPIO pin. |
paul@0 | 108 | |
paul@0 | 109 | Gpio_jz4780_irq_pin::Gpio_jz4780_irq_pin(unsigned pin, Hw::Register_block<32> const ®s) |
paul@0 | 110 | : _pin(pin), _regs(regs) |
paul@0 | 111 | {} |
paul@0 | 112 | |
paul@0 | 113 | void |
paul@0 | 114 | Gpio_jz4780_irq_pin::write_reg_pin(unsigned reg) |
paul@0 | 115 | { |
paul@0 | 116 | // Write the pin bit to the register, setting or clearing the pin |
paul@0 | 117 | // depending on the register chosen. |
paul@0 | 118 | |
paul@0 | 119 | _regs[reg] = _pin_bit(_pin); |
paul@0 | 120 | } |
paul@0 | 121 | |
paul@0 | 122 | void Gpio_jz4780_irq_pin::do_mask() |
paul@0 | 123 | { |
paul@0 | 124 | // Set the interrupt bit in the PxIM register. |
paul@0 | 125 | |
paul@0 | 126 | write_reg_pin(Irq_mask_set); |
paul@0 | 127 | } |
paul@0 | 128 | |
paul@0 | 129 | void Gpio_jz4780_irq_pin::do_unmask() |
paul@0 | 130 | { |
paul@0 | 131 | // Clear the interrupt bit in the PxIM register, first also clearing the |
paul@0 | 132 | // flag bit in the PxFLG register to allow interrupts to be delivered. |
paul@0 | 133 | |
paul@0 | 134 | write_reg_pin(Irq_flag_clear); |
paul@0 | 135 | write_reg_pin(Irq_mask_clear); |
paul@0 | 136 | } |
paul@0 | 137 | |
paul@0 | 138 | bool Gpio_jz4780_irq_pin::do_set_mode(unsigned mode) |
paul@0 | 139 | { |
paul@0 | 140 | // Standard comment found for this method: |
paul@0 | 141 | // this operation touches multiple mmio registers and is thus |
paul@0 | 142 | // not atomic, that's why we first mask the IRQ and if it was |
paul@0 | 143 | // enabled we unmask it after we have changed the mode |
paul@0 | 144 | |
paul@0 | 145 | if (enabled()) |
paul@0 | 146 | do_mask(); |
paul@0 | 147 | |
paul@0 | 148 | // Do the PxINT, PxPAT1 and PxPAT0 configuration. |
paul@0 | 149 | |
paul@0 | 150 | switch(mode) |
paul@0 | 151 | { |
paul@0 | 152 | case L4_IRQ_F_LEVEL_HIGH: |
paul@0 | 153 | write_reg_pin(Port_int_set); |
paul@0 | 154 | write_reg_pin(Port_trigger_clear); |
paul@0 | 155 | write_reg_pin(Port_level_set); |
paul@0 | 156 | break; |
paul@0 | 157 | case L4_IRQ_F_LEVEL_LOW: |
paul@0 | 158 | write_reg_pin(Port_int_set); |
paul@0 | 159 | write_reg_pin(Port_trigger_clear); |
paul@0 | 160 | write_reg_pin(Port_level_clear); |
paul@0 | 161 | break; |
paul@0 | 162 | case L4_IRQ_F_POS_EDGE: |
paul@0 | 163 | write_reg_pin(Port_int_set); |
paul@0 | 164 | write_reg_pin(Port_trigger_set); |
paul@0 | 165 | write_reg_pin(Port_level_set); |
paul@0 | 166 | break; |
paul@0 | 167 | case L4_IRQ_F_NEG_EDGE: |
paul@0 | 168 | write_reg_pin(Port_int_set); |
paul@0 | 169 | write_reg_pin(Port_trigger_set); |
paul@0 | 170 | write_reg_pin(Port_level_clear); |
paul@0 | 171 | break; |
paul@0 | 172 | |
paul@0 | 173 | default: |
paul@0 | 174 | return false; |
paul@0 | 175 | } |
paul@0 | 176 | |
paul@0 | 177 | if (enabled()) |
paul@0 | 178 | do_unmask(); |
paul@0 | 179 | |
paul@0 | 180 | return true; |
paul@0 | 181 | } |
paul@0 | 182 | |
paul@0 | 183 | int Gpio_jz4780_irq_pin::clear() |
paul@0 | 184 | { |
paul@0 | 185 | // Obtain the flag status for the pin, clearing it if set. |
paul@0 | 186 | |
paul@0 | 187 | l4_uint32_t e = _regs[Irq_flag] & (1UL << _pin); |
paul@0 | 188 | if (e) |
paul@0 | 189 | _regs[Irq_flag_clear] = e; |
paul@0 | 190 | |
paul@0 | 191 | return (e >> _pin); |
paul@0 | 192 | } |
paul@0 | 193 | |
paul@0 | 194 | bool Gpio_jz4780_irq_pin::enabled() |
paul@0 | 195 | { |
paul@0 | 196 | return true; |
paul@0 | 197 | } |
paul@0 | 198 | |
paul@0 | 199 | |
paul@0 | 200 | |
paul@0 | 201 | // Initialise the GPIO controller. |
paul@0 | 202 | |
paul@285 | 203 | Gpio_jz4780_chip::Gpio_jz4780_chip(l4_addr_t start, uint8_t port_number) |
paul@285 | 204 | : _nr_pins(32) |
paul@0 | 205 | { |
paul@285 | 206 | _start = start + port_number * 0x100; |
paul@0 | 207 | _regs = new Hw::Mmio_register_block<32>(_start); |
paul@285 | 208 | _pull_config = &gpio_ports[port_number]; |
paul@0 | 209 | } |
paul@0 | 210 | |
paul@0 | 211 | // Return the value of a pin. |
paul@0 | 212 | |
paul@0 | 213 | int |
paul@0 | 214 | Gpio_jz4780_chip::get(unsigned pin) |
paul@0 | 215 | { |
paul@0 | 216 | if (pin >= _nr_pins) |
paul@0 | 217 | throw -L4_EINVAL; |
paul@0 | 218 | |
paul@0 | 219 | l4_uint32_t val = _regs[Pin_level]; |
paul@0 | 220 | return (val >> _pin_shift(pin)) & 1; |
paul@0 | 221 | } |
paul@0 | 222 | |
paul@0 | 223 | // Return multiple pin values. |
paul@0 | 224 | |
paul@0 | 225 | unsigned |
paul@0 | 226 | Gpio_jz4780_chip::multi_get(unsigned offset) |
paul@0 | 227 | { |
paul@0 | 228 | _reg_offset_check(offset); |
paul@0 | 229 | return _regs[Pin_level]; |
paul@0 | 230 | } |
paul@0 | 231 | |
paul@0 | 232 | // Set the value of a pin. |
paul@0 | 233 | |
paul@0 | 234 | void |
paul@0 | 235 | Gpio_jz4780_chip::set(unsigned pin, int value) |
paul@0 | 236 | { |
paul@0 | 237 | if (pin >= _nr_pins) |
paul@0 | 238 | throw -L4_EINVAL; |
paul@0 | 239 | |
paul@0 | 240 | l4_uint32_t reg_set = value ? Port_data_set : Port_data_clear; |
paul@0 | 241 | _regs[reg_set] = _pin_bit(pin); |
paul@0 | 242 | } |
paul@0 | 243 | |
paul@0 | 244 | // Set multiple pin values. |
paul@0 | 245 | |
paul@0 | 246 | void |
paul@0 | 247 | Gpio_jz4780_chip::multi_set(Pin_slice const &mask, unsigned data) |
paul@0 | 248 | { |
paul@0 | 249 | _reg_offset_check(mask.offset); |
paul@0 | 250 | if (mask.mask & data) |
paul@0 | 251 | _regs[Port_data_set] = (mask.mask & data); |
paul@0 | 252 | if (mask.mask & ~data) |
paul@0 | 253 | _regs[Port_data_clear] = (mask.mask & ~data); |
paul@0 | 254 | } |
paul@0 | 255 | |
paul@0 | 256 | // Set a pin up with the given mode and value (if appropriate). |
paul@0 | 257 | |
paul@0 | 258 | void |
paul@0 | 259 | Gpio_jz4780_chip::setup(unsigned pin, unsigned mode, int value) |
paul@0 | 260 | { |
paul@0 | 261 | if (pin >= _nr_pins) |
paul@0 | 262 | throw -L4_EINVAL; |
paul@0 | 263 | |
paul@0 | 264 | config(pin, mode); |
paul@0 | 265 | |
paul@0 | 266 | if (mode == Output) |
paul@0 | 267 | set(pin, value); |
paul@0 | 268 | } |
paul@0 | 269 | |
paul@0 | 270 | // Configuration of a pin using the generic input/output/IRQ mode. |
paul@0 | 271 | |
paul@0 | 272 | void |
paul@0 | 273 | Gpio_jz4780_chip::config(unsigned pin, unsigned mode) |
paul@0 | 274 | { |
paul@0 | 275 | switch (mode) |
paul@0 | 276 | { |
paul@0 | 277 | case Input: |
paul@0 | 278 | _regs[Port_int_clear] = _pin_bit(pin); |
paul@0 | 279 | _regs[Port_gpio_set] = _pin_bit(pin); |
paul@0 | 280 | _regs[Port_dir_set] = _pin_bit(pin); |
paul@0 | 281 | break; |
paul@0 | 282 | case Output: |
paul@0 | 283 | _regs[Port_int_clear] = _pin_bit(pin); |
paul@0 | 284 | _regs[Port_gpio_set] = _pin_bit(pin); |
paul@0 | 285 | _regs[Port_dir_clear] = _pin_bit(pin); |
paul@0 | 286 | break; |
paul@0 | 287 | case Irq: |
paul@0 | 288 | _regs[Port_int_set] = _pin_bit(pin); |
paul@0 | 289 | // Other details depend on the actual trigger mode. |
paul@0 | 290 | break; |
paul@0 | 291 | default: |
paul@0 | 292 | break; |
paul@0 | 293 | } |
paul@0 | 294 | } |
paul@0 | 295 | |
paul@0 | 296 | // Pull-up/down configuration for a pin. |
paul@0 | 297 | |
paul@0 | 298 | void |
paul@0 | 299 | Gpio_jz4780_chip::config_pull(unsigned pin, unsigned mode) |
paul@0 | 300 | { |
paul@0 | 301 | if (pin >= _nr_pins) |
paul@0 | 302 | throw -L4_EINVAL; |
paul@0 | 303 | |
paul@0 | 304 | switch (mode) |
paul@0 | 305 | { |
paul@0 | 306 | case Pull_none: |
paul@0 | 307 | _regs[Pull_disable_set] = _pin_bit(pin); |
paul@0 | 308 | break; |
paul@0 | 309 | case Pull_down: |
paul@285 | 310 | if (_pin_bit(pin) & _pull_config->pull_downs) |
paul@0 | 311 | _regs[Pull_disable_clear] = _pin_bit(pin); |
paul@0 | 312 | break; |
paul@0 | 313 | case Pull_up: |
paul@285 | 314 | if (_pin_bit(pin) & _pull_config->pull_ups) |
paul@285 | 315 | _regs[Pull_disable_clear] = _pin_bit(pin); |
paul@0 | 316 | break; |
paul@0 | 317 | default: |
paul@0 | 318 | // Invalid pull-up/down mode for pin. |
paul@0 | 319 | throw -L4_EINVAL; |
paul@0 | 320 | } |
paul@0 | 321 | } |
paul@0 | 322 | |
paul@0 | 323 | // Pin function configuration. |
paul@0 | 324 | |
paul@0 | 325 | void |
paul@0 | 326 | Gpio_jz4780_chip::config_pad(unsigned pin, unsigned func, unsigned value) |
paul@0 | 327 | { |
paul@0 | 328 | if (pin >= _nr_pins) |
paul@0 | 329 | throw -L4_EINVAL; |
paul@0 | 330 | |
paul@188 | 331 | if (value > 3) |
paul@0 | 332 | throw -L4_EINVAL; |
paul@0 | 333 | |
paul@0 | 334 | switch (func) |
paul@0 | 335 | { |
paul@0 | 336 | // Support two different outputs. |
paul@0 | 337 | |
paul@0 | 338 | case Hw::Gpio_chip::Function_gpio: |
paul@0 | 339 | _regs[Port_int_clear] = _pin_bit(pin); |
paul@0 | 340 | _regs[Port_gpio_set] = _pin_bit(pin); |
paul@0 | 341 | _regs[value & 1 ? Port_data_set : Port_data_clear] = _pin_bit(pin); |
paul@0 | 342 | break; |
paul@0 | 343 | |
paul@0 | 344 | // Support four different device functions. |
paul@0 | 345 | |
paul@0 | 346 | case Hw::Gpio_chip::Function_alt: |
paul@0 | 347 | _regs[Port_int_clear] = _pin_bit(pin); |
paul@0 | 348 | _regs[Port_gpio_clear] = _pin_bit(pin); |
paul@0 | 349 | _regs[value & 2 ? Port_group1_set : Port_group1_clear] = _pin_bit(pin); |
paul@0 | 350 | _regs[value & 1 ? Port_group0_set : Port_group0_clear] = _pin_bit(pin); |
paul@0 | 351 | break; |
paul@0 | 352 | default: |
paul@0 | 353 | throw -L4_EINVAL; |
paul@0 | 354 | } |
paul@0 | 355 | } |
paul@0 | 356 | |
paul@0 | 357 | // Obtain a pin's configuration from a register in the supplied value. |
paul@0 | 358 | |
paul@0 | 359 | void |
paul@0 | 360 | Gpio_jz4780_chip::config_get(unsigned pin, unsigned reg, unsigned *value) |
paul@0 | 361 | { |
paul@0 | 362 | if (pin >= _nr_pins) |
paul@0 | 363 | throw -L4_EINVAL; |
paul@0 | 364 | |
paul@0 | 365 | *value = (_regs[reg] >> _pin_shift(pin)) & 1; |
paul@0 | 366 | } |
paul@0 | 367 | |
paul@188 | 368 | // Return function and function-specific configuration for a pin. |
paul@188 | 369 | |
paul@188 | 370 | void |
paul@188 | 371 | Gpio_jz4780_chip::config_pad_get(unsigned pin, unsigned *func, unsigned *value) |
paul@188 | 372 | { |
paul@188 | 373 | unsigned direction, gpio, group0, group1, interrupt, level, trigger; |
paul@188 | 374 | |
paul@188 | 375 | config_get(pin, Port_int, &interrupt); |
paul@188 | 376 | |
paul@188 | 377 | if (interrupt) |
paul@188 | 378 | { |
paul@188 | 379 | config_get(pin, Port_trigger, &trigger); |
paul@188 | 380 | config_get(pin, Port_level, &level); |
paul@188 | 381 | |
paul@188 | 382 | *func = Hw::Gpio_chip::Function_irq; |
paul@188 | 383 | *value = (trigger ? (level ? L4_IRQ_F_POS_EDGE : L4_IRQ_F_NEG_EDGE) |
paul@188 | 384 | : (level ? L4_IRQ_F_LEVEL_HIGH : L4_IRQ_F_LEVEL_LOW)); |
paul@188 | 385 | return; |
paul@188 | 386 | } |
paul@188 | 387 | |
paul@188 | 388 | config_get(pin, Port_gpio, &gpio); |
paul@188 | 389 | |
paul@188 | 390 | if (gpio) |
paul@188 | 391 | { |
paul@188 | 392 | config_get(pin, Port_dir, &direction); |
paul@188 | 393 | |
paul@188 | 394 | *func = Hw::Gpio_chip::Function_gpio; |
paul@188 | 395 | *value = direction ? Input : Output; |
paul@188 | 396 | return; |
paul@188 | 397 | } |
paul@188 | 398 | |
paul@188 | 399 | *func = Hw::Gpio_chip::Function_alt; |
paul@188 | 400 | |
paul@188 | 401 | config_get(pin, Port_group0, &group0); |
paul@188 | 402 | config_get(pin, Port_group1, &group1); |
paul@188 | 403 | |
paul@188 | 404 | *value = (group1 << 1) | group0; |
paul@188 | 405 | } |
paul@188 | 406 | |
paul@0 | 407 | // Obtain an IRQ abstraction for a pin. |
paul@0 | 408 | |
paul@0 | 409 | Hw::Gpio_irq_pin * |
paul@0 | 410 | Gpio_jz4780_chip::get_irq(unsigned pin) |
paul@0 | 411 | { |
paul@0 | 412 | if (pin >= _nr_pins) |
paul@0 | 413 | throw -L4_EINVAL; |
paul@0 | 414 | |
paul@0 | 415 | return new Gpio_jz4780_irq_pin(pin, _regs); |
paul@0 | 416 | } |
paul@0 | 417 | |
paul@0 | 418 | // Pin function configuration for multiple pins. |
paul@0 | 419 | |
paul@0 | 420 | void |
paul@0 | 421 | Gpio_jz4780_chip::multi_config_pad(Pin_slice const &mask, unsigned func, unsigned val) |
paul@0 | 422 | { |
paul@0 | 423 | unsigned m = mask.mask; |
paul@0 | 424 | for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1) |
paul@0 | 425 | if (m & 1) |
paul@0 | 426 | config_pad(pin, func, val); |
paul@0 | 427 | } |
paul@0 | 428 | |
paul@0 | 429 | // Set up multiple pins with the given mode. |
paul@0 | 430 | |
paul@0 | 431 | void |
paul@0 | 432 | Gpio_jz4780_chip::multi_setup(Pin_slice const &mask, unsigned mode, unsigned outvalues) |
paul@0 | 433 | { |
paul@0 | 434 | unsigned m = mask.mask; |
paul@0 | 435 | for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1, outvalues >>= 1) |
paul@0 | 436 | if (m & 1) |
paul@0 | 437 | setup(pin, mode, outvalues & 1); |
paul@0 | 438 | } |
paul@0 | 439 | |
paul@0 | 440 | |
paul@0 | 441 | |
paul@0 | 442 | // C language interface functions. |
paul@0 | 443 | |
paul@285 | 444 | void *jz4780_gpio_init(l4_addr_t start, uint8_t port_number) |
paul@0 | 445 | { |
paul@285 | 446 | return (void *) new Gpio_jz4780_chip(start, port_number); |
paul@0 | 447 | } |
paul@0 | 448 | |
paul@0 | 449 | void jz4780_gpio_setup(void *gpio, unsigned pin, unsigned mode, int value) |
paul@0 | 450 | { |
paul@0 | 451 | static_cast<Gpio_jz4780_chip *>(gpio)->setup(pin, mode, value); |
paul@0 | 452 | } |
paul@0 | 453 | |
paul@0 | 454 | void jz4780_gpio_config_pull(void *gpio, unsigned pin, unsigned mode) |
paul@0 | 455 | { |
paul@0 | 456 | static_cast<Gpio_jz4780_chip *>(gpio)->config_pull(pin, mode); |
paul@0 | 457 | } |
paul@0 | 458 | |
paul@0 | 459 | void jz4780_gpio_config_pad(void *gpio, unsigned pin, unsigned func, unsigned value) |
paul@0 | 460 | { |
paul@0 | 461 | static_cast<Gpio_jz4780_chip *>(gpio)->config_pad(pin, func, value); |
paul@0 | 462 | } |
paul@0 | 463 | |
paul@0 | 464 | void jz4780_gpio_config_get(void *gpio, unsigned pin, unsigned reg, unsigned *value) |
paul@0 | 465 | { |
paul@0 | 466 | static_cast<Gpio_jz4780_chip *>(gpio)->config_get(pin, reg, value); |
paul@0 | 467 | } |
paul@0 | 468 | |
paul@188 | 469 | void jz4780_gpio_config_pad_get(void *gpio, unsigned pin, unsigned *func, unsigned *value) |
paul@188 | 470 | { |
paul@188 | 471 | static_cast<Gpio_jz4780_chip *>(gpio)->config_pad_get(pin, func, value); |
paul@188 | 472 | } |
paul@188 | 473 | |
paul@0 | 474 | void jz4780_gpio_multi_setup(void *gpio, Pin_slice const *mask, unsigned mode, unsigned outvalues) |
paul@0 | 475 | { |
paul@0 | 476 | static_cast<Gpio_jz4780_chip *>(gpio)->multi_setup(*mask, mode, outvalues); |
paul@0 | 477 | } |
paul@0 | 478 | |
paul@0 | 479 | void jz4780_gpio_multi_config_pad(void *gpio, Pin_slice const *mask, unsigned func, unsigned value) |
paul@0 | 480 | { |
paul@0 | 481 | static_cast<Gpio_jz4780_chip *>(gpio)->multi_config_pad(*mask, func, value); |
paul@0 | 482 | } |
paul@0 | 483 | |
paul@0 | 484 | void jz4780_gpio_multi_set(void *gpio, Pin_slice const *mask, unsigned data) |
paul@0 | 485 | { |
paul@0 | 486 | static_cast<Gpio_jz4780_chip *>(gpio)->multi_set(*mask, data); |
paul@0 | 487 | } |
paul@0 | 488 | |
paul@0 | 489 | unsigned jz4780_gpio_multi_get(void *gpio, unsigned offset) |
paul@0 | 490 | { |
paul@0 | 491 | return static_cast<Gpio_jz4780_chip *>(gpio)->multi_get(offset); |
paul@0 | 492 | } |
paul@0 | 493 | |
paul@0 | 494 | int jz4780_gpio_get(void *gpio, unsigned pin) |
paul@0 | 495 | { |
paul@0 | 496 | return static_cast<Gpio_jz4780_chip *>(gpio)->get(pin); |
paul@0 | 497 | } |
paul@0 | 498 | |
paul@0 | 499 | void jz4780_gpio_set(void *gpio, unsigned pin, int value) |
paul@0 | 500 | { |
paul@0 | 501 | static_cast<Gpio_jz4780_chip *>(gpio)->set(pin, value); |
paul@0 | 502 | } |
paul@0 | 503 | |
paul@0 | 504 | void *jz4780_gpio_get_irq(void *gpio, unsigned pin) |
paul@0 | 505 | { |
paul@0 | 506 | return (void *) static_cast<Gpio_jz4780_chip *>(gpio)->get_irq(pin); |
paul@0 | 507 | } |
paul@0 | 508 | |
paul@0 | 509 | bool jz4780_gpio_irq_set_mode(void *gpio_irq, unsigned mode) |
paul@0 | 510 | { |
paul@0 | 511 | return static_cast<Hw::Gpio_irq_pin *>(gpio_irq)->do_set_mode(mode); |
paul@0 | 512 | } |