paul@188 | 1 | /* |
paul@188 | 2 | * GPIO driver for Ingenic X1600. |
paul@188 | 3 | * (See below for additional copyright and licensing notices.) |
paul@188 | 4 | * |
paul@188 | 5 | * Copyright (C) 2017, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@188 | 6 | * |
paul@188 | 7 | * This program is free software; you can redistribute it and/or |
paul@188 | 8 | * modify it under the terms of the GNU General Public License as |
paul@188 | 9 | * published by the Free Software Foundation; either version 2 of |
paul@188 | 10 | * the License, or (at your option) any later version. |
paul@188 | 11 | * |
paul@188 | 12 | * This program is distributed in the hope that it will be useful, |
paul@188 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@188 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@188 | 15 | * GNU General Public License for more details. |
paul@188 | 16 | * |
paul@188 | 17 | * You should have received a copy of the GNU General Public License |
paul@188 | 18 | * along with this program; if not, write to the Free Software |
paul@188 | 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@188 | 20 | * Boston, MA 02110-1301, USA |
paul@188 | 21 | * |
paul@188 | 22 | * |
paul@188 | 23 | * Subject to other copyrights, being derived from the bcm2835.cc and |
paul@188 | 24 | * omap.cc GPIO driver implementations. |
paul@188 | 25 | * |
paul@188 | 26 | * This file is part of TUD:OS and distributed under the terms of the |
paul@188 | 27 | * GNU General Public License 2. |
paul@188 | 28 | * Please see the COPYING-GPL-2 file for details. |
paul@188 | 29 | */ |
paul@188 | 30 | |
paul@188 | 31 | #include <l4/sys/icu.h> |
paul@188 | 32 | #include <l4/util/util.h> |
paul@188 | 33 | #include <l4/devices/hw_mmio_register_block.h> |
paul@188 | 34 | |
paul@188 | 35 | #include "gpio-x1600.h" |
paul@188 | 36 | |
paul@188 | 37 | /* |
paul@188 | 38 | GPIO register offsets (x in A..D). |
paul@188 | 39 | |
paul@188 | 40 | Register summary: |
paul@188 | 41 | |
paul@188 | 42 | PxINT 0 (function/GPIO) 1 (interrupt) |
paul@188 | 43 | PxMSK 0 (function) 1 (GPIO) 0 (IRQ enable)/1 (IRQ disable) |
paul@188 | 44 | PxPAT1 0 (function 0/1) 1 (function 2/3) 0 (output) 1 (input) 0 (level trigger) 1 (edge trigger) |
paul@188 | 45 | PxPAT0 0 (function 0) 0 (function 2) 0 (output value 0) 0 (low level) 0 (falling edge) |
paul@188 | 46 | 1 (function 1) 1 (function 3) 1 (output value 1) 1 (high level) 1 (rising edge) |
paul@188 | 47 | */ |
paul@188 | 48 | |
paul@188 | 49 | enum Regs |
paul@188 | 50 | { |
paul@188 | 51 | Pin_level = 0x000, // PxPINL (read-only) |
paul@188 | 52 | |
paul@188 | 53 | Port_int = 0x010, // PxINT |
paul@188 | 54 | Port_int_set = 0x014, // PxINTS |
paul@188 | 55 | Port_int_clear = 0x018, // PxINTC |
paul@188 | 56 | |
paul@188 | 57 | Irq_mask = 0x020, // PxMSK (for PxINT == 1) |
paul@188 | 58 | Irq_mask_set = 0x024, // PxMSKS |
paul@188 | 59 | Irq_mask_clear = 0x028, // PxMSKC |
paul@188 | 60 | Port_gpio = 0x020, // PxMSK (for PxINT == 0) |
paul@188 | 61 | Port_gpio_set = 0x024, // PxMSKS |
paul@188 | 62 | Port_gpio_clear = 0x028, // PxMSKC |
paul@188 | 63 | |
paul@188 | 64 | Port_trigger = 0x030, // PxPAT1 (for PxINT == 1) |
paul@188 | 65 | Port_trigger_set = 0x034, // PxPAT1S |
paul@188 | 66 | Port_trigger_clear = 0x038, // PxPAT1C |
paul@188 | 67 | Port_dir = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 1) |
paul@188 | 68 | Port_dir_set = 0x034, // PxPAT1S |
paul@188 | 69 | Port_dir_clear = 0x038, // PxPAT1C |
paul@188 | 70 | Port_group1 = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 0) |
paul@188 | 71 | Port_group1_set = 0x034, // PxPAT1S |
paul@188 | 72 | Port_group1_clear = 0x038, // PxPAT1C |
paul@188 | 73 | |
paul@188 | 74 | Port_level = 0x040, // PxPAT0 (for PxINT == 1) |
paul@188 | 75 | Port_level_set = 0x044, // PxPAT0S |
paul@188 | 76 | Port_level_clear = 0x048, // PxPAT0C |
paul@188 | 77 | Port_data = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 1, PxPAT1 == 0) |
paul@188 | 78 | Port_data_set = 0x044, // PxPAT0S |
paul@188 | 79 | Port_data_clear = 0x048, // PxPAT0C |
paul@188 | 80 | Port_group0 = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 0) |
paul@188 | 81 | Port_group0_set = 0x044, // PxPAT0S |
paul@188 | 82 | Port_group0_clear = 0x048, // PxPAT0C |
paul@188 | 83 | |
paul@188 | 84 | Irq_flag = 0x050, // PxFLG (read-only) |
paul@188 | 85 | Irq_flag_clear = 0x058, // PxFLGC |
paul@188 | 86 | |
paul@188 | 87 | // Only the following registers differ from the JZ4780. The dual-edge |
paul@188 | 88 | // registers being added to the X1600, with the pull-up/down registers being |
paul@189 | 89 | // relocated and their sense changed from disable to enable. |
paul@188 | 90 | |
paul@188 | 91 | Pull_edge = 0x070, // PxEDG |
paul@188 | 92 | Pull_edge_set = 0x074, // PxEDGS |
paul@188 | 93 | Pull_edge_clear = 0x078, // PxEDGC |
paul@188 | 94 | |
paul@189 | 95 | Pull_enable = 0x080, // PxPE |
paul@189 | 96 | Pull_enable_set = 0x084, // PxPES |
paul@189 | 97 | Pull_enable_clear = 0x088, // PxPEC |
paul@188 | 98 | |
paul@188 | 99 | // The shadow port Z is available at offset 0x700 and supports the INTS, INTC, |
paul@188 | 100 | // MSKS, MSKC, PAT1S, PAT1C, PAT0S, PAT0C registers, along with the following. |
paul@188 | 101 | |
paul@188 | 102 | Shadow_transfer = 0x0f0, // PzGID2LD |
paul@188 | 103 | }; |
paul@188 | 104 | |
paul@188 | 105 | |
paul@188 | 106 | |
paul@188 | 107 | // IRQ control for each GPIO pin. |
paul@188 | 108 | |
paul@188 | 109 | Gpio_x1600_irq_pin::Gpio_x1600_irq_pin(unsigned pin, Hw::Register_block<32> const ®s) |
paul@188 | 110 | : _pin(pin), _regs(regs) |
paul@188 | 111 | {} |
paul@188 | 112 | |
paul@188 | 113 | void |
paul@188 | 114 | Gpio_x1600_irq_pin::write_reg_pin(unsigned reg) |
paul@188 | 115 | { |
paul@188 | 116 | // Write the pin bit to the register, setting or clearing the pin |
paul@188 | 117 | // depending on the register chosen. |
paul@188 | 118 | |
paul@188 | 119 | _regs[reg] = _pin_bit(_pin); |
paul@188 | 120 | } |
paul@188 | 121 | |
paul@188 | 122 | void Gpio_x1600_irq_pin::do_mask() |
paul@188 | 123 | { |
paul@188 | 124 | // Set the interrupt bit in the PxIM register. |
paul@188 | 125 | |
paul@188 | 126 | write_reg_pin(Irq_mask_set); |
paul@188 | 127 | } |
paul@188 | 128 | |
paul@188 | 129 | void Gpio_x1600_irq_pin::do_unmask() |
paul@188 | 130 | { |
paul@188 | 131 | // Clear the interrupt bit in the PxIM register, first also clearing the |
paul@188 | 132 | // flag bit in the PxFLG register to allow interrupts to be delivered. |
paul@188 | 133 | |
paul@188 | 134 | write_reg_pin(Irq_flag_clear); |
paul@188 | 135 | write_reg_pin(Irq_mask_clear); |
paul@188 | 136 | } |
paul@188 | 137 | |
paul@188 | 138 | bool Gpio_x1600_irq_pin::do_set_mode(unsigned mode) |
paul@188 | 139 | { |
paul@188 | 140 | // Standard comment found for this method: |
paul@188 | 141 | // this operation touches multiple mmio registers and is thus |
paul@188 | 142 | // not atomic, that's why we first mask the IRQ and if it was |
paul@188 | 143 | // enabled we unmask it after we have changed the mode |
paul@188 | 144 | |
paul@188 | 145 | /* NOTE: The X1600 provides a special port Z that allows changes to be made |
paul@188 | 146 | and then committed atomically using PzGID2LD. This is not currently |
paul@188 | 147 | used. */ |
paul@188 | 148 | |
paul@188 | 149 | if (enabled()) |
paul@188 | 150 | do_mask(); |
paul@188 | 151 | |
paul@188 | 152 | // Do the PxINT, PxPAT1 and PxPAT0 configuration. |
paul@188 | 153 | |
paul@188 | 154 | switch(mode) |
paul@188 | 155 | { |
paul@188 | 156 | case L4_IRQ_F_LEVEL_HIGH: |
paul@188 | 157 | write_reg_pin(Port_int_set); |
paul@188 | 158 | write_reg_pin(Port_trigger_clear); |
paul@188 | 159 | write_reg_pin(Port_level_set); |
paul@188 | 160 | break; |
paul@188 | 161 | case L4_IRQ_F_LEVEL_LOW: |
paul@188 | 162 | write_reg_pin(Port_int_set); |
paul@188 | 163 | write_reg_pin(Port_trigger_clear); |
paul@188 | 164 | write_reg_pin(Port_level_clear); |
paul@188 | 165 | break; |
paul@188 | 166 | case L4_IRQ_F_POS_EDGE: |
paul@188 | 167 | write_reg_pin(Port_int_set); |
paul@188 | 168 | write_reg_pin(Port_trigger_set); |
paul@188 | 169 | write_reg_pin(Port_level_set); |
paul@188 | 170 | break; |
paul@188 | 171 | case L4_IRQ_F_NEG_EDGE: |
paul@188 | 172 | write_reg_pin(Port_int_set); |
paul@188 | 173 | write_reg_pin(Port_trigger_set); |
paul@188 | 174 | write_reg_pin(Port_level_clear); |
paul@188 | 175 | break; |
paul@188 | 176 | |
paul@188 | 177 | default: |
paul@188 | 178 | return false; |
paul@188 | 179 | } |
paul@188 | 180 | |
paul@188 | 181 | if (enabled()) |
paul@188 | 182 | do_unmask(); |
paul@188 | 183 | |
paul@188 | 184 | return true; |
paul@188 | 185 | } |
paul@188 | 186 | |
paul@188 | 187 | int Gpio_x1600_irq_pin::clear() |
paul@188 | 188 | { |
paul@188 | 189 | // Obtain the flag status for the pin, clearing it if set. |
paul@188 | 190 | |
paul@188 | 191 | l4_uint32_t e = _regs[Irq_flag] & (1UL << _pin); |
paul@188 | 192 | if (e) |
paul@188 | 193 | _regs[Irq_flag_clear] = e; |
paul@188 | 194 | |
paul@188 | 195 | return (e >> _pin); |
paul@188 | 196 | } |
paul@188 | 197 | |
paul@188 | 198 | bool Gpio_x1600_irq_pin::enabled() |
paul@188 | 199 | { |
paul@188 | 200 | return true; |
paul@188 | 201 | } |
paul@188 | 202 | |
paul@188 | 203 | |
paul@188 | 204 | |
paul@188 | 205 | // Initialise the GPIO controller. |
paul@188 | 206 | |
paul@188 | 207 | Gpio_x1600_chip::Gpio_x1600_chip(l4_addr_t start, l4_addr_t end, |
paul@188 | 208 | unsigned nr_pins, |
paul@188 | 209 | l4_uint32_t pull_ups, l4_uint32_t pull_downs) |
paul@188 | 210 | : _start(start), _end(end), |
paul@188 | 211 | _nr_pins(nr_pins), |
paul@188 | 212 | _pull_ups(pull_ups), _pull_downs(pull_downs) |
paul@188 | 213 | { |
paul@188 | 214 | _regs = new Hw::Mmio_register_block<32>(_start); |
paul@188 | 215 | } |
paul@188 | 216 | |
paul@188 | 217 | // Return the value of a pin. |
paul@188 | 218 | |
paul@188 | 219 | int |
paul@188 | 220 | Gpio_x1600_chip::get(unsigned pin) |
paul@188 | 221 | { |
paul@188 | 222 | if (pin >= _nr_pins) |
paul@188 | 223 | throw -L4_EINVAL; |
paul@188 | 224 | |
paul@188 | 225 | l4_uint32_t val = _regs[Pin_level]; |
paul@188 | 226 | return (val >> _pin_shift(pin)) & 1; |
paul@188 | 227 | } |
paul@188 | 228 | |
paul@188 | 229 | // Return multiple pin values. |
paul@188 | 230 | |
paul@188 | 231 | unsigned |
paul@188 | 232 | Gpio_x1600_chip::multi_get(unsigned offset) |
paul@188 | 233 | { |
paul@188 | 234 | _reg_offset_check(offset); |
paul@188 | 235 | return _regs[Pin_level]; |
paul@188 | 236 | } |
paul@188 | 237 | |
paul@188 | 238 | // Set the value of a pin. |
paul@188 | 239 | |
paul@188 | 240 | void |
paul@188 | 241 | Gpio_x1600_chip::set(unsigned pin, int value) |
paul@188 | 242 | { |
paul@188 | 243 | if (pin >= _nr_pins) |
paul@188 | 244 | throw -L4_EINVAL; |
paul@188 | 245 | |
paul@188 | 246 | l4_uint32_t reg_set = value ? Port_data_set : Port_data_clear; |
paul@188 | 247 | _regs[reg_set] = _pin_bit(pin); |
paul@188 | 248 | } |
paul@188 | 249 | |
paul@188 | 250 | // Set multiple pin values. |
paul@188 | 251 | |
paul@188 | 252 | void |
paul@188 | 253 | Gpio_x1600_chip::multi_set(Pin_slice const &mask, unsigned data) |
paul@188 | 254 | { |
paul@188 | 255 | _reg_offset_check(mask.offset); |
paul@188 | 256 | if (mask.mask & data) |
paul@188 | 257 | _regs[Port_data_set] = (mask.mask & data); |
paul@188 | 258 | if (mask.mask & ~data) |
paul@188 | 259 | _regs[Port_data_clear] = (mask.mask & ~data); |
paul@188 | 260 | } |
paul@188 | 261 | |
paul@188 | 262 | // Set a pin up with the given mode and value (if appropriate). |
paul@188 | 263 | |
paul@188 | 264 | void |
paul@188 | 265 | Gpio_x1600_chip::setup(unsigned pin, unsigned mode, int value) |
paul@188 | 266 | { |
paul@188 | 267 | if (pin >= _nr_pins) |
paul@188 | 268 | throw -L4_EINVAL; |
paul@188 | 269 | |
paul@188 | 270 | config(pin, mode); |
paul@188 | 271 | |
paul@188 | 272 | if (mode == Output) |
paul@188 | 273 | set(pin, value); |
paul@188 | 274 | } |
paul@188 | 275 | |
paul@188 | 276 | // Configuration of a pin using the generic input/output/IRQ mode. |
paul@188 | 277 | |
paul@188 | 278 | void |
paul@188 | 279 | Gpio_x1600_chip::config(unsigned pin, unsigned mode) |
paul@188 | 280 | { |
paul@188 | 281 | switch (mode) |
paul@188 | 282 | { |
paul@188 | 283 | case Input: |
paul@188 | 284 | _regs[Port_int_clear] = _pin_bit(pin); |
paul@188 | 285 | _regs[Port_gpio_set] = _pin_bit(pin); |
paul@188 | 286 | _regs[Port_dir_set] = _pin_bit(pin); |
paul@188 | 287 | break; |
paul@188 | 288 | case Output: |
paul@188 | 289 | _regs[Port_int_clear] = _pin_bit(pin); |
paul@188 | 290 | _regs[Port_gpio_set] = _pin_bit(pin); |
paul@188 | 291 | _regs[Port_dir_clear] = _pin_bit(pin); |
paul@188 | 292 | break; |
paul@188 | 293 | case Irq: |
paul@188 | 294 | _regs[Port_int_set] = _pin_bit(pin); |
paul@188 | 295 | // Other details depend on the actual trigger mode. |
paul@188 | 296 | break; |
paul@188 | 297 | default: |
paul@188 | 298 | break; |
paul@188 | 299 | } |
paul@188 | 300 | } |
paul@188 | 301 | |
paul@188 | 302 | // Pull-up/down configuration for a pin. |
paul@188 | 303 | |
paul@188 | 304 | void |
paul@188 | 305 | Gpio_x1600_chip::config_pull(unsigned pin, unsigned mode) |
paul@188 | 306 | { |
paul@188 | 307 | if (pin >= _nr_pins) |
paul@188 | 308 | throw -L4_EINVAL; |
paul@188 | 309 | |
paul@188 | 310 | switch (mode) |
paul@188 | 311 | { |
paul@188 | 312 | case Pull_none: |
paul@189 | 313 | _regs[Pull_enable_clear] = _pin_bit(pin); |
paul@188 | 314 | break; |
paul@188 | 315 | case Pull_down: |
paul@188 | 316 | if (_pin_bit(pin) & _pull_downs) |
paul@189 | 317 | _regs[Pull_enable_set] = _pin_bit(pin); |
paul@188 | 318 | break; |
paul@188 | 319 | case Pull_up: |
paul@188 | 320 | if (_pin_bit(pin) & _pull_ups) |
paul@189 | 321 | _regs[Pull_enable_set] = _pin_bit(pin); |
paul@188 | 322 | break; |
paul@188 | 323 | default: |
paul@188 | 324 | // Invalid pull-up/down mode for pin. |
paul@188 | 325 | throw -L4_EINVAL; |
paul@188 | 326 | } |
paul@188 | 327 | } |
paul@188 | 328 | |
paul@188 | 329 | // Pin function configuration. |
paul@188 | 330 | |
paul@188 | 331 | void |
paul@188 | 332 | Gpio_x1600_chip::config_pad(unsigned pin, unsigned func, unsigned value) |
paul@188 | 333 | { |
paul@188 | 334 | if (pin >= _nr_pins) |
paul@188 | 335 | throw -L4_EINVAL; |
paul@188 | 336 | |
paul@188 | 337 | if (value > 3) |
paul@188 | 338 | throw -L4_EINVAL; |
paul@188 | 339 | |
paul@188 | 340 | switch (func) |
paul@188 | 341 | { |
paul@188 | 342 | // Support two different outputs. |
paul@188 | 343 | |
paul@188 | 344 | case Hw::Gpio_chip::Function_gpio: |
paul@188 | 345 | _regs[Port_int_clear] = _pin_bit(pin); |
paul@188 | 346 | _regs[Port_gpio_set] = _pin_bit(pin); |
paul@188 | 347 | _regs[value & 1 ? Port_data_set : Port_data_clear] = _pin_bit(pin); |
paul@188 | 348 | break; |
paul@188 | 349 | |
paul@188 | 350 | // Support four different device functions. |
paul@188 | 351 | |
paul@188 | 352 | case Hw::Gpio_chip::Function_alt: |
paul@188 | 353 | _regs[Port_int_clear] = _pin_bit(pin); |
paul@188 | 354 | _regs[Port_gpio_clear] = _pin_bit(pin); |
paul@188 | 355 | _regs[value & 2 ? Port_group1_set : Port_group1_clear] = _pin_bit(pin); |
paul@188 | 356 | _regs[value & 1 ? Port_group0_set : Port_group0_clear] = _pin_bit(pin); |
paul@188 | 357 | break; |
paul@188 | 358 | default: |
paul@188 | 359 | throw -L4_EINVAL; |
paul@188 | 360 | } |
paul@188 | 361 | } |
paul@188 | 362 | |
paul@188 | 363 | // Obtain a pin's configuration from a register in the supplied value. |
paul@188 | 364 | |
paul@188 | 365 | void |
paul@188 | 366 | Gpio_x1600_chip::config_get(unsigned pin, unsigned reg, unsigned *value) |
paul@188 | 367 | { |
paul@188 | 368 | if (pin >= _nr_pins) |
paul@188 | 369 | throw -L4_EINVAL; |
paul@188 | 370 | |
paul@188 | 371 | *value = (_regs[reg] >> _pin_shift(pin)) & 1; |
paul@188 | 372 | } |
paul@188 | 373 | |
paul@188 | 374 | // Return function and function-specific configuration for a pin. |
paul@188 | 375 | |
paul@188 | 376 | void |
paul@188 | 377 | Gpio_x1600_chip::config_pad_get(unsigned pin, unsigned *func, unsigned *value) |
paul@188 | 378 | { |
paul@188 | 379 | unsigned direction, gpio, group0, group1, interrupt, level, trigger; |
paul@188 | 380 | |
paul@188 | 381 | config_get(pin, Port_int, &interrupt); |
paul@188 | 382 | |
paul@188 | 383 | if (interrupt) |
paul@188 | 384 | { |
paul@188 | 385 | config_get(pin, Port_trigger, &trigger); |
paul@188 | 386 | config_get(pin, Port_level, &level); |
paul@188 | 387 | |
paul@188 | 388 | *func = Hw::Gpio_chip::Function_irq; |
paul@188 | 389 | *value = (trigger ? (level ? L4_IRQ_F_POS_EDGE : L4_IRQ_F_NEG_EDGE) |
paul@188 | 390 | : (level ? L4_IRQ_F_LEVEL_HIGH : L4_IRQ_F_LEVEL_LOW)); |
paul@188 | 391 | return; |
paul@188 | 392 | } |
paul@188 | 393 | |
paul@188 | 394 | config_get(pin, Port_gpio, &gpio); |
paul@188 | 395 | |
paul@188 | 396 | if (gpio) |
paul@188 | 397 | { |
paul@188 | 398 | config_get(pin, Port_dir, &direction); |
paul@188 | 399 | |
paul@188 | 400 | *func = Hw::Gpio_chip::Function_gpio; |
paul@188 | 401 | *value = direction ? Input : Output; |
paul@188 | 402 | return; |
paul@188 | 403 | } |
paul@188 | 404 | |
paul@188 | 405 | *func = Hw::Gpio_chip::Function_alt; |
paul@188 | 406 | |
paul@188 | 407 | config_get(pin, Port_group0, &group0); |
paul@188 | 408 | config_get(pin, Port_group1, &group1); |
paul@188 | 409 | |
paul@188 | 410 | *value = (group1 << 1) | group0; |
paul@188 | 411 | } |
paul@188 | 412 | |
paul@188 | 413 | // Obtain an IRQ abstraction for a pin. |
paul@188 | 414 | |
paul@188 | 415 | Hw::Gpio_irq_pin * |
paul@188 | 416 | Gpio_x1600_chip::get_irq(unsigned pin) |
paul@188 | 417 | { |
paul@188 | 418 | if (pin >= _nr_pins) |
paul@188 | 419 | throw -L4_EINVAL; |
paul@188 | 420 | |
paul@188 | 421 | return new Gpio_x1600_irq_pin(pin, _regs); |
paul@188 | 422 | } |
paul@188 | 423 | |
paul@188 | 424 | // Pin function configuration for multiple pins. |
paul@188 | 425 | |
paul@188 | 426 | void |
paul@188 | 427 | Gpio_x1600_chip::multi_config_pad(Pin_slice const &mask, unsigned func, unsigned val) |
paul@188 | 428 | { |
paul@188 | 429 | unsigned m = mask.mask; |
paul@188 | 430 | for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1) |
paul@188 | 431 | if (m & 1) |
paul@188 | 432 | config_pad(pin, func, val); |
paul@188 | 433 | } |
paul@188 | 434 | |
paul@188 | 435 | // Set up multiple pins with the given mode. |
paul@188 | 436 | |
paul@188 | 437 | void |
paul@188 | 438 | Gpio_x1600_chip::multi_setup(Pin_slice const &mask, unsigned mode, unsigned outvalues) |
paul@188 | 439 | { |
paul@188 | 440 | unsigned m = mask.mask; |
paul@188 | 441 | for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1, outvalues >>= 1) |
paul@188 | 442 | if (m & 1) |
paul@188 | 443 | setup(pin, mode, outvalues & 1); |
paul@188 | 444 | } |
paul@188 | 445 | |
paul@188 | 446 | |
paul@188 | 447 | |
paul@188 | 448 | // C language interface functions. |
paul@188 | 449 | |
paul@188 | 450 | void *x1600_gpio_init(l4_addr_t start, l4_addr_t end, unsigned pins, |
paul@188 | 451 | l4_uint32_t pull_ups, l4_uint32_t pull_downs) |
paul@188 | 452 | { |
paul@188 | 453 | return (void *) new Gpio_x1600_chip(start, end, pins, pull_ups, pull_downs); |
paul@188 | 454 | } |
paul@188 | 455 | |
paul@188 | 456 | void x1600_gpio_setup(void *gpio, unsigned pin, unsigned mode, int value) |
paul@188 | 457 | { |
paul@188 | 458 | static_cast<Gpio_x1600_chip *>(gpio)->setup(pin, mode, value); |
paul@188 | 459 | } |
paul@188 | 460 | |
paul@188 | 461 | void x1600_gpio_config_pull(void *gpio, unsigned pin, unsigned mode) |
paul@188 | 462 | { |
paul@188 | 463 | static_cast<Gpio_x1600_chip *>(gpio)->config_pull(pin, mode); |
paul@188 | 464 | } |
paul@188 | 465 | |
paul@188 | 466 | void x1600_gpio_config_pad(void *gpio, unsigned pin, unsigned func, unsigned value) |
paul@188 | 467 | { |
paul@188 | 468 | static_cast<Gpio_x1600_chip *>(gpio)->config_pad(pin, func, value); |
paul@188 | 469 | } |
paul@188 | 470 | |
paul@188 | 471 | void x1600_gpio_config_get(void *gpio, unsigned pin, unsigned reg, unsigned *value) |
paul@188 | 472 | { |
paul@188 | 473 | static_cast<Gpio_x1600_chip *>(gpio)->config_get(pin, reg, value); |
paul@188 | 474 | } |
paul@188 | 475 | |
paul@188 | 476 | void x1600_gpio_config_pad_get(void *gpio, unsigned pin, unsigned *func, unsigned *value) |
paul@188 | 477 | { |
paul@188 | 478 | static_cast<Gpio_x1600_chip *>(gpio)->config_pad_get(pin, func, value); |
paul@188 | 479 | } |
paul@188 | 480 | |
paul@188 | 481 | void x1600_gpio_multi_setup(void *gpio, Pin_slice const *mask, unsigned mode, unsigned outvalues) |
paul@188 | 482 | { |
paul@188 | 483 | static_cast<Gpio_x1600_chip *>(gpio)->multi_setup(*mask, mode, outvalues); |
paul@188 | 484 | } |
paul@188 | 485 | |
paul@188 | 486 | void x1600_gpio_multi_config_pad(void *gpio, Pin_slice const *mask, unsigned func, unsigned value) |
paul@188 | 487 | { |
paul@188 | 488 | static_cast<Gpio_x1600_chip *>(gpio)->multi_config_pad(*mask, func, value); |
paul@188 | 489 | } |
paul@188 | 490 | |
paul@188 | 491 | void x1600_gpio_multi_set(void *gpio, Pin_slice const *mask, unsigned data) |
paul@188 | 492 | { |
paul@188 | 493 | static_cast<Gpio_x1600_chip *>(gpio)->multi_set(*mask, data); |
paul@188 | 494 | } |
paul@188 | 495 | |
paul@188 | 496 | unsigned x1600_gpio_multi_get(void *gpio, unsigned offset) |
paul@188 | 497 | { |
paul@188 | 498 | return static_cast<Gpio_x1600_chip *>(gpio)->multi_get(offset); |
paul@188 | 499 | } |
paul@188 | 500 | |
paul@188 | 501 | int x1600_gpio_get(void *gpio, unsigned pin) |
paul@188 | 502 | { |
paul@188 | 503 | return static_cast<Gpio_x1600_chip *>(gpio)->get(pin); |
paul@188 | 504 | } |
paul@188 | 505 | |
paul@188 | 506 | void x1600_gpio_set(void *gpio, unsigned pin, int value) |
paul@188 | 507 | { |
paul@188 | 508 | static_cast<Gpio_x1600_chip *>(gpio)->set(pin, value); |
paul@188 | 509 | } |
paul@188 | 510 | |
paul@188 | 511 | void *x1600_gpio_get_irq(void *gpio, unsigned pin) |
paul@188 | 512 | { |
paul@188 | 513 | return (void *) static_cast<Gpio_x1600_chip *>(gpio)->get_irq(pin); |
paul@188 | 514 | } |
paul@188 | 515 | |
paul@188 | 516 | bool x1600_gpio_irq_set_mode(void *gpio_irq, unsigned mode) |
paul@188 | 517 | { |
paul@188 | 518 | return static_cast<Hw::Gpio_irq_pin *>(gpio_irq)->do_set_mode(mode); |
paul@188 | 519 | } |