paul@190 | 1 | /* |
paul@190 | 2 | * I2C support for the X1600. |
paul@190 | 3 | * |
paul@190 | 4 | * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@190 | 5 | * |
paul@190 | 6 | * This program is free software; you can redistribute it and/or |
paul@190 | 7 | * modify it under the terms of the GNU General Public License as |
paul@190 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@190 | 9 | * the License, or (at your option) any later version. |
paul@190 | 10 | * |
paul@190 | 11 | * This program is distributed in the hope that it will be useful, |
paul@190 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@190 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@190 | 14 | * GNU General Public License for more details. |
paul@190 | 15 | * |
paul@190 | 16 | * You should have received a copy of the GNU General Public License |
paul@190 | 17 | * along with this program; if not, write to the Free Software |
paul@190 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@190 | 19 | * Boston, MA 02110-1301, USA |
paul@190 | 20 | */ |
paul@190 | 21 | |
paul@190 | 22 | #include <l4/devices/i2c-x1600.h> |
paul@190 | 23 | #include <l4/devices/hw_mmio_register_block.h> |
paul@190 | 24 | |
paul@190 | 25 | #include <l4/sys/icu.h> |
paul@190 | 26 | #include <l4/util/util.h> |
paul@190 | 27 | #include <sys/time.h> |
paul@190 | 28 | |
paul@190 | 29 | #include <stdio.h> |
paul@190 | 30 | |
paul@190 | 31 | /* NOTE: This peripheral is very similar to the JZ4780 with the registers |
paul@190 | 32 | renamed to I2C from I2C, with a few high speed registers added, and |
paul@190 | 33 | with I2C_SDAHD appearing at a different location. */ |
paul@190 | 34 | |
paul@190 | 35 | enum Regs |
paul@190 | 36 | { |
paul@190 | 37 | I2c_control = 0x000, // I2C_CON |
paul@190 | 38 | I2c_target_address = 0x004, // I2C_TAR |
paul@190 | 39 | I2c_slave_address = 0x008, // I2C_SAR |
paul@190 | 40 | I2c_master_code = 0x00c, // I2C_HS_MADDR |
paul@190 | 41 | I2c_data_command = 0x010, // I2C_DC |
paul@190 | 42 | Std_high_count = 0x014, // I2C_SHCNT |
paul@190 | 43 | Std_low_count = 0x018, // I2C_SLCNT |
paul@190 | 44 | Fast_high_count = 0x01c, // I2C_FHCNT |
paul@190 | 45 | Fast_low_count = 0x020, // I2C_FLCNT |
paul@190 | 46 | High_high_count = 0x024, // I2C_HHCNT |
paul@190 | 47 | High_low_count = 0x028, // I2C_HLCNT |
paul@190 | 48 | Int_status = 0x02c, // I2C_INTST (read-only) |
paul@190 | 49 | Int_mask = 0x030, // I2C_INTM |
paul@190 | 50 | Int_raw_status = 0x034, // I2C_RINTST (read-only) |
paul@190 | 51 | Rx_fifo_thold = 0x038, // I2C_RXTL |
paul@190 | 52 | Tx_fifo_thold = 0x03c, // I2C_TXTL |
paul@190 | 53 | Int_combined_clear = 0x040, // I2C_CINT (read-only) |
paul@190 | 54 | Int_rx_uf_clear = 0x044, // I2C_CRXUF (read-only) |
paul@190 | 55 | Int_rx_of_clear = 0x048, // I2C_CRXOF (read-only) |
paul@190 | 56 | Int_tx_of_clear = 0x04c, // I2C_CTXOF (read-only) |
paul@190 | 57 | Int_rd_req_clear = 0x050, // I2C_CRXREQ (read-only) |
paul@190 | 58 | Int_tx_abort_clear = 0x054, // I2C_CTXABT (read-only) |
paul@190 | 59 | Int_rx_done_clear = 0x058, // I2C_CRXDN (read-only) |
paul@190 | 60 | Int_activity_clear = 0x05c, // I2C_CACT (read-only) |
paul@190 | 61 | Int_stop_clear = 0x060, // I2C_CSTP (read-only) |
paul@190 | 62 | Int_start_clear = 0x064, // I2C_CSTT (read-only) |
paul@190 | 63 | Int_call_clear = 0x068, // I2C_CGC (read-only) |
paul@190 | 64 | I2c_enable = 0x06c, // I2C_ENB |
paul@190 | 65 | I2c_status = 0x070, // I2C_ST (read-only) |
paul@190 | 66 | Tx_fifo_count = 0x074, // I2C_TXFLR (read-only) |
paul@190 | 67 | Rx_fifo_count = 0x078, // I2C_RXFLR (read-only) |
paul@190 | 68 | I2c_sda_hold_time = 0x07c, // I2C_SDAHD |
paul@190 | 69 | Trans_abort_status = 0x080, // I2C_ABTSRC (read-only) |
paul@190 | 70 | Slv_data_nack = 0x084, // I2CSDNACK |
paul@190 | 71 | I2c_dma_ctrl = 0x088, // I2C_DMACR |
paul@190 | 72 | I2c_trans_data_lvl = 0x08c, // I2C_DMATDLR |
paul@190 | 73 | I2c_recv_data_lvl = 0x090, // I2C_DMARDLR |
paul@190 | 74 | I2c_sda_setup_time = 0x094, // I2C_SDASU |
paul@190 | 75 | I2c_ack_call = 0x098, // I2C_ACKGC |
paul@190 | 76 | I2c_enable_status = 0x09c, // I2C_ENBST (read-only) |
paul@190 | 77 | I2c_spike_suppress = 0x0a0, // I2C_FSPKLEN |
paul@190 | 78 | |
paul@190 | 79 | I2c_block_offset = 0x1000 |
paul@190 | 80 | }; |
paul@190 | 81 | |
paul@190 | 82 | enum I2c_control_bits : unsigned |
paul@190 | 83 | { |
paul@190 | 84 | I2c_disable_slave = 0x40, // SLVDIS (slave disabled) |
paul@190 | 85 | I2c_enable_restart = 0x20, // RESTART |
paul@190 | 86 | I2c_master_10bit = 0x10, // MATP (read-only) |
paul@190 | 87 | I2c_slave_10bit = 0x08, // SATP |
paul@190 | 88 | I2c_speed_mode_mask = 0x06, // SPEED |
paul@190 | 89 | I2c_enable_master = 0x01, // MD (master enabled) |
paul@190 | 90 | I2c_speed_bit = 1, // SPD |
paul@190 | 91 | }; |
paul@190 | 92 | |
paul@190 | 93 | enum I2c_speed_mode_values : unsigned |
paul@190 | 94 | { |
paul@190 | 95 | I2c_speed_standard = 1, |
paul@190 | 96 | I2c_speed_fast = 2, |
paul@190 | 97 | I2c_speed_high = 3, |
paul@190 | 98 | }; |
paul@190 | 99 | |
paul@190 | 100 | enum I2c_enable_bits : unsigned |
paul@190 | 101 | { |
paul@190 | 102 | I2c_enable_enabled = 0x01, // I2CEN |
paul@190 | 103 | }; |
paul@190 | 104 | |
paul@190 | 105 | enum I2c_status_bits : unsigned |
paul@190 | 106 | { |
paul@190 | 107 | I2c_status_master_act = 0x20, // MSTACT (master active) |
paul@190 | 108 | I2c_status_rx_nempty = 0x08, // RFNE (read queue not empty) |
paul@190 | 109 | I2c_status_tx_empty = 0x04, // TFE (write queue empty) |
paul@190 | 110 | I2c_status_tx_nfull = 0x02, // TFNF (write queue not full) |
paul@190 | 111 | I2c_status_active = 0x01, // ACT (device active as master or slave) |
paul@190 | 112 | }; |
paul@190 | 113 | |
paul@190 | 114 | enum I2c_target_bits : unsigned |
paul@190 | 115 | { |
paul@190 | 116 | I2c_target_master_10bit = 0x1000, |
paul@190 | 117 | I2c_target_special = 0x0800, // SPECIAL: perform general call or start byte |
paul@190 | 118 | I2c_target_start_byte = 0x0400, // Special: start byte (1) or general call (0) |
paul@190 | 119 | I2c_target_10bits = 0x3ff, // Mask for 10-bit address |
paul@190 | 120 | I2c_target_7bits = 0x7f, // Mask for 7-bit address |
paul@190 | 121 | }; |
paul@190 | 122 | |
paul@190 | 123 | enum I2c_hold_control_bits : unsigned |
paul@190 | 124 | { |
paul@190 | 125 | /* The hold enable flag has been removed since the JZ4780 and the hold time |
paul@190 | 126 | field widened. */ |
paul@190 | 127 | |
paul@190 | 128 | I2c_hold_mask = 0xffff, |
paul@190 | 129 | }; |
paul@190 | 130 | |
paul@190 | 131 | enum I2c_setup_control_bits : unsigned |
paul@190 | 132 | { |
paul@190 | 133 | I2c_setup_mask = 0x0ff, // SDASU |
paul@190 | 134 | }; |
paul@190 | 135 | |
paul@190 | 136 | enum I2c_command_bits : unsigned |
paul@190 | 137 | { |
paul@190 | 138 | I2c_command_restart = 0x400, // RESTART: explicit restart before next byte |
paul@190 | 139 | I2c_command_stop = 0x200, // STOP: explicit stop after next byte |
paul@190 | 140 | I2c_command_no_stop = 0x000, |
paul@190 | 141 | I2c_command_read = 0x100, // CMD |
paul@190 | 142 | I2c_command_write = 0x000, // CMD |
paul@190 | 143 | }; |
paul@190 | 144 | |
paul@190 | 145 | enum I2c_fifo_bits : unsigned |
paul@190 | 146 | { |
paul@190 | 147 | I2c_fifo_limit = 64, // RXTL, TXTL (256 noted in field description) |
paul@190 | 148 | }; |
paul@190 | 149 | |
paul@190 | 150 | enum Int_bits : unsigned |
paul@190 | 151 | { |
paul@190 | 152 | Int_call = 0x800, // IGC (general call received) |
paul@190 | 153 | Int_start = 0x400, // ISTT (start/restart condition occurred) |
paul@190 | 154 | Int_stop = 0x200, // ISTP (stop condition occurred) |
paul@190 | 155 | Int_activity = 0x100, // IACT (bus activity interrupt) |
paul@190 | 156 | Int_rx_done = 0x080, // RXDN (read from master device done) |
paul@190 | 157 | Int_tx_abort = 0x040, // TXABT (transmit abort) |
paul@190 | 158 | Int_rd_req = 0x020, // RDREQ (read request from master device) |
paul@190 | 159 | Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) |
paul@190 | 160 | Int_tx_of = 0x008, // TXOF (overflow when writing to queue) |
paul@190 | 161 | Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) |
paul@190 | 162 | Int_rx_of = 0x002, // RXOF (overflow from device) |
paul@190 | 163 | Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) |
paul@190 | 164 | }; |
paul@190 | 165 | |
paul@190 | 166 | |
paul@190 | 167 | |
paul@190 | 168 | // Initialise a channel. |
paul@190 | 169 | |
paul@190 | 170 | I2c_x1600_channel::I2c_x1600_channel(l4_addr_t start, |
paul@190 | 171 | Cpm_x1600_chip *cpm, |
paul@190 | 172 | uint32_t frequency) |
paul@190 | 173 | : _cpm(cpm), _frequency(frequency) |
paul@190 | 174 | { |
paul@190 | 175 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@190 | 176 | } |
paul@190 | 177 | |
paul@190 | 178 | // Enable the channel. |
paul@190 | 179 | |
paul@190 | 180 | void |
paul@190 | 181 | I2c_x1600_channel::enable() |
paul@190 | 182 | { |
paul@190 | 183 | _regs[I2c_enable] = I2c_enable_enabled; |
paul@190 | 184 | while (!(_regs[I2c_enable_status] & I2c_enable_enabled)); |
paul@190 | 185 | } |
paul@190 | 186 | |
paul@190 | 187 | // Disable the channel. |
paul@190 | 188 | |
paul@190 | 189 | void |
paul@190 | 190 | I2c_x1600_channel::disable() |
paul@190 | 191 | { |
paul@190 | 192 | _regs[I2c_enable] = 0; |
paul@190 | 193 | while (_regs[I2c_enable_status] & I2c_enable_enabled); |
paul@190 | 194 | } |
paul@190 | 195 | |
paul@190 | 196 | // Return the configured frequency. |
paul@190 | 197 | |
paul@190 | 198 | uint32_t |
paul@190 | 199 | I2c_x1600_channel::get_frequency() |
paul@190 | 200 | { |
paul@190 | 201 | return _frequency; |
paul@190 | 202 | } |
paul@190 | 203 | |
paul@190 | 204 | // Set the frequency-related peripheral parameters. |
paul@190 | 205 | |
paul@190 | 206 | void |
paul@190 | 207 | I2c_x1600_channel::set_frequency() |
paul@190 | 208 | { |
paul@190 | 209 | // The APB clock (PCLK) is used to drive I2C transfers. Its value must be |
paul@190 | 210 | // obtained from the CPM unit. It is known as I2C_DEV_CLK here and is scaled |
paul@190 | 211 | // to kHz in order to keep the numbers easily representable, as is the bus |
paul@190 | 212 | // frequency. |
paul@190 | 213 | |
paul@190 | 214 | uint32_t i2c_dev_clk = _cpm->get_frequency(Clock_pclock) / 1000; |
paul@190 | 215 | |
paul@190 | 216 | // Note that this is not I2C_DEV_CLK but the actual I2C bus frequency. |
paul@190 | 217 | |
paul@190 | 218 | uint32_t i2c_clk = _frequency / 1000; |
paul@190 | 219 | |
paul@190 | 220 | // Select the appropriate speed. |
paul@190 | 221 | |
paul@190 | 222 | unsigned int speed = (i2c_clk <= 100) ? I2c_speed_standard |
paul@190 | 223 | : (i2c_clk <= 400 ? I2c_speed_fast |
paul@190 | 224 | : I2c_speed_high); |
paul@190 | 225 | |
paul@190 | 226 | _regs[I2c_control] = _regs[I2c_control] | (speed << I2c_speed_bit) | |
paul@190 | 227 | I2c_disable_slave | |
paul@190 | 228 | I2c_enable_restart | |
paul@190 | 229 | I2c_enable_master; |
paul@190 | 230 | |
paul@190 | 231 | // According to the programming manual, if the PCLK period is T{I2C_DEV_CLK} |
paul@190 | 232 | // then the I2C clock period is... |
paul@190 | 233 | |
paul@190 | 234 | // T{SCL} = T{SCL_high} + T{SCL_low} |
paul@190 | 235 | |
paul@190 | 236 | // Where... |
paul@190 | 237 | |
paul@190 | 238 | // T{SCL_low} = T{I2C_DEV_CLK} * (#cycles for low signal) |
paul@190 | 239 | // T{SCL_high} = T{I2C_DEV_CLK} * (#cycles for high signal) |
paul@190 | 240 | |
paul@190 | 241 | // Since, with minimum periods being defined... |
paul@190 | 242 | |
paul@190 | 243 | // T{SCL} >= T{min_SCL} |
paul@190 | 244 | // T{SCL_low} >= T{min_SCL_low} |
paul@190 | 245 | // T{SCL_high} >= T{min_SCL_high} |
paul@190 | 246 | // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} |
paul@190 | 247 | |
paul@190 | 248 | // Then the following applies... |
paul@190 | 249 | |
paul@190 | 250 | // T{I2C_DEV_CLK} * (#cycles for low signal)) >= T{min_SCL_low} |
paul@190 | 251 | // T{I2C_DEV_CLK} * (#cycles for high signal) >= T{min_SCL_high} |
paul@190 | 252 | |
paul@190 | 253 | // To work with different clock speeds while maintaining the low-to-high |
paul@190 | 254 | // ratios: |
paul@190 | 255 | |
paul@190 | 256 | // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} |
paul@190 | 257 | // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) |
paul@190 | 258 | |
paul@190 | 259 | // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} |
paul@190 | 260 | // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) |
paul@190 | 261 | |
paul@190 | 262 | // Constraints are given with respect to the high and low count registers. |
paul@190 | 263 | |
paul@190 | 264 | // #cycles for high signal = I2CxHCNT + 8 |
paul@190 | 265 | // #cycles for low signal = I2CxLCNT + 1 |
paul@190 | 266 | |
paul@190 | 267 | // From earlier, this yields... |
paul@190 | 268 | |
paul@190 | 269 | // T{I2C_DEV_CLK} * (I2CxLCNT + 1) >= T{min_SCL_low} |
paul@190 | 270 | // T{I2C_DEV_CLK} * (I2CxHCNT + 8) >= T{min_SCL_high} |
paul@190 | 271 | |
paul@190 | 272 | // Rearranging... |
paul@190 | 273 | |
paul@190 | 274 | // I2CxLCNT >= (T{min_SCL_low} / T{I2C_DEV_CLK}) - 1 |
paul@190 | 275 | // >= T{min_SCL_low} * I2C_DEV_CLK - 1 |
paul@190 | 276 | |
paul@190 | 277 | // I2CxHCNT >= (T{min_SCL_high} / T{I2C_DEV_CLK}) - 8 |
paul@190 | 278 | // >= T{min_SCL_high} * I2C_DEV_CLK - 8 |
paul@190 | 279 | |
paul@190 | 280 | // Introducing the definitions for the high and low periods... |
paul@190 | 281 | |
paul@190 | 282 | // I2CxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 1 |
paul@190 | 283 | // >= (T{min_SCL_low} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 1 |
paul@190 | 284 | |
paul@190 | 285 | // I2CxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 8 |
paul@190 | 286 | // >= (T{min_SCL_high} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 8 |
paul@190 | 287 | |
paul@190 | 288 | uint32_t high_reg, low_reg; |
paul@190 | 289 | uint32_t high_count, low_count; |
paul@190 | 290 | int32_t hold_count; |
paul@190 | 291 | uint32_t setup_count; |
paul@190 | 292 | |
paul@190 | 293 | // Level hold times: |
paul@190 | 294 | |
paul@190 | 295 | // Standard Fast High |
paul@190 | 296 | // SCL low 4.7us 1.3us 0.5us |
paul@190 | 297 | // SCL high 4.0us 0.6us 0.26us + |
paul@190 | 298 | // SCL period 8.7us 1.9us 0.76us = |
paul@190 | 299 | |
paul@190 | 300 | // See: UM10204 "I2C-bus specification and user manual" |
paul@190 | 301 | // Table 10: t{LOW} and t{HIGH} |
paul@190 | 302 | |
paul@190 | 303 | if (i2c_clk <= 100) // 100 kHz |
paul@190 | 304 | { |
paul@190 | 305 | low_count = (i2c_dev_clk * 47) / (i2c_clk * 87) - 1; |
paul@190 | 306 | high_count = (i2c_dev_clk * 40) / (i2c_clk * 87) - 8; |
paul@190 | 307 | low_reg = Std_low_count; |
paul@190 | 308 | high_reg = Std_high_count; |
paul@190 | 309 | } |
paul@190 | 310 | else if (i2c_clk <= 400) // 400 kHz |
paul@190 | 311 | { |
paul@190 | 312 | low_count = (i2c_dev_clk * 13) / (i2c_clk * 19) - 1; |
paul@190 | 313 | high_count = (i2c_dev_clk * 6) / (i2c_clk * 19) - 8; |
paul@190 | 314 | low_reg = Fast_low_count; |
paul@190 | 315 | high_reg = Fast_high_count; |
paul@190 | 316 | } |
paul@190 | 317 | else // > 400 kHz |
paul@190 | 318 | { |
paul@190 | 319 | // Note how the frequencies are scaled to accommodate the extra precision |
paul@190 | 320 | // required. |
paul@190 | 321 | |
paul@190 | 322 | low_count = (i2c_dev_clk / 10 * 50) / (i2c_clk / 10 * 76) - 1; |
paul@190 | 323 | high_count = (i2c_dev_clk / 10 * 26) / (i2c_clk / 10 * 76) - 8; |
paul@190 | 324 | low_reg = High_low_count; |
paul@190 | 325 | high_reg = High_high_count; |
paul@190 | 326 | } |
paul@190 | 327 | |
paul@190 | 328 | // Minimum counts are 8 and 6 for low and high respectively. |
paul@190 | 329 | |
paul@190 | 330 | _regs[low_reg] = low_count < 8 ? 8 : low_count; |
paul@190 | 331 | _regs[high_reg] = high_count < 6 ? 6 : high_count; |
paul@190 | 332 | |
paul@190 | 333 | //printf("low_count: %d\n", low_count); |
paul@190 | 334 | //printf("high_count: %d\n", high_count); |
paul@190 | 335 | |
paul@190 | 336 | // Data hold and setup times: |
paul@190 | 337 | |
paul@190 | 338 | // Standard Fast High |
paul@190 | 339 | // t{HD;DAT} 300ns 300ns 300ns |
paul@190 | 340 | // t{SU;DAT} 250ns 100ns 50ns |
paul@190 | 341 | |
paul@190 | 342 | // See: UM10204 "I2C-bus specification and user manual" |
paul@190 | 343 | // Table 10: t{HD;DAT} and t{SU;DAT}, also note [3] |
paul@190 | 344 | |
paul@190 | 345 | // T{delay} = (I2CSDAHD + 2) * T{I2C_DEV_CLK} |
paul@190 | 346 | // I2CSDAHD = T{delay} / T{I2C_DEV_CLK} - 2 |
paul@190 | 347 | // I2CSDAHD = I2C_DEV_CLK * T{delay} - 2 |
paul@190 | 348 | |
paul@190 | 349 | // Since the device clock is in kHz (scaled down by 1000) and the times are |
paul@190 | 350 | // given in ns (scaled up by 1000000000), a division of 1000000 is introduced. |
paul@190 | 351 | |
paul@190 | 352 | hold_count = (i2c_dev_clk * 300) / 1000000 - 1; |
paul@190 | 353 | |
paul@190 | 354 | _regs[I2c_sda_hold_time] = (_regs[I2c_sda_hold_time] & ~I2c_hold_mask) | |
paul@190 | 355 | (hold_count < 0 ? 0 |
paul@190 | 356 | : (hold_count < (int) I2c_hold_mask ? (uint32_t) hold_count |
paul@190 | 357 | : I2c_hold_mask)); |
paul@190 | 358 | |
paul@190 | 359 | //printf("i2c_dev_clk: %d\n", i2c_dev_clk); |
paul@190 | 360 | //printf("SDA hold: %x\n", hold_count); |
paul@190 | 361 | |
paul@190 | 362 | // I2C_SDASU is apparently not used in master mode. |
paul@190 | 363 | |
paul@190 | 364 | // T{delay} = (I2CSDASU - 1) * T{I2C_DEV_CLK} |
paul@190 | 365 | // I2CSDASU = T{delay} / T{I2C_DEV_CLK} + 1 |
paul@190 | 366 | // I2CSDASU = I2C_DEV_CLK * T{delay} + 1 |
paul@190 | 367 | |
paul@190 | 368 | if (i2c_clk <= 100) |
paul@190 | 369 | setup_count = (i2c_dev_clk * 250) / 1000000 + 1; |
paul@190 | 370 | else if (i2c_clk <= 400) |
paul@190 | 371 | setup_count = (i2c_dev_clk * 100) / 1000000 + 1; |
paul@190 | 372 | else |
paul@190 | 373 | setup_count = (i2c_dev_clk * 50) / 1000000 + 1; |
paul@190 | 374 | |
paul@190 | 375 | _regs[I2c_sda_setup_time] = (_regs[I2c_sda_setup_time] & ~I2c_setup_mask) | |
paul@190 | 376 | (setup_count < I2c_setup_mask ? setup_count : I2c_setup_mask); |
paul@190 | 377 | } |
paul@190 | 378 | |
paul@190 | 379 | // Set the target address and enable transfer. |
paul@190 | 380 | // NOTE: Only supporting 7-bit addresses currently. |
paul@190 | 381 | |
paul@190 | 382 | void |
paul@190 | 383 | I2c_x1600_channel::set_target(uint8_t address) |
paul@190 | 384 | { |
paul@190 | 385 | //printf("set_target: %x\n", address); |
paul@190 | 386 | disable(); |
paul@190 | 387 | set_frequency(); |
paul@190 | 388 | _regs[I2c_target_address] = address & I2c_target_7bits; |
paul@190 | 389 | enable(); |
paul@190 | 390 | init_parameters(); |
paul@190 | 391 | //printf("I2c_enable_status: %x\n", (uint32_t) _regs[I2c_enable_status]); |
paul@190 | 392 | //printf("I2c_status: %x\n", (uint32_t) _regs[I2c_status]); |
paul@190 | 393 | //printf("Int_mask: %x\n", (uint32_t) _regs[Int_mask]); |
paul@190 | 394 | //printf("Int_status: %x\n", (uint32_t) _regs[Int_status]); |
paul@190 | 395 | printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); |
paul@190 | 396 | } |
paul@190 | 397 | |
paul@190 | 398 | |
paul@190 | 399 | |
paul@190 | 400 | // Reset interrupt flags upon certain conditions. |
paul@190 | 401 | |
paul@190 | 402 | void |
paul@190 | 403 | I2c_x1600_channel::reset_flags() |
paul@190 | 404 | { |
paul@190 | 405 | volatile uint32_t r; |
paul@190 | 406 | |
paul@190 | 407 | _regs[Int_mask] = 0; |
paul@190 | 408 | |
paul@190 | 409 | // Read from the register to clear interrupts. |
paul@190 | 410 | |
paul@190 | 411 | r = _regs[Int_combined_clear]; |
paul@190 | 412 | (void) r; |
paul@190 | 413 | } |
paul@190 | 414 | |
paul@190 | 415 | // Initialise interrupt flags and queue thresholds for reading and writing. |
paul@190 | 416 | |
paul@190 | 417 | void |
paul@190 | 418 | I2c_x1600_channel::init_parameters() |
paul@190 | 419 | { |
paul@190 | 420 | // Handle read queue conditions for data, write queue conditions for commands. |
paul@190 | 421 | |
paul@190 | 422 | reset_flags(); |
paul@190 | 423 | |
paul@190 | 424 | _regs[Tx_fifo_thold] = 0; // write when 0 in queue |
paul@190 | 425 | } |
paul@190 | 426 | |
paul@190 | 427 | |
paul@190 | 428 | |
paul@190 | 429 | // Return whether the device is active. |
paul@190 | 430 | |
paul@190 | 431 | int |
paul@190 | 432 | I2c_x1600_channel::active() |
paul@190 | 433 | { |
paul@190 | 434 | return _regs[I2c_status] & I2c_status_master_act; |
paul@190 | 435 | } |
paul@190 | 436 | |
paul@190 | 437 | // Return whether data is available to receive. |
paul@190 | 438 | |
paul@190 | 439 | int |
paul@190 | 440 | I2c_x1600_channel::have_input() |
paul@190 | 441 | { |
paul@190 | 442 | return _regs[I2c_status] & I2c_status_rx_nempty; |
paul@190 | 443 | } |
paul@190 | 444 | |
paul@190 | 445 | // Return whether data is queued for sending. |
paul@190 | 446 | |
paul@190 | 447 | int |
paul@190 | 448 | I2c_x1600_channel::have_output() |
paul@190 | 449 | { |
paul@190 | 450 | return !(_regs[I2c_status] & I2c_status_tx_empty); |
paul@190 | 451 | } |
paul@190 | 452 | |
paul@190 | 453 | // Return whether data can be queued for sending. |
paul@190 | 454 | |
paul@190 | 455 | int |
paul@190 | 456 | I2c_x1600_channel::can_send() |
paul@190 | 457 | { |
paul@190 | 458 | return _regs[I2c_status] & I2c_status_tx_nfull; |
paul@190 | 459 | } |
paul@190 | 460 | |
paul@190 | 461 | // Return whether a receive operation has failed. |
paul@190 | 462 | |
paul@190 | 463 | int |
paul@190 | 464 | I2c_x1600_channel::read_failed() |
paul@190 | 465 | { |
paul@190 | 466 | return _regs[Int_status] & Int_rx_of; |
paul@190 | 467 | } |
paul@190 | 468 | |
paul@190 | 469 | // Return whether a send operation has failed. |
paul@190 | 470 | |
paul@190 | 471 | int |
paul@190 | 472 | I2c_x1600_channel::write_failed() |
paul@190 | 473 | { |
paul@190 | 474 | return _regs[Int_status] & Int_tx_abort; |
paul@190 | 475 | } |
paul@190 | 476 | |
paul@190 | 477 | int |
paul@190 | 478 | I2c_x1600_channel::read_done() |
paul@190 | 479 | { |
paul@190 | 480 | return _pos == _total; |
paul@190 | 481 | } |
paul@190 | 482 | |
paul@190 | 483 | int |
paul@190 | 484 | I2c_x1600_channel::write_done() |
paul@190 | 485 | { |
paul@190 | 486 | return _reqpos == _total; |
paul@190 | 487 | } |
paul@190 | 488 | |
paul@190 | 489 | unsigned |
paul@190 | 490 | I2c_x1600_channel::have_read() |
paul@190 | 491 | { |
paul@190 | 492 | return _pos; |
paul@190 | 493 | } |
paul@190 | 494 | |
paul@190 | 495 | unsigned |
paul@190 | 496 | I2c_x1600_channel::have_written() |
paul@190 | 497 | { |
paul@190 | 498 | return _reqpos; |
paul@190 | 499 | } |
paul@190 | 500 | |
paul@190 | 501 | int |
paul@190 | 502 | I2c_x1600_channel::failed() |
paul@190 | 503 | { |
paul@190 | 504 | return _fail; |
paul@190 | 505 | } |
paul@190 | 506 | |
paul@190 | 507 | |
paul@190 | 508 | |
paul@190 | 509 | // Send read commands for empty queue entries. |
paul@190 | 510 | |
paul@190 | 511 | void |
paul@190 | 512 | I2c_x1600_channel::queue_reads() |
paul@190 | 513 | { |
paul@190 | 514 | unsigned int remaining = _total - _reqpos; |
paul@190 | 515 | unsigned int queued = _reqpos - _pos; |
paul@190 | 516 | unsigned int can_queue = I2c_fifo_limit - queued; |
paul@190 | 517 | |
paul@190 | 518 | // Keep the number of reads in progress below the length of the read queue. |
paul@190 | 519 | |
paul@190 | 520 | if (!can_queue) |
paul@190 | 521 | return; |
paul@190 | 522 | |
paul@190 | 523 | // At most, only queue as many reads as are remaining. |
paul@190 | 524 | |
paul@190 | 525 | if (remaining < can_queue) |
paul@190 | 526 | can_queue = remaining; |
paul@190 | 527 | |
paul@190 | 528 | // Queue read requests for any remaining queue entries. |
paul@190 | 529 | |
paul@190 | 530 | while (can_queue && can_send()) |
paul@190 | 531 | { |
paul@190 | 532 | uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; |
paul@190 | 533 | printf("Queue read %d/%d %s\n", _reqpos, _total - 1, stop ? "stop" : "continue"); |
paul@190 | 534 | |
paul@190 | 535 | _regs[I2c_data_command] = I2c_command_read | stop; |
paul@190 | 536 | _reqpos++; |
paul@190 | 537 | can_queue--; |
paul@190 | 538 | } |
paul@190 | 539 | |
paul@190 | 540 | // Update the threshold to be notified of any reduced remaining amount. |
paul@190 | 541 | |
paul@190 | 542 | set_read_threshold(); |
paul@190 | 543 | } |
paul@190 | 544 | |
paul@190 | 545 | // Send write commands for empty queue entries. |
paul@190 | 546 | |
paul@190 | 547 | void |
paul@190 | 548 | I2c_x1600_channel::queue_writes() |
paul@190 | 549 | { |
paul@190 | 550 | unsigned int remaining = _total - _reqpos; |
paul@190 | 551 | unsigned int can_queue = I2c_fifo_limit; |
paul@190 | 552 | |
paul@190 | 553 | if (remaining < can_queue) |
paul@190 | 554 | can_queue = remaining; |
paul@190 | 555 | |
paul@190 | 556 | printf("queue_writes: %d %s\n", can_queue, can_send() ? "can send" : "cannot send"); |
paul@190 | 557 | |
paul@190 | 558 | // Queue write requests for any remaining queue entries. |
paul@190 | 559 | |
paul@190 | 560 | while (can_queue && can_send()) |
paul@190 | 561 | { |
paul@190 | 562 | uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; |
paul@190 | 563 | printf("Queue write %d/%d %s\n", _reqpos, _total - 1, stop ? "stop" : "continue"); |
paul@190 | 564 | |
paul@190 | 565 | _regs[I2c_data_command] = I2c_command_write | _buf[_reqpos] | stop; |
paul@190 | 566 | _reqpos++; |
paul@190 | 567 | can_queue--; |
paul@190 | 568 | } |
paul@190 | 569 | |
paul@190 | 570 | printf("Tx_fifo_count = %d\n", (uint32_t) _regs[Tx_fifo_count]); |
paul@190 | 571 | } |
paul@190 | 572 | |
paul@190 | 573 | // Store read command results from the queue. |
paul@190 | 574 | |
paul@190 | 575 | void |
paul@190 | 576 | I2c_x1600_channel::store_reads() |
paul@190 | 577 | { |
paul@190 | 578 | printf("store_reads: %s\n", have_input() ? "input" : "no input"); |
paul@190 | 579 | |
paul@190 | 580 | // Read any input and store it in the buffer. |
paul@190 | 581 | |
paul@190 | 582 | while (have_input() && (_pos < _reqpos)) |
paul@190 | 583 | { |
paul@190 | 584 | _buf[_pos] = _regs[I2c_data_command] & 0xff; |
paul@190 | 585 | _pos++; |
paul@190 | 586 | } |
paul@190 | 587 | } |
paul@190 | 588 | |
paul@190 | 589 | void |
paul@190 | 590 | I2c_x1600_channel::set_read_threshold() |
paul@190 | 591 | { |
paul@190 | 592 | unsigned int queued = _reqpos - _pos; |
paul@190 | 593 | |
paul@190 | 594 | if (!queued) |
paul@190 | 595 | return; |
paul@190 | 596 | |
paul@190 | 597 | // Read all expected. |
paul@190 | 598 | |
paul@190 | 599 | _regs[Rx_fifo_thold] = queued - 1; |
paul@190 | 600 | printf("Rx_fifo_thold = %d\n", (uint32_t) _regs[Rx_fifo_thold]); |
paul@190 | 601 | } |
paul@190 | 602 | |
paul@190 | 603 | // Read from the target device. |
paul@190 | 604 | |
paul@190 | 605 | void |
paul@190 | 606 | I2c_x1600_channel::start_read(uint8_t buf[], unsigned int total, int stop) |
paul@190 | 607 | { |
paul@190 | 608 | _buf = buf; |
paul@190 | 609 | _total = total; |
paul@190 | 610 | _pos = 0; |
paul@190 | 611 | _reqpos = 0; |
paul@190 | 612 | _fail = 0; |
paul@190 | 613 | _stop = stop; |
paul@190 | 614 | |
paul@190 | 615 | printf("start_read: %d\n", total); |
paul@190 | 616 | |
paul@190 | 617 | _regs[Int_mask] = Int_rx_full | // read condition (reading needed) |
paul@190 | 618 | Int_rx_of | // abort condition |
paul@190 | 619 | Int_tx_abort; // abort condition |
paul@190 | 620 | |
paul@190 | 621 | // Perform initial read requests. |
paul@190 | 622 | |
paul@190 | 623 | read(); |
paul@190 | 624 | } |
paul@190 | 625 | |
paul@190 | 626 | void |
paul@190 | 627 | I2c_x1600_channel::read() |
paul@190 | 628 | { |
paul@190 | 629 | printf("Rx_fifo_count = %d\n", (uint32_t) _regs[Rx_fifo_count]); |
paul@190 | 630 | printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); |
paul@190 | 631 | printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]); |
paul@190 | 632 | |
paul@190 | 633 | if (read_failed() || write_failed()) |
paul@190 | 634 | { |
paul@190 | 635 | _fail = 1; |
paul@190 | 636 | _regs[Int_mask] = 0; |
paul@190 | 637 | return; |
paul@190 | 638 | } |
paul@190 | 639 | |
paul@190 | 640 | if (_regs[Int_status] & Int_rx_full) |
paul@190 | 641 | store_reads(); |
paul@190 | 642 | |
paul@190 | 643 | // Always attempt to queue more read requests. |
paul@190 | 644 | |
paul@190 | 645 | queue_reads(); |
paul@190 | 646 | } |
paul@190 | 647 | |
paul@190 | 648 | // Write to the target device. |
paul@190 | 649 | |
paul@190 | 650 | void |
paul@190 | 651 | I2c_x1600_channel::start_write(uint8_t buf[], unsigned int total, int stop) |
paul@190 | 652 | { |
paul@190 | 653 | _buf = buf; |
paul@190 | 654 | _total = total; |
paul@190 | 655 | _reqpos = 0; |
paul@190 | 656 | _fail = 0; |
paul@190 | 657 | _stop = stop; |
paul@190 | 658 | |
paul@190 | 659 | printf("start_write: %d\n", total); |
paul@190 | 660 | |
paul@190 | 661 | // Enable interrupts for further writes. |
paul@190 | 662 | |
paul@190 | 663 | _regs[Int_mask] = Int_tx_empty | // write condition (writing needed) |
paul@190 | 664 | Int_tx_abort; // abort condition |
paul@190 | 665 | |
paul@190 | 666 | // Perform initial writes. |
paul@190 | 667 | |
paul@190 | 668 | write(); |
paul@190 | 669 | } |
paul@190 | 670 | |
paul@190 | 671 | void |
paul@190 | 672 | I2c_x1600_channel::write() |
paul@190 | 673 | { |
paul@190 | 674 | printf("Tx_fifo_count = %d\n", (uint32_t) _regs[Tx_fifo_count]); |
paul@190 | 675 | printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); |
paul@190 | 676 | printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]); |
paul@190 | 677 | |
paul@190 | 678 | if (write_failed()) |
paul@190 | 679 | { |
paul@190 | 680 | _fail = 1; |
paul@190 | 681 | _regs[Int_mask] = 0; |
paul@190 | 682 | return; |
paul@190 | 683 | } |
paul@190 | 684 | |
paul@190 | 685 | if (_regs[Int_status] & Int_tx_empty) |
paul@190 | 686 | queue_writes(); |
paul@190 | 687 | } |
paul@190 | 688 | |
paul@190 | 689 | // Explicitly stop communication. |
paul@190 | 690 | |
paul@190 | 691 | void |
paul@190 | 692 | I2c_x1600_channel::stop() |
paul@190 | 693 | { |
paul@190 | 694 | } |
paul@190 | 695 | |
paul@190 | 696 | |
paul@190 | 697 | |
paul@190 | 698 | // Initialise the I2C controller. |
paul@190 | 699 | |
paul@190 | 700 | I2c_x1600_chip::I2c_x1600_chip(l4_addr_t start, l4_addr_t end, |
paul@190 | 701 | Cpm_x1600_chip *cpm, |
paul@190 | 702 | uint32_t frequency) |
paul@190 | 703 | : _start(start), _end(end), _cpm(cpm), _frequency(frequency) |
paul@190 | 704 | { |
paul@190 | 705 | } |
paul@190 | 706 | |
paul@190 | 707 | // Obtain a channel object. |
paul@190 | 708 | |
paul@190 | 709 | I2c_x1600_channel * |
paul@190 | 710 | I2c_x1600_chip::get_channel(uint8_t channel) |
paul@190 | 711 | { |
paul@190 | 712 | l4_addr_t block = _start + channel * I2c_block_offset; |
paul@190 | 713 | enum Clock_identifiers bits[] = {Clock_i2c0, Clock_i2c1}; |
paul@190 | 714 | |
paul@190 | 715 | if (channel < 2) |
paul@190 | 716 | { |
paul@190 | 717 | _cpm->start_clock(bits[channel]); |
paul@190 | 718 | return new I2c_x1600_channel(block, _cpm, _frequency); |
paul@190 | 719 | } |
paul@190 | 720 | else |
paul@190 | 721 | throw -L4_EINVAL; |
paul@190 | 722 | } |
paul@190 | 723 | |
paul@190 | 724 | |
paul@190 | 725 | |
paul@190 | 726 | // C language interface functions. |
paul@190 | 727 | |
paul@190 | 728 | void *x1600_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) |
paul@190 | 729 | { |
paul@190 | 730 | return (void *) new I2c_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm), frequency); |
paul@190 | 731 | } |
paul@190 | 732 | |
paul@190 | 733 | void x1600_i2c_disable(void *i2c_channel) |
paul@190 | 734 | { |
paul@190 | 735 | static_cast<I2c_x1600_channel *>(i2c_channel)->disable(); |
paul@190 | 736 | } |
paul@190 | 737 | |
paul@190 | 738 | void *x1600_i2c_get_channel(void *i2c, uint8_t channel) |
paul@190 | 739 | { |
paul@190 | 740 | return static_cast<I2c_x1600_chip *>(i2c)->get_channel(channel); |
paul@190 | 741 | } |
paul@190 | 742 | |
paul@190 | 743 | uint32_t x1600_i2c_get_frequency(void *i2c_channel) |
paul@190 | 744 | { |
paul@190 | 745 | return static_cast<I2c_x1600_channel *>(i2c_channel)->get_frequency(); |
paul@190 | 746 | } |
paul@190 | 747 | |
paul@190 | 748 | void x1600_i2c_set_target(void *i2c_channel, uint8_t addr) |
paul@190 | 749 | { |
paul@190 | 750 | static_cast<I2c_x1600_channel *>(i2c_channel)->set_target(addr); |
paul@190 | 751 | } |
paul@190 | 752 | |
paul@190 | 753 | void x1600_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned int total, |
paul@190 | 754 | int stop) |
paul@190 | 755 | { |
paul@190 | 756 | static_cast<I2c_x1600_channel *>(i2c_channel)->start_read(buf, total, stop); |
paul@190 | 757 | } |
paul@190 | 758 | |
paul@190 | 759 | void x1600_i2c_read(void *i2c_channel) |
paul@190 | 760 | { |
paul@190 | 761 | static_cast<I2c_x1600_channel *>(i2c_channel)->read(); |
paul@190 | 762 | } |
paul@190 | 763 | |
paul@190 | 764 | void x1600_i2c_start_write(void *i2c_channel, uint8_t buf[], unsigned int total, |
paul@190 | 765 | int stop) |
paul@190 | 766 | { |
paul@190 | 767 | static_cast<I2c_x1600_channel *>(i2c_channel)->start_write(buf, total, stop); |
paul@190 | 768 | } |
paul@190 | 769 | |
paul@190 | 770 | void x1600_i2c_write(void *i2c_channel) |
paul@190 | 771 | { |
paul@190 | 772 | static_cast<I2c_x1600_channel *>(i2c_channel)->write(); |
paul@190 | 773 | } |
paul@190 | 774 | |
paul@190 | 775 | int x1600_i2c_read_done(void *i2c_channel) |
paul@190 | 776 | { |
paul@190 | 777 | return static_cast<I2c_x1600_channel *>(i2c_channel)->read_done(); |
paul@190 | 778 | } |
paul@190 | 779 | |
paul@190 | 780 | int x1600_i2c_write_done(void *i2c_channel) |
paul@190 | 781 | { |
paul@190 | 782 | return static_cast<I2c_x1600_channel *>(i2c_channel)->write_done(); |
paul@190 | 783 | } |
paul@190 | 784 | |
paul@190 | 785 | unsigned int x1600_i2c_have_read(void *i2c_channel) |
paul@190 | 786 | { |
paul@190 | 787 | return static_cast<I2c_x1600_channel *>(i2c_channel)->have_read(); |
paul@190 | 788 | } |
paul@190 | 789 | |
paul@190 | 790 | unsigned int x1600_i2c_have_written(void *i2c_channel) |
paul@190 | 791 | { |
paul@190 | 792 | return static_cast<I2c_x1600_channel *>(i2c_channel)->have_written(); |
paul@190 | 793 | } |
paul@190 | 794 | |
paul@190 | 795 | int x1600_i2c_failed(void *i2c_channel) |
paul@190 | 796 | { |
paul@190 | 797 | return static_cast<I2c_x1600_channel *>(i2c_channel)->failed(); |
paul@190 | 798 | } |
paul@190 | 799 | |
paul@190 | 800 | void x1600_i2c_stop(void *i2c_channel) |
paul@190 | 801 | { |
paul@190 | 802 | static_cast<I2c_x1600_channel *>(i2c_channel)->stop(); |
paul@190 | 803 | } |