Landfall

Annotated pkg/devices/include/clocks.h

255:fcc601d70467
8 months ago Paul Boddie Fixed transfer result value for asynchronous transfers. Reformatted comments. cpm-library-improvements
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/*
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 * Clock identifiers for clock and power management.
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 *
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 * Copyright (C) 2021, 2023 Paul Boddie <paul@boddie.org.uk>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
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 * Boston, MA  02110-1301, USA
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 */
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#pragma once
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/* Identifiers for controllable "logical" or "abstract" clocks. Operations
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   involving these clocks may operate on multiple "physical" or "specific"
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   clocks. */
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enum Clock_identifiers
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{
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  Clock_none,             /* not a clock: special value */
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  Clock_aic,
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  Clock_aic_bitclk,
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  Clock_aic_pclk,
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  Clock_can0,
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  Clock_can1,
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  Clock_cdbus,
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  Clock_cim,
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  Clock_cpu,
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  Clock_ddr,
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  Clock_dma,
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  Clock_emac,
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  Clock_external,         /* EXCLK */
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  Clock_external_div_512,
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  Clock_hclock0,          /* AHB0 */
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  Clock_hclock2,          /* AHB2 */
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  Clock_hclock2_pclock,   /* AHB2, APB parent clock (JZ4780, X1600) */
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  Clock_hdmi,
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  Clock_i2c0,
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  Clock_i2c1,
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  Clock_i2c2,
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  Clock_i2c3,
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  Clock_i2c4,
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  Clock_i2s0,
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  Clock_i2s0_rx,
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  Clock_i2s0_tx,
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  Clock_i2s1,
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  Clock_i2s1_rx,
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  Clock_i2s1_tx,
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  Clock_kbc,
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  Clock_l2cache,
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  Clock_lcd,              /* LCD peripheral clock */
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  Clock_lcd_pixel0,
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  Clock_lcd_pixel1,
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  Clock_mac,
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  Clock_main,             /* SCLK_A */
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  Clock_mipi_csi,
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  Clock_msc,              /* MSC parent clock (JZ4780) */
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  Clock_msc0,
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  Clock_msc1,
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  Clock_msc2,
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  Clock_nemc,
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  Clock_otg0,
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  Clock_otg1,
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  Clock_pclock,           /* APB */
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  Clock_pcm,
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  Clock_pll_A,
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  Clock_pll_E,
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  Clock_pll_M,
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  Clock_pll_V,
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  Clock_pwm0,
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  Clock_pwm1,
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  Clock_rtc,              /* RTC parent clock */
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  Clock_rtc_external,     /* RTCLK */
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  Clock_sadc,
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  Clock_scc,
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  Clock_sfc,
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  Clock_ssi,              /* SSI parent clock (JZ4780) */
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  Clock_ssi0,
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  Clock_ssi1,
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  Clock_ssi2,
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  Clock_timer,
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  Clock_uart0,
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  Clock_uart1,
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  Clock_uart2,
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  Clock_uart3,
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  Clock_uart4,
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  Clock_udc,
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  Clock_uhc,
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  Clock_uprt,
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  Clock_usb_phy,
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  Clock_vpu,
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  Clock_specific_start,   /* not a clock: start of chip-specific clocks */
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};
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