1.1 --- a/pkg/devices/lib/hdmi/src/jz4780.cc Sat May 23 22:34:17 2020 +0200
1.2 +++ b/pkg/devices/lib/hdmi/src/jz4780.cc Mon Jun 01 15:37:38 2020 +0200
1.3 @@ -3,6 +3,13 @@
1.4 *
1.5 * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk>
1.6 *
1.7 + * Techniques and operations introduced from the Linux DRM bridge driver for
1.8 + * Synopsys DW-HDMI whose authors are as follows:
1.9 + *
1.10 + * Copyright (C) 2013-2015 Mentor Graphics Inc.
1.11 + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
1.12 + * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
1.13 + *
1.14 * This program is free software; you can redistribute it and/or
1.15 * modify it under the terms of the GNU General Public License as
1.16 * published by the Free Software Foundation; either version 2 of
1.17 @@ -17,10 +24,31 @@
1.18 * along with this program; if not, write to the Free Software
1.19 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.20 * Boston, MA 02110-1301, USA
1.21 + *
1.22 + * ----
1.23 + *
1.24 + * Some acronyms:
1.25 + *
1.26 + * CEC (Consumer Electronics Control) is a HDMI device control interface for up
1.27 + * to 15 devices.
1.28 + *
1.29 + * CSC (Colour Space Conversion) is the processing needed to convert from one
1.30 + * representation of colours to another.
1.31 + *
1.32 + * HEAC (HDMI Ethernet and Audio Return Channel) is a combination of HEC (HDMI
1.33 + * Ethernet Channel) which provides a 100Mb/s bidirectional link and ARC (Audio
1.34 + * Return Channel) which permits the consumption of audio data from the device.
1.35 + *
1.36 + * MHL (Mobile High-Definition Link) is an adaptation of HDMI for mobile
1.37 + * devices.
1.38 + *
1.39 + * TMDS (Transition-Minimized Differential Signaling) is the method by which
1.40 + * audio, control and video data are all sent to the device.
1.41 */
1.42
1.43 #include <l4/devices/hdmi-jz4780.h>
1.44 #include <l4/devices/hw_mmio_register_block.h>
1.45 +#include <l4/devices/lcd-jz4740-config.h>
1.46
1.47 #include <l4/sys/irq.h>
1.48 #include <l4/util/util.h>
1.49 @@ -39,74 +67,150 @@
1.50 {
1.51 // Identification.
1.52
1.53 - Design_id = 0x000, // DESIGN_ID
1.54 - Revision_id = 0x001, // REVISION_ID
1.55 - Product_id0 = 0x002, // PRODUCT_ID0
1.56 - Product_id1 = 0x003, // PRODUCT_ID1
1.57 - Config_id0 = 0x004, // CONFIG_ID0
1.58 - Config_id1 = 0x005, // CONFIG_ID1
1.59 - Config_id2 = 0x006, // CONFIG_ID2
1.60 - Config_id3 = 0x007, // CONFIG_ID3
1.61 + Design_id = 0x000, // DESIGN_ID
1.62 + Revision_id = 0x001, // REVISION_ID
1.63 + Product_id0 = 0x002, // PRODUCT_ID0
1.64 + Product_id1 = 0x003, // PRODUCT_ID1
1.65 + Config_id0 = 0x004, // CONFIG_ID0
1.66 + Config_id1 = 0x005, // CONFIG_ID1
1.67 + Config_id2 = 0x006, // CONFIG_ID2
1.68 + Config_id3 = 0x007, // CONFIG_ID3
1.69
1.70 // Top-level interrupt control.
1.71
1.72 - Int_mask = 0x1ff, // MUTE
1.73 + Int_mask = 0x1ff, // MUTE
1.74
1.75 // Interrupt status and mask for various functions.
1.76
1.77 - Fc_int_status0 = 0x100, // FC_STAT0
1.78 - Fc_int_status1 = 0x101, // FC_STAT1
1.79 - Fc_int_status2 = 0x102, // FC_STAT2
1.80 - As_int_status = 0x103, // AS_STAT0
1.81 - Phy_int_status = 0x104, // PHY_STAT0
1.82 - Cec_int_status = 0x106, // CEC_STAT0
1.83 - Vp_int_status = 0x107, // VP_STAT0
1.84 - Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0
1.85 + Fc_int_status0 = 0x100, // FC_STAT0
1.86 + Fc_int_status1 = 0x101, // FC_STAT1
1.87 + Fc_int_status2 = 0x102, // FC_STAT2
1.88 + As_int_status = 0x103, // AS_STAT0
1.89 + Phy_int_status = 0x104, // PHY_STAT0
1.90 + Cec_int_status = 0x106, // CEC_STAT0
1.91 + Vp_int_status = 0x107, // VP_STAT0
1.92 + Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0
1.93
1.94 - Fc_int_mask0 = 0x180, // MUTE_FC_STAT0
1.95 - Fc_int_mask1 = 0x181, // MUTE_FC_STAT1
1.96 - Fc_int_mask2 = 0x182, // MUTE_FC_STAT2
1.97 - As_int_mask = 0x183, // MUTE_AS_STAT0
1.98 - Phy_int_mask = 0x184, // MUTE_PHY_STAT0
1.99 - Cec_int_mask = 0x186, // MUTE_CEC_STAT0
1.100 - Vp_int_mask = 0x187, // MUTE_VP_STAT0
1.101 - Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0
1.102 + Fc_int_mask0 = 0x180, // MUTE_FC_STAT0
1.103 + Fc_int_mask1 = 0x181, // MUTE_FC_STAT1
1.104 + Fc_int_mask2 = 0x182, // MUTE_FC_STAT2
1.105 + As_int_mask = 0x183, // MUTE_AS_STAT0
1.106 + Phy_int_mask = 0x184, // MUTE_PHY_STAT0
1.107 + Cec_int_mask = 0x186, // MUTE_CEC_STAT0
1.108 + Vp_int_mask = 0x187, // MUTE_VP_STAT0
1.109 + Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0
1.110
1.111 // I2C for E-DDC.
1.112
1.113 - I2c_int_status = 0x105, // I2CM_STAT0
1.114 - I2c_int_mask = 0x185, // MUTE_I2CM_STAT0
1.115 + I2c_int_status = 0x105, // I2CM_STAT0
1.116 + I2c_int_mask = 0x185, // MUTE_I2CM_STAT0
1.117
1.118 - I2c_device_address = 0x7e00, // I2CM_SLAVE
1.119 - I2c_register = 0x7e01, // I2CM_ADDRESS
1.120 - I2c_data_out = 0x7e02, // I2CM_DATAO
1.121 - I2c_data_in = 0x7e03, // I2CM_DATAI
1.122 - I2c_operation = 0x7e04, // I2CM_OPERATION
1.123 - I2c_int_config0 = 0x7e05, // I2CM_INT
1.124 - I2c_int_config1 = 0x7e06, // I2CM_CTLINT
1.125 - I2c_divider = 0x7e07, // I2CM_DIV
1.126 - I2c_segment_address = 0x7e08, // I2CM_SEGADDR
1.127 - I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ
1.128 - I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR
1.129 + I2c_device_address = 0x7e00, // I2CM_SLAVE
1.130 + I2c_register = 0x7e01, // I2CM_ADDRESS
1.131 + I2c_data_out = 0x7e02, // I2CM_DATAO
1.132 + I2c_data_in = 0x7e03, // I2CM_DATAI
1.133 + I2c_operation = 0x7e04, // I2CM_OPERATION
1.134 + I2c_int_config0 = 0x7e05, // I2CM_INT
1.135 + I2c_int_config1 = 0x7e06, // I2CM_CTLINT
1.136 + I2c_divider = 0x7e07, // I2CM_DIV
1.137 + I2c_segment_address = 0x7e08, // I2CM_SEGADDR
1.138 + I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ
1.139 + I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR
1.140
1.141 // I2C for PHY.
1.142
1.143 - I2c_phy_int_status = 0x108, // I2CMPHY_STAT0
1.144 - I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0
1.145 + I2c_phy_int_status = 0x108, // I2CMPHY_STAT0
1.146 + I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0
1.147
1.148 - I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR
1.149 - I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR
1.150 + I2c_phy_device_address = 0x3020, // PHY_I2CM_SLAVE_ADDR
1.151 + I2c_phy_register = 0x3021, // PHY_I2CM_ADDRESS_ADDR
1.152 + I2c_phy_data_out1 = 0x3022, // PHY_I2CM_DATAO_1_ADDR
1.153 + I2c_phy_data_out0 = 0x3023, // PHY_I2CM_DATAO_0_ADDR
1.154 + I2c_phy_data_in1 = 0x3024, // PHY_I2CM_DATAI_1_ADDR
1.155 + I2c_phy_data_in0 = 0x3025, // PHY_I2CM_DATAI_0_ADDR
1.156 + I2c_phy_operation = 0x3026, // PHY_I2CM_OPERATION_ADDR
1.157 + I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR
1.158 + I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR
1.159 + I2c_phy_divider = 0x3029, // PHY_I2CM_DIV_ADDR
1.160 + I2c_phy_software_reset = 0x302a, // PHY_I2CM_SOFTRSTZ_ADDR
1.161
1.162 // PHY registers.
1.163
1.164 - Phy_config = 0x3000, // PHY_CONF0
1.165 - Phy_test0 = 0x3001, // PHY_TST0
1.166 - Phy_test1 = 0x3002, // PHY_TST1
1.167 - Phy_test2 = 0x3003, // PHY_TST2
1.168 - Phy_status = 0x3004, // PHY_STAT0
1.169 - Phy_int_config = 0x3005, // PHY_INT0
1.170 - Phy_mask = 0x3006, // PHY_MASK0
1.171 - Phy_polarity = 0x3007, // PHY_POL0
1.172 + Phy_config = 0x3000, // PHY_CONF0
1.173 + Phy_test0 = 0x3001, // PHY_TST0
1.174 + Phy_test1 = 0x3002, // PHY_TST1
1.175 + Phy_test2 = 0x3003, // PHY_TST2
1.176 + Phy_status = 0x3004, // PHY_STAT0
1.177 + Phy_int_config = 0x3005, // PHY_INT0
1.178 + Phy_mask = 0x3006, // PHY_MASK0
1.179 + Phy_polarity = 0x3007, // PHY_POL0
1.180 +
1.181 + // Main controller registers.
1.182 +
1.183 + Main_clock_disable = 0x4001, // MC_CLKDIS
1.184 + Main_software_reset = 0x4002, // MC_SWRSTZ
1.185 + Main_flow_control = 0x4004, // MC_FLOWCTRL
1.186 + Main_reset = 0x4005, // MC_PHYRSTZ
1.187 + Main_heac_phy_reset = 0x4007, // MC_HEACPHY_RST
1.188 +
1.189 + // Frame composer registers for input video.
1.190 +
1.191 + Fc_video_config = 0x1000, // FC_INVIDCONF
1.192 + Fc_horizontal_active_width0 = 0x1001, // FC_INHACTV0
1.193 + Fc_horizontal_active_width1 = 0x1002, // FC_INHACTV1
1.194 + Fc_horizontal_blank_width0 = 0x1003, // FC_INHBLANK0
1.195 + Fc_horizontal_blank_width1 = 0x1004, // FC_INHBLANK1
1.196 + Fc_vertical_active_height0 = 0x1005, // FC_INVACTV0
1.197 + Fc_vertical_active_height1 = 0x1006, // FC_INVACTV1
1.198 + Fc_vertical_blank_height = 0x1007, // FC_INVBLANK
1.199 +
1.200 + // Frame composer registers for sync pulses.
1.201 +
1.202 + Fc_hsync_delay0 = 0x1008, // FC_HSYNCINDELAY0
1.203 + Fc_hsync_delay1 = 0x1009, // FC_HSYNCINDELAY1
1.204 + Fc_hsync_width0 = 0x100A, // FC_HSYNCINWIDTH0
1.205 + Fc_hsync_width1 = 0x100B, // FC_HSYNCINWIDTH1
1.206 + Fc_vsync_delay = 0x100C, // FC_VSYNCINDELAY
1.207 + Fc_vsync_height = 0x100D, // FC_VSYNCINWIDTH
1.208 +
1.209 + // Frame composer registers for video path configuration.
1.210 +
1.211 + Fc_control_duration = 0x1011, // FC_CTRLDUR
1.212 + Fc_ex_control_duration = 0x1012, // FC_EXCTRLDUR
1.213 + Fc_ex_control_space = 0x1013, // FC_EXCTRLSPAC
1.214 + Fc_channel0_preamble = 0x1014, // FC_CH0PREAM
1.215 + Fc_channel1_preamble = 0x1015, // FC_CH1PREAM
1.216 + Fc_channel2_preamble = 0x1016, // FC_CH2PREAM
1.217 +
1.218 + // Colour space conversion registers.
1.219 +
1.220 + Csc_config = 0x4100, // CSC_CFG
1.221 + Csc_scale = 0x4101, // CSC_SCALE
1.222 +
1.223 + // HDCP registers.
1.224 +
1.225 + Hdcp_config0 = 0x5000, // A_HDCPCFG0
1.226 + Hdcp_config1 = 0x5001, // A_HDCPCFG1
1.227 + Hdcp_video_polarity = 0x5009, // A_VIDPOLCFG
1.228 +
1.229 + // Video sample registers.
1.230 +
1.231 + Sample_video_config = 0x0200, // TX_INVID0
1.232 + Sample_video_stuffing = 0x0201, // TX_INSTUFFING
1.233 + Sample_gy_data0 = 0x0202, // TX_GYDATA0
1.234 + Sample_gy_data1 = 0x0203, // TX_GYDATA1
1.235 + Sample_rcr_data0 = 0x0204, // TX_RCRDATA0
1.236 + Sample_rcr_data1 = 0x0205, // TX_RCRDATA1
1.237 + Sample_bcb_data0 = 0x0206, // TX_BCBDATA0
1.238 + Sample_bcb_data1 = 0x0207, // TX_BCBDATA1
1.239 +
1.240 + // Video packetizer registers.
1.241 +
1.242 + Packet_status = 0x0800, // VP_STATUS
1.243 + Packet_pixel_repeater = 0x0801, // VP_PR_CD
1.244 + Packet_stuffing = 0x0802, // VP_STUFF
1.245 + Packet_remap = 0x0803, // VP_REMAP
1.246 + Packet_config = 0x0804, // VP_CONF
1.247 };
1.248
1.249 // Identification values.
1.250 @@ -149,6 +253,8 @@
1.251 Int_mask_all = 0x01,
1.252 };
1.253
1.254 +// I2C status and mask bits, also for PHY I2C.
1.255 +
1.256 enum I2c_int_status_bits : unsigned
1.257 {
1.258 I2c_int_status_done = 0x02,
1.259 @@ -160,38 +266,73 @@
1.260 enum I2c_operation_bits : unsigned
1.261 {
1.262 I2c_operation_write = 0x10,
1.263 - I2c_operation_segment_read = 0x02,
1.264 + I2c_operation_segment_read = 0x02, // not PHY I2C
1.265 I2c_operation_read = 0x01,
1.266 };
1.267
1.268 -// Interrupt configuration bits.
1.269 +// Device addresses.
1.270 +
1.271 +enum I2c_phy_device_addresses : unsigned
1.272 +{
1.273 + I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2
1.274 + I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY
1.275 +};
1.276 +
1.277 +// Device registers.
1.278 +
1.279 +enum I2c_phy_device_registers : unsigned
1.280 +{
1.281 + I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL
1.282 + I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL
1.283 + I2c_phy_3d_tx_clock_symbol_ctrl = 0x09, // 3D_TX_PHY_CKSYMTXCTRL
1.284 + I2c_phy_3d_tx_vlevel_ctrl = 0x0e, // 3D_TX_PHY_VLEVCTRL
1.285 + I2c_phy_3d_tx_curr_ctrl = 0x10, // 3D_TX_PHY_CURRCTRL
1.286 + I2c_phy_3d_tx_pll_phby_ctrl = 0x13, // 3D_TX_PHY_PLLPHBYCTRL
1.287 + I2c_phy_3d_tx_gmp_ctrl = 0x15, // 3D_TX_PHY_GMPCTRL
1.288 + I2c_phy_3d_tx_msm_ctrl = 0x17, // 3D_TX_PHY_MSM_CTRL
1.289 + I2c_phy_3d_tx_term = 0x19, // 3D_TX_PHY_TXTERM
1.290 +};
1.291 +
1.292 +// PHY I2C register values.
1.293 +
1.294 +enum Msm_ctrl_bits : unsigned
1.295 +{
1.296 + Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK
1.297 +};
1.298 +
1.299 +enum Clock_cal_ctrl_bits : unsigned
1.300 +{
1.301 + Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE
1.302 +};
1.303 +
1.304 +// Interrupt configuration bits, also for PHY I2C.
1.305
1.306 enum I2c_int_config0_bits : unsigned
1.307 {
1.308 - I2c_int_config0_done_polarity = 0x08,
1.309 - I2c_int_config0_done_mask = 0x04,
1.310 + I2c_int_config0_done_polarity = 0x08,
1.311 + I2c_int_config0_done_mask = 0x04,
1.312 };
1.313
1.314 enum I2c_int_config1_bits : unsigned
1.315 {
1.316 - I2c_int_config1_nack_polarity = 0x80,
1.317 - I2c_int_config1_nack_mask = 0x40,
1.318 - I2c_int_config1_arb_polarity = 0x08,
1.319 - I2c_int_config1_arb_mask = 0x04,
1.320 + I2c_int_config1_nack_polarity = 0x80,
1.321 + I2c_int_config1_nack_mask = 0x40,
1.322 + I2c_int_config1_arb_polarity = 0x08,
1.323 + I2c_int_config1_arb_mask = 0x04,
1.324 };
1.325
1.326 // PHY configuration values.
1.327
1.328 enum Phy_config_bits : unsigned
1.329 {
1.330 - Phy_config_pdz_mask = 0x80, // PHY_CONF0_PDZ_MASK
1.331 - Phy_config_enable_tmds_mask = 0x40, // PHY_CONF0_ENTMDS_MASK
1.332 - Phy_config_svsret_mask = 0x20, // PHY_CONF0_SVSRET_MASK
1.333 - Phy_config_gen2_pddq_mask = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK
1.334 - Phy_config_gen2_tx_power_on_mask = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK
1.335 - Phy_config_gen2_enable_hotplug_detect_rx_sense_mask = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK
1.336 - Phy_config_select_data_enable_polarity_mask = 0x02, // PHY_CONF0_SELDATAENPOL_MASK
1.337 - Phy_config_select_interface_control_mask = 0x01, // PHY_CONF0_SELDIPIF_MASK
1.338 + Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK
1.339 + Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK
1.340 + Phy_config_svsret = 0x20, // PHY_CONF0_SVSRET_MASK
1.341 + Phy_config_gen2_powerdown = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK
1.342 + Phy_config_gen2_tx_power = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK
1.343 + Phy_config_gen2_hotplug_detect_rx_sense = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK
1.344 + Phy_config_select_data_enable_polarity = 0x02, // PHY_CONF0_SELDATAENPOL_MASK
1.345 + Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK
1.346 };
1.347
1.348 enum Phy_test_bits : unsigned
1.349 @@ -205,6 +346,7 @@
1.350
1.351 enum Phy_status_bits : unsigned
1.352 {
1.353 + Phy_status_all = 0xf3,
1.354 Phy_status_rx_sense_all = 0xf0,
1.355 Phy_status_rx_sense3 = 0x80, // PHY_RX_SENSE3
1.356 Phy_status_rx_sense2 = 0x40, // PHY_RX_SENSE2
1.357 @@ -212,12 +354,14 @@
1.358 Phy_status_rx_sense0 = 0x10, // PHY_RX_SENSE0
1.359 Phy_status_hotplug_detect = 0x02, // PHY_HPD
1.360 Phy_status_tx_phy_lock = 0x01, // PHY_TX_PHY_LOCK
1.361 + Phy_status_none = 0,
1.362 };
1.363
1.364 -// PHY interrupt status and mask bits.
1.365 +// PHY interrupt status and mask values.
1.366
1.367 enum Phy_int_status_bits : unsigned
1.368 {
1.369 + Phy_int_status_all = 0x3f,
1.370 Phy_int_status_rx_sense_all = 0x3c,
1.371 Phy_int_status_rx_sense3 = 0x20, // IH_PHY_STAT0_RX_SENSE3
1.372 Phy_int_status_rx_sense2 = 0x10, // IH_PHY_STAT0_RX_SENSE2
1.373 @@ -225,6 +369,202 @@
1.374 Phy_int_status_rx_sense0 = 0x04, // IH_PHY_STAT0_RX_SENSE0
1.375 Phy_int_status_tx_phy_lock = 0x02, // IH_PHY_STAT0_TX_PHY_LOCK
1.376 Phy_int_status_hotplug_detect = 0x01, // IH_PHY_STAT0_HPD
1.377 + Phy_int_status_none = 0,
1.378 +};
1.379 +
1.380 +// PHY main register values.
1.381 +
1.382 +enum Main_heac_phy_reset_bits : unsigned
1.383 +{
1.384 + Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT
1.385 +};
1.386 +
1.387 +enum Main_flow_control_bits : unsigned
1.388 +{
1.389 + Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH
1.390 + Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS
1.391 +};
1.392 +
1.393 +enum Main_clock_disable_bits : unsigned
1.394 +{
1.395 + Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE
1.396 + Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE
1.397 + Main_clock_disable_csc = 0x10, // MC_CLKDIS_CSCCLK_DISABLE
1.398 + Main_clock_disable_audio = 0x08, // MC_CLKDIS_AUDCLK_DISABLE
1.399 + Main_clock_disable_prep = 0x04, // MC_CLKDIS_PREPCLK_DISABLE
1.400 + Main_clock_disable_tmds = 0x02, // MC_CLKDIS_TMDSCLK_DISABLE
1.401 + Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE
1.402 +};
1.403 +
1.404 +// Frame composer values.
1.405 +
1.406 +enum Fc_video_config_bits : unsigned
1.407 +{
1.408 + Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE
1.409 + Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE
1.410 + Fc_video_config_vsync_active_high = 0x40, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH
1.411 + Fc_video_config_vsync_active_low = 0x00, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW
1.412 + Fc_video_config_hsync_active_high = 0x20, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH
1.413 + Fc_video_config_hsync_active_low = 0x00, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW
1.414 + Fc_video_config_data_enable_active_high = 0x10, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH
1.415 + Fc_video_config_data_enable_active_low = 0x00, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW
1.416 + Fc_video_config_hdmi_mode = 0x08, // FC_INVIDCONF_DVI_MODEZ_HDMI_MODE
1.417 + Fc_video_config_dvi_mode = 0x00, // FC_INVIDCONF_DVI_MODEZ_DVI_MODE
1.418 + Fc_video_config_osc_active_high = 0x02, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH
1.419 + Fc_video_config_osc_active_low = 0x00, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW
1.420 + Fc_video_config_interlaced = 0x01, // FC_INVIDCONF_IN_I_P_INTERLACED
1.421 + Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE
1.422 +};
1.423 +
1.424 +enum Fc_int_status2_bits : unsigned
1.425 +{
1.426 + Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK
1.427 + Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW
1.428 + Fc_int_status2_overflow_high = 0x01 // FC_STAT2_HIGH_PRIORITY_OVERFLOW,
1.429 +};
1.430 +
1.431 +// Colour space conversion values.
1.432 +
1.433 +enum Csc_config_bits : unsigned
1.434 +{
1.435 + Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK
1.436 + Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE
1.437 + Csc_config_interpolation_form1 = 0x10, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA1
1.438 + Csc_config_interpolation_form2 = 0x20, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA2
1.439 + Csc_config_decimation_mask = 0x3, // CSC_CFG_DECMODE_MASK
1.440 + Csc_config_decimation_disable = 0x0, // CSC_CFG_DECMODE_DISABLE
1.441 + Csc_config_decimation_form1 = 0x1, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA1
1.442 + Csc_config_decimation_form2 = 0x2, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA2
1.443 + Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3
1.444 +};
1.445 +
1.446 +enum Csc_scale_bits : unsigned
1.447 +{
1.448 + Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK
1.449 + Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP
1.450 + Csc_scale_colour_depth_30bpp = 0x50, // CSC_SCALE_CSC_COLORDE_PTH_30BPP
1.451 + Csc_scale_colour_depth_36bpp = 0x60, // CSC_SCALE_CSC_COLORDE_PTH_36BPP
1.452 + Csc_scale_colour_depth_48bpp = 0x70, // CSC_SCALE_CSC_COLORDE_PTH_48BPP
1.453 + Csc_scale_mask = 0x03, // CSC_SCALE_CSCSCALE_MASK
1.454 +};
1.455 +
1.456 +// HDCP register values.
1.457 +
1.458 +enum Hdcp_config0_bits : unsigned
1.459 +{
1.460 + Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE
1.461 +};
1.462 +
1.463 +enum Hdcp_config1_bits : unsigned
1.464 +{
1.465 + Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE
1.466 +};
1.467 +
1.468 +enum Hdcp_video_polarity_bits : unsigned
1.469 +{
1.470 + Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH
1.471 +};
1.472 +
1.473 +// Video sample register values.
1.474 +
1.475 +enum Sample_video_config_bits : unsigned
1.476 +{
1.477 + Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE
1.478 + Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK
1.479 +};
1.480 +
1.481 +enum Sample_video_stuffing_bits : unsigned
1.482 +{
1.483 + Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE
1.484 + Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE
1.485 + Sample_video_stuffing_gy_data = 0x01, // TX_INSTUFFING_GYDATA_STUFFING_ENABLE
1.486 +};
1.487 +
1.488 +// Video packetizer register values.
1.489 +
1.490 +enum Packet_stuffing_bits : unsigned
1.491 +{
1.492 + Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK
1.493 + Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK
1.494 + Packet_stuffing_icx = 0x08, // VP_STUFF_ICX_GOTO_P0_ST_MASK
1.495 + Packet_stuffing_ycc422 = 0x04, // VP_STUFF_YCC422_STUFFING_STUFFING_MODE
1.496 + Packet_stuffing_pp = 0x02, // VP_STUFF_PP_STUFFING_STUFFING_MODE
1.497 + Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE
1.498 +};
1.499 +
1.500 +enum Packet_config_bits : unsigned
1.501 +{
1.502 + Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE
1.503 + Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE
1.504 + Packet_config_pr_enable = 0x10, // VP_CONF_PR_EN_ENABLE
1.505 + Packet_config_ycc422_enable = 0x8, // VP_CONF_YCC422_EN_ENABLE
1.506 + Packet_config_bypass_select_packetizer = 0x4, // VP_CONF_BYPASS_SELECT_VID_PACKETIZER
1.507 + Packet_config_output_selector_mask = 0x3, // VP_CONF_OUTPUT_SELECTOR_MASK
1.508 + Packet_config_output_selector_bypass = 0x3, // VP_CONF_OUTPUT_SELECTOR_BYPASS
1.509 + Packet_config_output_selector_ycc422 = 0x1, // VP_CONF_OUTPUT_SELECTOR_YCC422
1.510 + Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP
1.511 +};
1.512 +
1.513 +enum Packet_remap_bits : unsigned
1.514 +{
1.515 + Packet_remap_mask = 0x3, // VP_REMAP_MASK
1.516 + Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit
1.517 + Packet_remap_ycc422_20bit = 0x1, // VP_REMAP_YCC422_20bit
1.518 + Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit
1.519 +};
1.520 +
1.521 +enum Packet_pixel_repeater_bits : unsigned
1.522 +{
1.523 + Packet_pixel_repeater_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK
1.524 + Packet_pixel_repeater_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET
1.525 + Packet_pixel_repeater_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK
1.526 + Packet_pixel_repeater_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET
1.527 +};
1.528 +
1.529 +
1.530 +
1.531 +// PHY capabilities.
1.532 +
1.533 +static const Phy_capabilities phy_capabilities[] = {
1.534 + // name gen svsret configure
1.535 + {Config2_dwc_hdmi_tx_phy, "DWC_HDMI_TX_PHY", 1, false, false},
1.536 + {Config2_dwc_mhl_phy_heac, "DWC_MHL_PHY_HEAC", 2, true, true},
1.537 + {Config2_dwc_mhl_phy, "DWC_MHL_PHY", 2, true, true},
1.538 + {Config2_dwc_hdmi_3d_tx_phy_heac, "DWC_HDMI_3D_TX_PHY_HEAC", 2, false, true},
1.539 + {Config2_dwc_hdmi_3d_tx_phy, "DWC_HDMI_3D_TX_PHY", 2, false, true},
1.540 + {Config2_dwc_hdmi20_tx_phy, "DWC_HDMI20_TX_PHY", 2, true, true},
1.541 + {0, "Vendor PHY", 0, false, false},
1.542 + };
1.543 +
1.544 +
1.545 +
1.546 +// PHY configuration, adopting the Linux driver's tables of values.
1.547 +
1.548 +static const struct Phy_mpll_config phy_mpll_config[] = {
1.549 + // 8bpc 10bpc 12bpc
1.550 + // pixelclock cpce gmp cpce gmp cpce gmp
1.551 + { 45250000, { {0x01e0, 0x0000}, {0x21e1, 0x0000}, {0x41e2, 0x0000} } },
1.552 + { 92500000, { {0x0140, 0x0005}, {0x2141, 0x0005}, {0x4142, 0x0005} } },
1.553 + { 148500000, { {0x00a0, 0x000a}, {0x20a1, 0x000a}, {0x40a2, 0x000a} } },
1.554 + { 216000000, { {0x00a0, 0x000a}, {0x2001, 0x000f}, {0x4002, 0x000f} } },
1.555 + { ~0UL, { {0x0000, 0x0000}, {0x0000, 0x0000}, {0x0000, 0x0000} } }
1.556 +};
1.557 +
1.558 +static const struct Phy_curr_ctrl phy_curr_ctrl[] = {
1.559 + // pixelclock 8bpc 10bpc 12bpc
1.560 + { 54000000, {0x091c, 0x091c, 0x06dc} },
1.561 + { 58400000, {0x091c, 0x06dc, 0x06dc} },
1.562 + { 72000000, {0x06dc, 0x06dc, 0x091c} },
1.563 + { 74250000, {0x06dc, 0x0b5c, 0x091c} },
1.564 + { 118800000, {0x091c, 0x091c, 0x06dc} },
1.565 + { 216000000, {0x06dc, 0x0b5c, 0x091c} },
1.566 + { ~0UL, {0x0000, 0x0000, 0x0000} }
1.567 +};
1.568 +
1.569 +static const struct Phy_config phy_config[] = {
1.570 + // pixelclock symbol term vlevel
1.571 + { 216000000, 0x800d, 0x0005, 0x01ad},
1.572 + { ~0UL, 0x0000, 0x0000, 0x0000}
1.573 };
1.574
1.575
1.576 @@ -232,33 +572,114 @@
1.577 // Initialise the HDMI peripheral.
1.578
1.579 Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end,
1.580 - l4_cap_idx_t irq)
1.581 -: _start(start), _end(end), _irq(irq)
1.582 + l4_cap_idx_t irq,
1.583 + struct Jz4740_lcd_panel *panel)
1.584 +: _start(start), _end(end), _irq(irq), _panel(panel)
1.585 {
1.586 // 8-bit registers with 2-bit address shifting.
1.587
1.588 _regs = new Hw::Mmio_register_block<8>(start, 2);
1.589
1.590 + // Initialise I2C state for DDC.
1.591 +
1.592 _segment_read = false;
1.593 _device_register = 0;
1.594
1.595 + // Initialise I2C state for PHY initialisation.
1.596 +
1.597 + _phy_device_register = 0;
1.598 +
1.599 + // Initialise identifying details and capabilities of the hardware.
1.600 +
1.601 get_identification();
1.602 +
1.603 + // Reset interrupts to a minimal, enabled state.
1.604 +
1.605 irq_init();
1.606 - i2c_init();
1.607 - hotplug_init();
1.608 +
1.609 + // Set up DDC and PHY communication.
1.610 +
1.611 + i2c_init(I2c_software_reset, I2c_divider, I2c_int_config0, I2c_int_config1,
1.612 + I2c_int_status, I2c_int_mask);
1.613 + i2c_init(I2c_phy_software_reset, I2c_phy_divider, I2c_phy_int_config0, I2c_phy_int_config1,
1.614 + I2c_phy_int_status, I2c_phy_int_mask);
1.615 +
1.616 + // Enable PHY interrupts.
1.617 +
1.618 + phy_irq_init();
1.619 +}
1.620 +
1.621 +// Pixel clock frequency calculation.
1.622 +
1.623 +unsigned long Hdmi_jz4780_chip::get_pixelclock()
1.624 +{
1.625 + return _pixelclock;
1.626 +
1.627 +/* Calculated frequency, which may not be the actual pixelclock frequency...
1.628 +
1.629 + return (_panel->line_start + _panel->width + _panel->line_end + _panel->hsync) *
1.630 + (_panel->frame_start + _panel->height + _panel->frame_end + _panel->vsync) *
1.631 + _panel->frame_rate;
1.632 +*/
1.633 }
1.634
1.635 +
1.636 +
1.637 +// Update a register by enabling/setting or disabling/clearing the given bits.
1.638 +
1.639 +void Hdmi_jz4780_chip::reg_update(uint32_t reg, uint32_t bits, bool enable)
1.640 +{
1.641 + if (enable)
1.642 + _regs[reg] = _regs[reg] | bits;
1.643 + else
1.644 + _regs[reg] = _regs[reg] & ~bits;
1.645 +}
1.646 +
1.647 +// Update a field. The bits must be shifted to coincide with the mask.
1.648 +
1.649 +void Hdmi_jz4780_chip::reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits)
1.650 +{
1.651 + _regs[reg] = (_regs[reg] & ~(mask)) | (bits & mask);
1.652 +}
1.653 +
1.654 +void Hdmi_jz4780_chip::reg_fill_field(uint32_t reg, uint32_t mask)
1.655 +{
1.656 + _regs[reg] = _regs[reg] | mask;
1.657 +}
1.658 +
1.659 +
1.660 +
1.661 +// Chipset querying.
1.662 +
1.663 void Hdmi_jz4780_chip::get_identification()
1.664 {
1.665 _version = (_regs[Design_id] << 8) | _regs[Revision_id];
1.666 + _phy_type = _regs[Config_id2];
1.667 +
1.668 + // Initialise a member to any matching capabilities or leave it as the "null"
1.669 + // entry.
1.670 +
1.671 + _phy_def = phy_capabilities;
1.672 +
1.673 + while (_phy_def->gen && (_phy_def->type != _phy_type))
1.674 + _phy_def++;
1.675 }
1.676
1.677 void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor)
1.678 {
1.679 - *major = _version >> 12;
1.680 + *major = (_version >> 12) & 0xfff;
1.681 *minor = _version & 0xfff;
1.682 }
1.683
1.684 +void Hdmi_jz4780_chip::get_phy_capabilities(const struct Phy_capabilities **phy_def)
1.685 +{
1.686 + *phy_def = _phy_def;
1.687 +}
1.688 +
1.689 +
1.690 +
1.691 +// Initialisation.
1.692 +
1.693 void Hdmi_jz4780_chip::irq_init()
1.694 {
1.695 // Disable interrupts.
1.696 @@ -273,9 +694,9 @@
1.697 _regs[As_int_mask] = 0xff;
1.698 _regs[Phy_int_mask] = 0xff;
1.699 _regs[I2c_int_mask] = 0xff;
1.700 + _regs[I2c_phy_int_mask] = 0xff;
1.701 _regs[Cec_int_mask] = 0xff;
1.702 _regs[Vp_int_mask] = 0xff;
1.703 - _regs[I2c_phy_int_mask] = 0xff;
1.704 _regs[Ahb_dma_audio_int_mask] = 0xff;
1.705
1.706 // Enable interrupts.
1.707 @@ -283,35 +704,53 @@
1.708 _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all);
1.709 }
1.710
1.711 -void Hdmi_jz4780_chip::i2c_init()
1.712 +void Hdmi_jz4780_chip::phy_irq_init()
1.713 {
1.714 // Set PHY interrupt polarities.
1.715
1.716 - _regs[I2c_phy_int_config0] = I2c_int_config0_done_polarity;
1.717 - _regs[I2c_phy_int_config1] = I2c_int_config1_nack_polarity |
1.718 - I2c_int_config1_arb_polarity;
1.719 + _regs[Phy_polarity] = Phy_status_all;
1.720 +
1.721 + // Enable/unmask second-level interrupts.
1.722 +
1.723 + _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_all);
1.724 +
1.725 + // Clear pending interrupts.
1.726 +
1.727 + _regs[Phy_int_status] = Phy_int_status_all;
1.728 +
1.729 + // Enable/unmask interrupts.
1.730
1.731 + _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_all);
1.732 +}
1.733 +
1.734 +
1.735 +
1.736 +// I2C support.
1.737 +
1.738 +void Hdmi_jz4780_chip::i2c_init(uint32_t reset, uint32_t divider,
1.739 + uint32_t config0, uint32_t config1,
1.740 + uint32_t status, uint32_t mask)
1.741 +{
1.742 // Software reset.
1.743
1.744 - _regs[I2c_software_reset] = 0;
1.745 + _regs[reset] = 0;
1.746
1.747 // Standard mode (100kHz).
1.748
1.749 - _regs[I2c_divider] = 0;
1.750 + _regs[divider] = 0;
1.751
1.752 // Set interrupt polarities.
1.753
1.754 - _regs[I2c_int_config0] = I2c_int_config0_done_polarity;
1.755 - _regs[I2c_int_config1] = I2c_int_config1_nack_polarity |
1.756 - I2c_int_config1_arb_polarity;
1.757 + _regs[config0] = I2c_int_config0_done_polarity;
1.758 + _regs[config1] = I2c_int_config1_nack_polarity | I2c_int_config1_arb_polarity;
1.759
1.760 // Clear and mask/mute interrupts.
1.761
1.762 - _regs[I2c_int_status] = I2c_int_status_done | I2c_int_status_error;
1.763 - _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error;
1.764 + _regs[status] = I2c_int_status_done | I2c_int_status_error;
1.765 + _regs[mask] = I2c_int_status_done | I2c_int_status_error;
1.766 }
1.767
1.768 -long Hdmi_jz4780_chip::i2c_wait()
1.769 +long Hdmi_jz4780_chip::i2c_wait(uint32_t status)
1.770 {
1.771 long err;
1.772 uint8_t int_status;
1.773 @@ -325,7 +764,7 @@
1.774 if (err)
1.775 return err;
1.776
1.777 - int_status = _regs[I2c_int_status];
1.778 + int_status = _regs[status];
1.779
1.780 // Test for an error condition.
1.781
1.782 @@ -334,7 +773,7 @@
1.783
1.784 // Acknowledge the interrupt.
1.785
1.786 - _regs[I2c_int_status] = int_status;
1.787 + _regs[status] = int_status;
1.788
1.789 } while (!(int_status & I2c_int_status_done));
1.790
1.791 @@ -360,7 +799,7 @@
1.792
1.793 // Wait and then read.
1.794
1.795 - err = i2c_wait();
1.796 + err = i2c_wait(I2c_int_status);
1.797 if (err)
1.798 break;
1.799
1.800 @@ -374,6 +813,45 @@
1.801 return i;
1.802 }
1.803
1.804 +int Hdmi_jz4780_chip::i2c_phy_write(uint8_t address, uint16_t value)
1.805 +{
1.806 + i2c_phy_set_address(address);
1.807 + return i2c_phy_write(&value, 1);
1.808 +}
1.809 +
1.810 +int Hdmi_jz4780_chip::i2c_phy_write(uint16_t *buf, unsigned int length)
1.811 +{
1.812 + unsigned int i;
1.813 + long err;
1.814 +
1.815 + // Unmask interrupts.
1.816 +
1.817 + _regs[I2c_phy_int_mask] = 0;
1.818 +
1.819 + for (i = 0; i < length; i++)
1.820 + {
1.821 + // Increment the device register.
1.822 +
1.823 + _regs[I2c_phy_register] = _device_register++;
1.824 + _regs[I2c_phy_operation] = I2c_operation_write;
1.825 +
1.826 + // Write and then wait.
1.827 +
1.828 + _regs[I2c_phy_data_out1] = (buf[i] >> 8) & 0xff;
1.829 + _regs[I2c_phy_data_out0] = buf[i] & 0xff;
1.830 +
1.831 + err = i2c_wait(I2c_phy_int_status);
1.832 + if (err)
1.833 + break;
1.834 + }
1.835 +
1.836 + // Mask interrupts again.
1.837 +
1.838 + _regs[I2c_phy_int_mask] = I2c_int_status_done | I2c_int_status_error;
1.839 +
1.840 + return i;
1.841 +}
1.842 +
1.843 void Hdmi_jz4780_chip::i2c_set_address(uint8_t address)
1.844 {
1.845 _regs[I2c_device_address] = address;
1.846 @@ -381,6 +859,18 @@
1.847 i2c_set_register(0);
1.848 }
1.849
1.850 +void Hdmi_jz4780_chip::i2c_phy_set_address(uint8_t address)
1.851 +{
1.852 + // The Linux drivers seem to set the clear field when changing the PHY device
1.853 + // address, presumably because some manual says so.
1.854 +
1.855 + _regs[Phy_test0] = _regs[Phy_test0] | Phy_test0_clear_mask;
1.856 + _regs[I2c_phy_device_address] = address;
1.857 + _regs[Phy_test0] = _regs[Phy_test0] & ~Phy_test0_clear_mask;
1.858 +
1.859 + i2c_phy_set_register(0);
1.860 +}
1.861 +
1.862 void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment)
1.863 {
1.864 _regs[I2c_segment_address] = 0x30;
1.865 @@ -394,25 +884,197 @@
1.866 _device_register = device_register;
1.867 }
1.868
1.869 -void Hdmi_jz4780_chip::hotplug_init()
1.870 +void Hdmi_jz4780_chip::i2c_phy_set_register(uint8_t device_register)
1.871 +{
1.872 + _phy_device_register = device_register;
1.873 +}
1.874 +
1.875 +
1.876 +
1.877 +// PHY operations.
1.878 +
1.879 +void Hdmi_jz4780_chip::phy_enable_powerdown(bool enable)
1.880 +{
1.881 + reg_update(Phy_config, Phy_config_powerdown_disable, !enable);
1.882 +}
1.883 +
1.884 +void Hdmi_jz4780_chip::phy_enable_tmds(bool enable)
1.885 +{
1.886 + reg_update(Phy_config, Phy_config_tmds, enable);
1.887 +}
1.888 +
1.889 +void Hdmi_jz4780_chip::phy_enable_svsret(bool enable)
1.890 {
1.891 - // Set PHY interrupt polarities.
1.892 + reg_update(Phy_config, Phy_config_svsret, enable);
1.893 +}
1.894 +
1.895 +void Hdmi_jz4780_chip::phy_enable_gen2_powerdown(bool enable)
1.896 +{
1.897 + reg_update(Phy_config, Phy_config_gen2_powerdown, enable);
1.898 +}
1.899 +
1.900 +void Hdmi_jz4780_chip::phy_enable_gen2_tx_power(bool enable)
1.901 +{
1.902 + reg_update(Phy_config, Phy_config_gen2_tx_power, enable);
1.903 +}
1.904 +
1.905 +void Hdmi_jz4780_chip::phy_enable_interface(bool enable)
1.906 +{
1.907 + reg_update(Phy_config, Phy_config_select_data_enable_polarity, enable);
1.908 + reg_update(Phy_config, Phy_config_select_interface_control, !enable);
1.909 +}
1.910 +
1.911 +// Configure the PHY. Various things not supported by the JZ4780 PHY are ignored
1.912 +// such as the TDMS clock ratio (dependent on HDMI 2 and content scrambling).
1.913 +
1.914 +long Hdmi_jz4780_chip::phy_configure()
1.915 +{
1.916 + long err;
1.917
1.918 - _regs[Phy_polarity] = Phy_status_hotplug_detect | Phy_status_rx_sense_all;
1.919 + phy_power_off();
1.920 +
1.921 + if (_phy_def->svsret)
1.922 + phy_enable_svsret(true);
1.923 +
1.924 + phy_reset();
1.925 +
1.926 + _regs[Main_heac_phy_reset] = Main_heac_phy_reset_assert;
1.927 +
1.928 + i2c_phy_set_address(I2c_phy_device_phy_gen2);
1.929 +
1.930 + if (_phy_def->configure)
1.931 + {
1.932 + err = phy_configure_specific();
1.933 + if (err)
1.934 + return err;
1.935 + }
1.936 +
1.937 + // NOTE: TMDS clock delay here in Linux driver.
1.938 +
1.939 + phy_power_on();
1.940
1.941 - // Enable/unmask second-level interrupts.
1.942 + return L4_EOK;
1.943 +}
1.944 +
1.945 +// Configure for the JZ4780 specifically.
1.946 +
1.947 +long Hdmi_jz4780_chip::phy_configure_specific()
1.948 +{
1.949 + const struct Phy_mpll_config *m = phy_mpll_config;
1.950 + const struct Phy_curr_ctrl *c = phy_curr_ctrl;
1.951 + const struct Phy_config *p = phy_config;
1.952 + unsigned long pixelclock = get_pixelclock();
1.953 +
1.954 + // Find MPLL, CURR_CTRL and PHY configuration settings appropriate for the
1.955 + // pixel clock frequency.
1.956 +
1.957 + while (m->pixelclock && (pixelclock > m->pixelclock))
1.958 + m++;
1.959 +
1.960 + while (c->pixelclock && (pixelclock > c->pixelclock))
1.961 + c++;
1.962 +
1.963 + while (p->pixelclock && (pixelclock > p->pixelclock))
1.964 + p++;
1.965 +
1.966 + printf("MPLL for %ld; CURR_CTRL for %ld; PHY for %ld\n", m->pixelclock, c->pixelclock, p->pixelclock);
1.967
1.968 - _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_hotplug_detect | Phy_status_rx_sense_all);
1.969 + if (!m->pixelclock || !c->pixelclock || !p->pixelclock)
1.970 + return -L4_EINVAL;
1.971 +
1.972 + // Using values for 8bpc from the tables.
1.973 +
1.974 + // Initialise MPLL.
1.975 +
1.976 + i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, m->res[Phy_resolution_8bpc].cpce);
1.977 + i2c_phy_write(I2c_phy_3d_tx_gmp_ctrl, m->res[Phy_resolution_8bpc].gmp);
1.978 +
1.979 + // Initialise CURRCTRL.
1.980 +
1.981 + i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, c->curr[Phy_resolution_8bpc]);
1.982 +
1.983 + // Initialise PHY_CONFIG.
1.984 +
1.985 + i2c_phy_write(I2c_phy_3d_tx_pll_phby_ctrl, 0);
1.986 + i2c_phy_write(I2c_phy_3d_tx_msm_ctrl, Msm_ctrl_clock_output_select_fb);
1.987 +
1.988 + i2c_phy_write(I2c_phy_3d_tx_term, p->term);
1.989 + i2c_phy_write(I2c_phy_3d_tx_clock_symbol_ctrl, p->symbol);
1.990 + i2c_phy_write(I2c_phy_3d_tx_vlevel_ctrl, p->vlevel);
1.991
1.992 - // Clear pending interrupts.
1.993 + // Override and disable clock termination.
1.994 +
1.995 + i2c_phy_write(I2c_phy_3d_tx_clock_cal_ctrl, Clock_cal_ctrl_override);
1.996 +
1.997 + return L4_EOK;
1.998 +}
1.999 +
1.1000 +long Hdmi_jz4780_chip::phy_init()
1.1001 +{
1.1002 + printf("phy_init...\n");
1.1003 +
1.1004 + long err;
1.1005 + int i;
1.1006 +
1.1007 + // Initialisation repeated for HDMI PHY specification reasons.
1.1008 +
1.1009 + for (i = 0; i < 2; i++)
1.1010 + {
1.1011 + phy_enable_interface(true);
1.1012 + err = phy_configure();
1.1013 + if (err)
1.1014 + return err;
1.1015 + }
1.1016
1.1017 - _regs[Phy_int_status] = Phy_int_status_hotplug_detect | Phy_int_status_rx_sense_all;
1.1018 + return L4_EOK;
1.1019 +}
1.1020 +
1.1021 +void Hdmi_jz4780_chip::phy_reset()
1.1022 +{
1.1023 + _regs[Main_reset] = 1;
1.1024 + _regs[Main_reset] = 0;
1.1025 +}
1.1026 +
1.1027 +void Hdmi_jz4780_chip::phy_power_off()
1.1028 +{
1.1029 + printf("phy_power_off...\n");
1.1030 +
1.1031 + if (_phy_def && (_phy_def->gen == 1))
1.1032 + {
1.1033 + phy_enable_tmds(false);
1.1034 + phy_enable_powerdown(true);
1.1035 + return;
1.1036 + }
1.1037 +
1.1038 + phy_enable_gen2_tx_power(false);
1.1039 +
1.1040 + wait_for_tx_phy_lock(0);
1.1041
1.1042 - // Enable/unmask interrupts.
1.1043 + phy_enable_gen2_powerdown(true);
1.1044 +}
1.1045 +
1.1046 +void Hdmi_jz4780_chip::phy_power_on()
1.1047 +{
1.1048 + printf("phy_power_on...\n");
1.1049
1.1050 - _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_hotplug_detect | Phy_int_status_rx_sense_all);
1.1051 + if (_phy_def && (_phy_def->gen == 1))
1.1052 + {
1.1053 + phy_enable_powerdown(false);
1.1054 + phy_enable_tmds(false);
1.1055 + phy_enable_tmds(true);
1.1056 + return;
1.1057 + }
1.1058 +
1.1059 + phy_enable_gen2_tx_power(true);
1.1060 + phy_enable_gen2_powerdown(false);
1.1061 +
1.1062 + wait_for_tx_phy_lock(1);
1.1063 }
1.1064
1.1065 +
1.1066 +
1.1067 +// Hotplug detection.
1.1068 +
1.1069 bool Hdmi_jz4780_chip::connected()
1.1070 {
1.1071 return (_regs[Phy_status] & Phy_status_hotplug_detect) != 0;
1.1072 @@ -420,8 +1082,19 @@
1.1073
1.1074 long Hdmi_jz4780_chip::wait_for_connection()
1.1075 {
1.1076 + return wait_for_phy_irq(Phy_int_status_hotplug_detect, Phy_status_hotplug_detect,
1.1077 + Phy_status_hotplug_detect);
1.1078 +}
1.1079 +
1.1080 +// General PHY interrupt handling.
1.1081 +
1.1082 +long Hdmi_jz4780_chip::wait_for_phy_irq(uint32_t int_status_flags,
1.1083 + uint32_t status_flags,
1.1084 + uint32_t status_values)
1.1085 +{
1.1086 long err;
1.1087 - uint8_t int_status, polarity;
1.1088 + uint8_t int_status, status;
1.1089 + uint8_t status_unchanged = ~(status_values) & status_flags;
1.1090 l4_msgtag_t tag;
1.1091
1.1092 do
1.1093 @@ -435,27 +1108,310 @@
1.1094 // Obtain the details.
1.1095
1.1096 int_status = _regs[Phy_int_status];
1.1097 - polarity = _regs[Phy_polarity];
1.1098 + status = _regs[Phy_status];
1.1099
1.1100 // Acknowledge the interrupt.
1.1101
1.1102 - _regs[Phy_int_status] = int_status;
1.1103 + _regs[Phy_int_status] = int_status_flags;
1.1104 +
1.1105 + // Continue without a handled event.
1.1106 + // An event is handled when detected and when the status differs from
1.1107 + // the unchanged state.
1.1108 +
1.1109 + printf("Status: %x versus %x\n", status & status_flags, status_unchanged);
1.1110 +
1.1111 + } while (!((int_status & int_status_flags) &&
1.1112 + ((status & status_flags) ^ status_unchanged)));
1.1113 +
1.1114 + return L4_EOK;
1.1115 +}
1.1116 +
1.1117 +// Wait for TX_PHY_LOCK to become high or low.
1.1118 +
1.1119 +long Hdmi_jz4780_chip::wait_for_tx_phy_lock(int level)
1.1120 +{
1.1121 + if (!!(_regs[Phy_status] & Phy_status_tx_phy_lock) == level)
1.1122 + return L4_EOK;
1.1123 +
1.1124 + return wait_for_phy_irq(Phy_int_status_tx_phy_lock, Phy_status_tx_phy_lock,
1.1125 + level ? Phy_status_tx_phy_lock : Phy_status_none);
1.1126 +}
1.1127 +
1.1128 +
1.1129 +
1.1130 +// Output setup operations.
1.1131 +
1.1132 +long Hdmi_jz4780_chip::enable(unsigned long pixelclock)
1.1133 +{
1.1134 + _pixelclock = pixelclock;
1.1135 +
1.1136 + // Disable frame composer overflow interrupts.
1.1137 +
1.1138 + enable_overflow_irq(false);
1.1139
1.1140 - // Continue without a hotplug event indicating connection.
1.1141 + // NOTE: Here, CEA modes are normally detected and thus the output encoding.
1.1142 + // NOTE: Instead, a fixed RGB output encoding and format is used.
1.1143 + // NOTE: Meanwhile, the input encoding and format will also be fixed to a RGB
1.1144 + // NOTE: representation.
1.1145 +
1.1146 + // _bits_per_channel = 8;
1.1147 + // _data_enable_polarity = true;
1.1148 +
1.1149 + // HDMI initialisation "step B.1": video frame initialisation.
1.1150 +
1.1151 + frame_init();
1.1152 +
1.1153 + // HDMI initialisation "step B.2": PHY initialisation.
1.1154 +
1.1155 + long err = phy_init();
1.1156 + if (err)
1.1157 + return err;
1.1158
1.1159 - } while (!((int_status & Phy_int_status_hotplug_detect) &&
1.1160 - (polarity & Phy_status_hotplug_detect)));
1.1161 + // HDMI initialisation "step B.3": video signal initialisation.
1.1162 +
1.1163 + data_path_init();
1.1164 +
1.1165 + // With audio, various clock updates are needed.
1.1166 +
1.1167 + // NOTE: DVI mode is being assumed for now, for simplicity.
1.1168 +
1.1169 + // In non-DVI mode, the AVI, vendor-specific infoframe and regular infoframe
1.1170 + // are set up.
1.1171 +
1.1172 + packet_init();
1.1173 + csc_init();
1.1174 + sample_init();
1.1175 + hdcp_init();
1.1176 +
1.1177 + // Enable frame composer overflow interrupts.
1.1178 +
1.1179 + enable_overflow_irq(true);
1.1180
1.1181 return L4_EOK;
1.1182 }
1.1183
1.1184 +void Hdmi_jz4780_chip::enable_overflow_irq(bool enable)
1.1185 +{
1.1186 + reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable);
1.1187 +}
1.1188 +
1.1189 +void Hdmi_jz4780_chip::frame_init()
1.1190 +{
1.1191 + printf("frame_init...\n");
1.1192 +
1.1193 + // Initialise the video configuration. This is rather like the initialisation
1.1194 + // of the LCD controller. The sync and data enable polarities are set up, plus
1.1195 + // extras like HDCP, DVI mode, progressive/interlace.
1.1196 + // NOTE: Here, the JZ4740-specific configuration is used to store the picture
1.1197 + // NOTE: properties, but a neutral structure should be adopted.
1.1198 +
1.1199 + uint8_t config = 0;
1.1200 +
1.1201 + config |= (_panel->config & Jz4740_lcd_hsync_negative)
1.1202 + ? Fc_video_config_hsync_active_low
1.1203 + : Fc_video_config_hsync_active_high;
1.1204 +
1.1205 + config |= (_panel->config & Jz4740_lcd_vsync_negative)
1.1206 + ? Fc_video_config_vsync_active_low
1.1207 + : Fc_video_config_vsync_active_high;
1.1208 +
1.1209 + config |= (_panel->config & Jz4740_lcd_de_negative)
1.1210 + ? Fc_video_config_data_enable_active_low
1.1211 + : Fc_video_config_data_enable_active_high;
1.1212 +
1.1213 + // NOTE: Only supporting DVI mode so far.
1.1214 +
1.1215 + config |= Fc_video_config_dvi_mode;
1.1216 +
1.1217 + // NOTE: Not supporting HDCP.
1.1218 +
1.1219 + config |= Fc_video_config_hdcp_keepout_inactive;
1.1220 +
1.1221 + // NOTE: Only supporting progressive scan so far.
1.1222 +
1.1223 + config |= Fc_video_config_progressive;
1.1224 + config |= Fc_video_config_osc_active_low;
1.1225 +
1.1226 + _regs[Fc_video_config] = config;
1.1227 +
1.1228 + printf("Fc_video_config (%x) = %x\n", Fc_video_config, (uint8_t) _regs[Fc_video_config]);
1.1229 +
1.1230 + // Then, the frame characteristics (visible area, sync pulse) are set. Indeed,
1.1231 + // the frame area details should be practically the same as those used by the
1.1232 + // LCD controller.
1.1233 +
1.1234 + uint16_t hblank = _panel->line_start + _panel->line_end + _panel->hsync,
1.1235 + vblank = _panel->frame_start + _panel->frame_end + _panel->vsync,
1.1236 + hsync_delay = _panel->line_end,
1.1237 + vsync_delay = _panel->frame_end,
1.1238 + hsync_width = _panel->hsync,
1.1239 + vsync_height = _panel->vsync;
1.1240 +
1.1241 + _regs[Fc_horizontal_active_width1] = (_panel->width >> 8) & 0xff;
1.1242 + _regs[Fc_horizontal_active_width0] = _panel->width & 0xff;
1.1243 +
1.1244 + _regs[Fc_horizontal_blank_width1] = (hblank >> 8) & 0xff;
1.1245 + _regs[Fc_horizontal_blank_width0] = hblank & 0xff;
1.1246 +
1.1247 + _regs[Fc_vertical_active_height1] = (_panel->height >> 8) & 0xff;
1.1248 + _regs[Fc_vertical_active_height0] = _panel->height & 0xff;
1.1249 +
1.1250 + _regs[Fc_vertical_blank_height] = vblank & 0xff;
1.1251 +
1.1252 + _regs[Fc_hsync_delay1] = (hsync_delay >> 8) & 0xff;
1.1253 + _regs[Fc_hsync_delay0] = hsync_delay & 0xff;
1.1254 +
1.1255 + _regs[Fc_vsync_delay] = vsync_delay & 0xff;
1.1256 +
1.1257 + _regs[Fc_hsync_width1] = (hsync_width >> 8) & 0xff;
1.1258 + _regs[Fc_hsync_width0] = hsync_width & 0xff;
1.1259 +
1.1260 + _regs[Fc_vsync_height] = vsync_height & 0xff;
1.1261 +}
1.1262 +
1.1263 +void Hdmi_jz4780_chip::data_path_init()
1.1264 +{
1.1265 + printf("data_path_init...\n");
1.1266 +
1.1267 + // Initialise the path of the video data. Here, the elements of the data
1.1268 + // stream are defined such as the control period duration, data channel
1.1269 + // characteristics, pixel and TMDS clocks, and the involvement of colour space
1.1270 + // conversion.
1.1271 +
1.1272 + // Control period minimum duration.
1.1273 +
1.1274 + _regs[Fc_control_duration] = 12;
1.1275 + _regs[Fc_ex_control_duration] = 32;
1.1276 + _regs[Fc_ex_control_space] = 1;
1.1277 +
1.1278 + // Set to fill TMDS data channels.
1.1279 +
1.1280 + _regs[Fc_channel0_preamble] = 0x0b;
1.1281 + _regs[Fc_channel1_preamble] = 0x16;
1.1282 + _regs[Fc_channel2_preamble] = 0x21;
1.1283 +
1.1284 + // Apparent two-stage clock activation.
1.1285 +
1.1286 + uint8_t clock_disable = Main_clock_disable_hdcp |
1.1287 + Main_clock_disable_csc |
1.1288 + Main_clock_disable_audio |
1.1289 + Main_clock_disable_prep |
1.1290 + Main_clock_disable_tmds;
1.1291 +
1.1292 + // Activate the pixel clock.
1.1293 +
1.1294 + _regs[Main_clock_disable] = clock_disable;
1.1295 +
1.1296 + // Then activate the TMDS clock.
1.1297 +
1.1298 + clock_disable &= ~(Main_clock_disable_tmds);
1.1299 + _regs[Main_clock_disable] = clock_disable;
1.1300 +
1.1301 + // NOTE: Bypass colour space conversion for now.
1.1302 +
1.1303 + _regs[Main_flow_control] = Main_flow_control_csc_inactive;
1.1304 +}
1.1305 +
1.1306 +void Hdmi_jz4780_chip::packet_init()
1.1307 +{
1.1308 + printf("packet_init...\n");
1.1309 +
1.1310 + // Initialise the video packet details.
1.1311 + // NOTE: With 24bpp RGB output only for now, no pixel repetition.
1.1312 +
1.1313 + int colour_depth = 4;
1.1314 +
1.1315 + _regs[Packet_pixel_repeater] =
1.1316 + ((colour_depth << Packet_pixel_repeater_depth_offset) &
1.1317 + Packet_pixel_repeater_depth_mask);
1.1318 +
1.1319 + _regs[Packet_remap] = Packet_remap_ycc422_16bit;
1.1320 +
1.1321 + reg_fill_field(Packet_stuffing, Packet_stuffing_pr |
1.1322 + Packet_stuffing_default_phase |
1.1323 + Packet_stuffing_pp |
1.1324 + Packet_stuffing_ycc422);
1.1325 +
1.1326 + // Disable pixel repeater.
1.1327 +
1.1328 + reg_update_field(Packet_config, Packet_config_pr_enable |
1.1329 + Packet_config_bypass_select_packetizer |
1.1330 + Packet_config_bypass_enable |
1.1331 + Packet_config_pp_enable |
1.1332 + Packet_config_ycc422_enable |
1.1333 + Packet_config_output_selector_mask,
1.1334 + Packet_config_bypass_select_packetizer |
1.1335 + Packet_config_bypass_enable |
1.1336 + Packet_config_output_selector_bypass);
1.1337 +}
1.1338 +
1.1339 +void Hdmi_jz4780_chip::csc_init()
1.1340 +{
1.1341 + printf("csc_init...\n");
1.1342 +
1.1343 + // Initialise the colour space conversion details.
1.1344 + // NOTE: No conversion will be done yet (see data_path_init).
1.1345 +
1.1346 + _regs[Csc_config] = Csc_config_interpolation_disable |
1.1347 + Csc_config_decimation_disable;
1.1348 +
1.1349 + // NOTE: Use 8bpc (24bpp) for now.
1.1350 +
1.1351 + reg_update_field(Csc_scale, Csc_scale_colour_depth_mask, Csc_scale_colour_depth_24bpp);
1.1352 +
1.1353 + // NOTE: Coefficients should be set here.
1.1354 +}
1.1355 +
1.1356 +void Hdmi_jz4780_chip::sample_init()
1.1357 +{
1.1358 + printf("sample_init...\n");
1.1359 +
1.1360 + // Initialise the mapping of video input data.
1.1361 + // NOTE: With 24bpp RGB input only for now.
1.1362 +
1.1363 + int colour_format = 0x01;
1.1364 +
1.1365 + // Data enable inactive.
1.1366 +
1.1367 + _regs[Sample_video_config] = (colour_format & Sample_video_config_mapping_mask);
1.1368 +
1.1369 + // Transmission stuffing when data enable is inactive.
1.1370 +
1.1371 + _regs[Sample_video_stuffing] = Sample_video_stuffing_bdb_data |
1.1372 + Sample_video_stuffing_rcr_data |
1.1373 + Sample_video_stuffing_gy_data;
1.1374 +
1.1375 + _regs[Sample_gy_data0] = 0;
1.1376 + _regs[Sample_gy_data1] = 0;
1.1377 + _regs[Sample_rcr_data0] = 0;
1.1378 + _regs[Sample_rcr_data1] = 0;
1.1379 + _regs[Sample_bcb_data0] = 0;
1.1380 + _regs[Sample_bcb_data1] = 0;
1.1381 +}
1.1382 +
1.1383 +void Hdmi_jz4780_chip::hdcp_init()
1.1384 +{
1.1385 + printf("hdcp_init...\n");
1.1386 +
1.1387 + // Initialise HDCP registers, mostly turning things off.
1.1388 +
1.1389 + reg_update(Hdcp_config0, Hdcp_config0_rxdetect_enable, false);
1.1390 +
1.1391 + reg_update(Hdcp_video_polarity,
1.1392 + Hdcp_video_polarity_data_enable_active_high,
1.1393 + !(_panel->config & Jz4740_lcd_de_negative));
1.1394 +
1.1395 + reg_update(Hdcp_config1, Hdcp_config1_encryption_disable, true);
1.1396 +}
1.1397 +
1.1398
1.1399
1.1400 // C language interface functions.
1.1401
1.1402 -void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq)
1.1403 +void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq,
1.1404 + struct Jz4740_lcd_panel *panel)
1.1405 {
1.1406 - return (void *) new Hdmi_jz4780_chip(start, end, irq);
1.1407 + return (void *) new Hdmi_jz4780_chip(start, end, irq, panel);
1.1408 }
1.1409
1.1410 void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor)
1.1411 @@ -463,6 +1419,11 @@
1.1412 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_version(major, minor);
1.1413 }
1.1414
1.1415 +void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def)
1.1416 +{
1.1417 + static_cast<Hdmi_jz4780_chip *>(hdmi)->get_phy_capabilities(phy_def);
1.1418 +}
1.1419 +
1.1420 int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length)
1.1421 {
1.1422 return static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_read(buf, length);
1.1423 @@ -492,3 +1453,8 @@
1.1424 {
1.1425 return static_cast<Hdmi_jz4780_chip *>(hdmi)->wait_for_connection();
1.1426 }
1.1427 +
1.1428 +long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock)
1.1429 +{
1.1430 + return static_cast<Hdmi_jz4780_chip *>(hdmi)->enable(pixelclock);
1.1431 +}