1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pkg/devices/lib/rtc/include/rtc-defs.h Sat May 04 01:31:54 2024 +0200
1.3 @@ -0,0 +1,125 @@
1.4 +/*
1.5 + * RTC (real-time clock) support for various devices.
1.6 + *
1.7 + * Copyright (C) 2023, 2024 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software; you can redistribute it and/or
1.10 + * modify it under the terms of the GNU General Public License as
1.11 + * published by the Free Software Foundation; either version 2 of
1.12 + * the License, or (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program; if not, write to the Free Software
1.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.22 + * Boston, MA 02110-1301, USA
1.23 + */
1.24 +
1.25 +#pragma once
1.26 +
1.27 +#ifdef __cplusplus
1.28 +
1.29 +// Register locations.
1.30 +
1.31 +enum Regs : unsigned
1.32 +{
1.33 + Rtc_control = 0x000, // RTCCR
1.34 + Rtc_seconds = 0x004, // RTCSR
1.35 + Rtc_alarm_seconds = 0x008, // RTCSAR
1.36 + Rtc_regulator = 0x00c, // RTCGR
1.37 +
1.38 + Hibernate_control = 0x020, // HCR
1.39 + Hibernate_wakeup_filter_counter = 0x024, // HWFCR
1.40 + Hibernate_reset_counter = 0x028, // HRCR
1.41 + Hibernate_wakeup_control = 0x02c, // HWCR
1.42 + Hibernate_wakeup_status = 0x030, // HWRSR
1.43 + Hibernate_scratch_pattern = 0x034, // HSPR
1.44 + Hibernate_write_enable_pattern = 0x03c, // WENR
1.45 + Hibernate_wakeup_pin_configure = 0x048, // WKUPPINCR
1.46 +};
1.47 +
1.48 +// Field definitions.
1.49 +
1.50 +enum Control_bits : unsigned
1.51 +{
1.52 + Control_write_ready = 0x80, // WRDY
1.53 + Control_1Hz = 0x40, // 1HZ
1.54 + Control_1Hz_irq_enable = 0x20, // 1HZIE
1.55 + Control_alarm = 0x10, // AF
1.56 + Control_alarm_irq_enable = 0x08, // AIE
1.57 + Control_alarm_enable = 0x04, // AE
1.58 + Control_external_divided = 0x02, // SELEXC (JZ4780)
1.59 + Control_rtc_enable = 0x01, // RTCE
1.60 +};
1.61 +
1.62 +enum Regulator_bits : unsigned
1.63 +{
1.64 + Regulator_lock = 0x80000000, // LOCK
1.65 + Regulator_adjust_count_mask = 0x03ff0000, // ADJC
1.66 + Regulator_1Hz_cycle_count_mask = 0x0000ffff, // NC1HZ
1.67 +};
1.68 +
1.69 +enum Regulator_limits : unsigned
1.70 +{
1.71 + Regulator_adjust_count_limit = 0x03ff, // ADJC
1.72 + Regulator_1Hz_cycle_count_limit = 0xffff, // NC1HZ
1.73 +};
1.74 +
1.75 +enum Regulator_shifts : unsigned
1.76 +{
1.77 + Regulator_adjust_count_shift = 16, // ADJC
1.78 + Regulator_1Hz_cycle_count_shift = 0, // NC1HZ
1.79 +};
1.80 +
1.81 +enum Hibernate_control_bits : unsigned
1.82 +{
1.83 + Hibernate_power_down = 0x01, // PD
1.84 +};
1.85 +
1.86 +enum Hibernate_wakeup_filter_counter_bits : unsigned
1.87 +{
1.88 + Wakeup_minimum_time_mask = 0xffe0, // HWFCR
1.89 +};
1.90 +
1.91 +enum Hibernate_reset_counter_bits : unsigned
1.92 +{
1.93 + Reset_assert_time_mask = 0x7800, // HRCR
1.94 +};
1.95 +
1.96 +enum Hibernate_wakeup_control_bits : unsigned
1.97 +{
1.98 + Power_detect_enable_mask = 0xfffffff8, // EPDET
1.99 + Rtc_alarm_wakeup_enable = 0x00000001, // EALM
1.100 +};
1.101 +
1.102 +enum Hibernate_wakeup_status_bits : unsigned
1.103 +{
1.104 + Accident_power_down = 0x0100, // APD
1.105 + Hibernate_reset = 0x0020, // HR
1.106 + Pad_pin_reset = 0x0010, // PPR
1.107 + Wakeup_pin_status = 0x0002, // PIN
1.108 + Rtc_alarm_status = 0x0001, // ALM
1.109 +};
1.110 +
1.111 +enum Hibernate_write_enable_pattern_bits : unsigned
1.112 +{
1.113 + Write_enable_status = 0x80000000, // WEN
1.114 + Write_enable_pattern_mask = 0x0000ffff, // WENPAT
1.115 + Write_enable_pattern = 0x0000a55a, // WENPAT
1.116 +};
1.117 +
1.118 +enum Hibernate_wakeup_pin_configure_bits : unsigned
1.119 +{
1.120 + Rtc_oscillator_test_enable = 0x00080000, // OSC_TE
1.121 + Oscillator_xtclk_rtclk = 0x00040000, // OSC_RETON
1.122 + Oscillator_xtclk_low = 0x00000000, // OSC_RETON
1.123 + Rtc_internal_oscillator_enable = 0x00010000, // OSC_EN
1.124 + Wakeup_pin_extended_press_mask = 0x000000f0, // P_JUD_LEN
1.125 + Wakeup_pin_extended_press_enable = 0x0000000f, // P_RST_LEN
1.126 +};
1.127 +
1.128 +#endif /* __cplusplus */