1.1 --- a/pkg/devices/lib/cpm/src/jz4780.cc Mon Oct 30 17:25:00 2023 +0100
1.2 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Fri Nov 03 18:09:49 2023 +0100
1.3 @@ -90,7 +90,7 @@
1.4 Clock_source_lcd1 (Divider_lcd1, 3, 30), // LPCS
1.5 Clock_source_msc (Divider_msc0, 3, 30), // MPCS
1.6 Clock_source_pcm (Divider_pcm, 7, 29), // PCMS, PCMPCS
1.7 - Clock_source_ssi (Divider_ssi, 1, 30), // SPCS
1.8 + Clock_source_ssi (Divider_ssi, 3, 30), // SCS, SPCS
1.9 Clock_source_uhc (Divider_uhc, 3, 30), // UHCS
1.10 Clock_source_vpu (Divider_vpu, 3, 30), // VCS
1.11
1.12 @@ -166,7 +166,7 @@
1.13 Clock_gate_mac (Clock_gate0, 1, 23, true), // MAC
1.14 Clock_gate_gps (Clock_gate0, 1, 22, true), // GPS
1.15 Clock_gate_dma (Clock_gate0, 1, 21, true), // PDMA
1.16 - Clock_gate_ssi2 (Clock_gate0, 1, 20, true), // SSI2
1.17 + //Clock_gate_ssi2 (Clock_gate0, 1, 20, true), // SSI2
1.18 Clock_gate_ssi1 (Clock_gate0, 1, 19, true), // SSI1
1.19 Clock_gate_uart3 (Clock_gate0, 1, 18, true), // UART3
1.20 Clock_gate_uart2 (Clock_gate0, 1, 17, true), // UART2
1.21 @@ -357,9 +357,7 @@
1.22
1.23 clock_ssi0((Source(mux_clock_ssi)), Control(Clock_gate_ssi0)),
1.24
1.25 - clock_ssi1((Source(mux_clock_ssi)), Control(Clock_gate_ssi1)),
1.26 -
1.27 - clock_ssi2((Source(mux_clock_ssi)), Control(Clock_gate_ssi2));
1.28 + clock_ssi1((Source(mux_clock_ssi)), Control(Clock_gate_ssi1));
1.29
1.30 static Clock_divided
1.31 clock_bch(Source(mux_core, Clock_source_bch),
1.32 @@ -441,25 +439,29 @@
1.33 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
1.34 Divider_pll(Pll_multiplier_A, Pll_input_division_A,
1.35 Pll_output_division_A,
1.36 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
1.37 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
1.38 + true)),
1.39
1.40 clock_pll_E(Source(mux_external),
1.41 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
1.42 Divider_pll(Pll_multiplier_E, Pll_input_division_E,
1.43 Pll_output_division_E,
1.44 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
1.45 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
1.46 + true)),
1.47
1.48 clock_pll_M(Source(mux_external),
1.49 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
1.50 Divider_pll(Pll_multiplier_M, Pll_input_division_M,
1.51 Pll_output_division_M,
1.52 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
1.53 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
1.54 + true)),
1.55
1.56 clock_pll_V(Source(mux_external),
1.57 Control_pll(Pll_enable_V, Pll_stable_V, Pll_bypass_V),
1.58 Divider_pll(Pll_multiplier_V, Pll_input_division_V,
1.59 Pll_output_division_V,
1.60 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max));
1.61 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
1.62 + true));
1.63
1.64
1.65
1.66 @@ -521,7 +523,7 @@
1.67 &clock_ssi,
1.68 &clock_ssi0,
1.69 &clock_ssi1,
1.70 - &clock_ssi2,
1.71 + &clock_none, // Clock_ssi2
1.72 &clock_none, // Clock_timer
1.73 &clock_uart0,
1.74 &clock_uart1,