1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pkg/devices/lib/cpm/include/cpm-x1600.h Thu Sep 14 00:11:14 2023 +0200
1.3 @@ -0,0 +1,197 @@
1.4 +/*
1.5 + * CPM (clock and power management) support for the X1600.
1.6 + *
1.7 + * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software; you can redistribute it and/or
1.10 + * modify it under the terms of the GNU General Public License as
1.11 + * published by the Free Software Foundation; either version 2 of
1.12 + * the License, or (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program; if not, write to the Free Software
1.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.22 + * Boston, MA 02110-1301, USA
1.23 + */
1.24 +
1.25 +#pragma once
1.26 +
1.27 +#include <l4/devices/cpm.h>
1.28 +
1.29 +#include <l4/sys/types.h>
1.30 +#include <stdint.h>
1.31 +
1.32 +
1.33 +
1.34 +#ifdef __cplusplus
1.35 +
1.36 +#include <l4/devices/hw_register_block.h>
1.37 +
1.38 +/* A simple abstraction for accessing the CPM registers.
1.39 + * A proper device could inherit from Hw::Device and use an
1.40 + * Int_property for _exclk_freq. */
1.41 +
1.42 +class Cpm_x1600_chip : public Cpm_chip
1.43 +{
1.44 +private:
1.45 + Hw::Register_block<32> _regs;
1.46 + uint32_t _exclk_freq;
1.47 +
1.48 + // Utility methods.
1.49 +
1.50 + uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift);
1.51 + void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value);
1.52 + uint8_t _get_divider(uint32_t reg, uint32_t mask, uint8_t shift);
1.53 +
1.54 + // PLL control.
1.55 +
1.56 + int have_pll(uint32_t pll_reg);
1.57 + int pll_enabled(uint32_t pll_reg);
1.58 + int pll_bypassed(uint32_t pll_reg);
1.59 + void pll_disable(uint32_t pll_reg);
1.60 + void pll_enable(uint32_t pll_reg);
1.61 +
1.62 + // General frequency modifiers.
1.63 +
1.64 + uint16_t get_multiplier(uint32_t pll_reg);
1.65 + void set_multiplier(uint32_t pll_reg, uint16_t multiplier);
1.66 + uint8_t get_input_division(uint32_t pll_reg);
1.67 + void set_input_division(uint32_t pll_reg, uint8_t divider);
1.68 + uint8_t get_output_division(uint32_t pll_reg);
1.69 + void set_output_division(uint32_t pll_reg, uint8_t divider);
1.70 +
1.71 + // Clock dividers.
1.72 +
1.73 + void set_lcd_pixel_divider(uint8_t controller, uint16_t division);
1.74 +
1.75 + // Input frequencies.
1.76 +
1.77 + uint32_t get_pll_frequency(uint32_t pll_reg);
1.78 +
1.79 + // Clock sources.
1.80 +
1.81 + void set_hclock2_source(uint8_t source);
1.82 + void set_lcd_source(uint8_t controller, uint8_t source);
1.83 +
1.84 + // Clock control.
1.85 +
1.86 + uint32_t get_clock_gate_register(enum Clock_identifiers clock);
1.87 + uint32_t get_clock_gate_value(enum Clock_identifiers clock);
1.88 +
1.89 +public:
1.90 + void set_pclock_source(uint8_t source);
1.91 + Cpm_x1600_chip(l4_addr_t addr, uint32_t exclk_freq);
1.92 +
1.93 + int have_clock(enum Clock_identifiers clock);
1.94 + void start_clock(enum Clock_identifiers clock);
1.95 + void stop_clock(enum Clock_identifiers clock);
1.96 +
1.97 + // Clock divider values.
1.98 +
1.99 + uint8_t get_cpu_divider();
1.100 + uint8_t get_hclock0_divider();
1.101 + uint8_t get_hclock2_divider();
1.102 + uint8_t get_pclock_divider();
1.103 + uint8_t get_lcd_pixel_divider(uint8_t controller = 0);
1.104 + uint8_t get_memory_divider();
1.105 +
1.106 + // Input frequencies.
1.107 +
1.108 + uint8_t get_main_source();
1.109 + uint32_t get_main_frequency();
1.110 +
1.111 + // Clock sources, providing the input frequency.
1.112 +
1.113 + uint8_t get_cpu_source();
1.114 + uint8_t get_hclock0_source();
1.115 + uint8_t get_hclock2_source();
1.116 + uint8_t get_lcd_source(uint8_t controller);
1.117 + uint8_t get_lcd_source() { return get_lcd_source(0); }
1.118 + uint8_t get_memory_source();
1.119 + uint8_t get_pclock_source();
1.120 +
1.121 + uint32_t get_cpu_source_frequency();
1.122 + uint32_t get_hclock0_source_frequency();
1.123 + uint32_t get_hclock2_source_frequency();
1.124 + uint32_t get_lcd_source_frequency(uint8_t controller);
1.125 + uint32_t get_lcd_source_frequency() { return get_lcd_source_frequency(0); }
1.126 + uint32_t get_memory_source_frequency();
1.127 + uint32_t get_pclock_source_frequency();
1.128 +
1.129 + // Final, calculated frequencies.
1.130 +
1.131 + uint32_t get_cpu_frequency();
1.132 + uint32_t get_hclock0_frequency();
1.133 + uint32_t get_hclock2_frequency();
1.134 + uint32_t get_memory_frequency();
1.135 + uint32_t get_pclock_frequency();
1.136 +
1.137 + uint32_t get_apll_frequency();
1.138 + uint32_t get_epll_frequency();
1.139 + uint32_t get_mpll_frequency();
1.140 +
1.141 + void set_pll_parameters(uint32_t pll_reg, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider);
1.142 +
1.143 + uint32_t get_frequency(enum Clock_identifiers clock);
1.144 + void set_frequency(enum Clock_identifiers clock, uint32_t frequency);
1.145 +};
1.146 +
1.147 +#endif /* __cplusplus */
1.148 +
1.149 +
1.150 +
1.151 +/* C language interface. */
1.152 +
1.153 +EXTERN_C_BEGIN
1.154 +
1.155 +void *x1600_cpm_init(l4_addr_t cpm_base);
1.156 +
1.157 +int x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock);
1.158 +void x1600_cpm_start_clock(void *cpm, enum Clock_identifiers clock);
1.159 +void x1600_cpm_stop_clock(void *cpm, enum Clock_identifiers clock);
1.160 +
1.161 +uint8_t x1600_cpm_get_cpu_divider(void *cpm);
1.162 +uint8_t x1600_cpm_get_hclock0_divider(void *cpm);
1.163 +uint8_t x1600_cpm_get_hclock2_divider(void *cpm);
1.164 +uint8_t x1600_cpm_get_lcd_pixel_divider(void *cpm);
1.165 +uint8_t x1600_cpm_get_memory_divider(void *cpm);
1.166 +uint8_t x1600_cpm_get_pclock_divider(void *cpm);
1.167 +
1.168 +uint8_t x1600_cpm_get_hclock0_source(void *cpm);
1.169 +uint8_t x1600_cpm_get_hclock2_source(void *cpm);
1.170 +uint8_t x1600_cpm_get_lcd_source(void *cpm);
1.171 +uint8_t x1600_cpm_get_memory_source(void *cpm);
1.172 +uint8_t x1600_cpm_get_pclock_source(void *cpm);
1.173 +
1.174 +uint32_t x1600_cpm_get_hclock0_source_frequency(void *cpm);
1.175 +uint32_t x1600_cpm_get_hclock2_source_frequency(void *cpm);
1.176 +uint32_t x1600_cpm_get_lcd_source_frequency(void *cpm);
1.177 +uint32_t x1600_cpm_get_memory_source_frequency(void *cpm);
1.178 +uint32_t x1600_cpm_get_pclock_source_frequency(void *cpm);
1.179 +
1.180 +void x1600_cpm_set_pclock_source(void *cpm, uint8_t source);
1.181 +
1.182 +uint8_t x1600_cpm_get_main_source(void *cpm);
1.183 +uint32_t x1600_cpm_get_main_frequency(void *cpm);
1.184 +
1.185 +uint32_t x1600_cpm_get_cpu_frequency(void *cpm);
1.186 +uint32_t x1600_cpm_get_hclock0_frequency(void *cpm);
1.187 +uint32_t x1600_cpm_get_hclock2_frequency(void *cpm);
1.188 +uint32_t x1600_cpm_get_memory_frequency(void *cpm);
1.189 +uint32_t x1600_cpm_get_pclock_frequency(void *cpm);
1.190 +
1.191 +uint32_t x1600_cpm_get_apll_frequency(void *cpm);
1.192 +uint32_t x1600_cpm_get_epll_frequency(void *cpm);
1.193 +uint32_t x1600_cpm_get_mpll_frequency(void *cpm);
1.194 +
1.195 +uint32_t x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock);
1.196 +void x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency);
1.197 +
1.198 +void x1600_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider);
1.199 +
1.200 +EXTERN_C_END