1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pkg/devices/lib/lcd/include/lcd-jz4740-regs.h Sat Jun 06 01:22:18 2020 +0200
1.3 @@ -0,0 +1,301 @@
1.4 +/*
1.5 + * LCD peripheral support for the JZ4740 and related SoCs.
1.6 + *
1.7 + * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.8 + * Copyright (C) 2015, 2016, 2017, 2018,
1.9 + * 2020 Paul Boddie <paul@boddie.org.uk>
1.10 + *
1.11 + * This program is free software; you can redistribute it and/or
1.12 + * modify it under the terms of the GNU General Public License as
1.13 + * published by the Free Software Foundation; either version 2 of
1.14 + * the License, or (at your option) any later version.
1.15 + *
1.16 + * This program is distributed in the hope that it will be useful,
1.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.19 + * GNU General Public License for more details.
1.20 + *
1.21 + * You should have received a copy of the GNU General Public License
1.22 + * along with this program; if not, write to the Free Software
1.23 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.24 + * Boston, MA 02110-1301, USA
1.25 + */
1.26 +
1.27 +#pragma once
1.28 +
1.29 +
1.30 +
1.31 +enum Regs : unsigned
1.32 +{
1.33 + Lcd_config = 0x000, // LCD_CFG
1.34 + Lcd_vsync = 0x004, // LCD_VSYNC
1.35 + Lcd_hsync = 0x008, // LCD_HSYNC
1.36 + Virtual_area = 0x00c, // LCD_VAT
1.37 + Display_hlimits = 0x010, // LCD_DAH
1.38 + Display_vlimits = 0x014, // LCD_DAV
1.39 + Lcd_ps = 0x018, // LCD_PS
1.40 + Lcd_cls = 0x01c, // LCD_CLS
1.41 + Lcd_spl = 0x020, // LCD_SPL
1.42 + Lcd_rev = 0x024, // LCD_REV
1.43 + Lcd_control = 0x030, // LCD_CTRL
1.44 + Lcd_status = 0x034, // LCD_STATE
1.45 + Lcd_irq_id = 0x038, // LCD_IID
1.46 + Desc_address_0 = 0x040, // LCD_DA0
1.47 + Source_address_0 = 0x044, // LCD_SA0
1.48 + Frame_id_0 = 0x048, // LCD_FID0
1.49 + Command_0 = 0x04c, // LCD_CMD0
1.50 + Counter_position_0 = 0x068, // LCD_CPOS0
1.51 + Foreground_size_0 = 0x06c, // LCD_DESSIZE0
1.52 + Desc_address_1 = 0x050, // LCD_DA1
1.53 + Source_address_1 = 0x054, // LCD_SA1
1.54 + Frame_id_1 = 0x058, // LCD_FID1
1.55 + Command_1 = 0x05c, // LCD_CMD1
1.56 + Counter_position_1 = 0x078, // LCD_CPOS1
1.57 + Foreground_size_1 = 0x07c, // LCD_DESSIZE1
1.58 + Rgb_control = 0x090, // LCD_RGBC (JZ4780)
1.59 + Alpha_levels = 0x108, // LCD_ALPHA (JZ4780)
1.60 + Priority_level = 0x2c0, // LCD_PCFG
1.61 +
1.62 + // OSD registers.
1.63 +
1.64 + Osd_config = 0x100, // LCD_OSDC
1.65 + Osd_control = 0x104, // LCD_OSDCTRL
1.66 + Osd_status = 0x108, // LCD_OSDS
1.67 +};
1.68 +
1.69 +// Lcd_config descriptions.
1.70 +
1.71 +enum Config_values : unsigned
1.72 +{
1.73 + Config_stn_pins_mask = 0x3,
1.74 + Config_mode_mask = 0xf,
1.75 +};
1.76 +
1.77 +// Field positions for registers employing two values, with the first typically
1.78 +// being the start value and the second being an end value.
1.79 +
1.80 +enum Value_pair_bits : unsigned
1.81 +{
1.82 + Value_first = 16,
1.83 + Value_second = 0,
1.84 +};
1.85 +
1.86 +// Virtual area bits.
1.87 +
1.88 +enum Virtual_area_values : unsigned
1.89 +{
1.90 + Virtual_area_horizontal_size = Value_first, // sum of display and blank regions (dot/pixel clock periods)
1.91 + Virtual_area_vertical_size = Value_second, // sum of display and blank regions (line periods)
1.92 +};
1.93 +
1.94 +// Lcd_control descriptions.
1.95 +
1.96 +enum Control_bits : unsigned
1.97 +{
1.98 + Control_pin_modify = 31, // PINMD (change pin usage from 15..0 to 17..10, 8..1)
1.99 + Control_burst_length = 28, // BST (burst length selection)
1.100 + Control_rgb_mode = 27, // RGB (RGB mode)
1.101 + Control_out_underrun = 26, // OFUP (output FIFO underrun protection)
1.102 + Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection)
1.103 + Control_palette_delay = 16, // PDD (load palette delay counter)
1.104 + Control_dac_loopback_test = 14, // DACTE (DAC loopback test)
1.105 + Control_frame_end_irq_enable = 13, // EOFM (end of frame interrupt enable)
1.106 + Control_frame_start_irq_enable = 12, // SOFM (start of frame interrupt enable)
1.107 + Control_out_underrun_irq_enable = 11, // OFUM (output FIFO underrun interrupt enable)
1.108 + Control_in0_underrun_irq_enable = 10, // IFUM0 (input FIFO 0 underrun interrupt enable)
1.109 + Control_in1_underrun_irq_enable = 9, // IFUM1 (input FIFO 1 underrun interrupt enable)
1.110 + Control_disabled_irq_enable = 8, // LDDM (LCD disable done interrupt enable)
1.111 + Control_quick_disabled_irq_enable = 7, // QDM (LCD quick disable done interrupt enable)
1.112 + Control_endian_select = 6, // BEDN (endian selection)
1.113 + Control_bit_order = 5, // PEDN (bit order in bytes)
1.114 + Control_disable = 4, // DIS (disable controller)
1.115 + Control_enable = 3, // ENA (enable controller)
1.116 + Control_bpp = 0, // BPP (bits per pixel)
1.117 +};
1.118 +
1.119 +enum Burst_length_values : unsigned
1.120 +{
1.121 + Burst_length_4 = 0, // 4 word
1.122 + Burst_length_8 = 1, // 8 word
1.123 + Burst_length_16 = 2, // 16 word
1.124 +
1.125 + // JZ4780 extensions.
1.126 +
1.127 + Burst_length_32 = 3, // 32 word
1.128 + Burst_length_64 = 4, // 64 word
1.129 + Burst_length_mask = 0x7,
1.130 +};
1.131 +
1.132 +enum Rgb_mode_values : unsigned
1.133 +{
1.134 + Rgb_mode_565 = 0,
1.135 + Rgb_mode_555 = 1,
1.136 + Rgb_mode_mask = 0x1,
1.137 +};
1.138 +
1.139 +enum Frc_algorithm_values : unsigned
1.140 +{
1.141 + Frc_greyscales_16 = 0,
1.142 + Frc_greyscales_4 = 1,
1.143 + Frc_greyscales_2 = 2,
1.144 + Frc_greyscales_mask = 0x3,
1.145 +};
1.146 +
1.147 +enum Control_bpp_values : unsigned
1.148 +{
1.149 + Control_bpp_1bpp = 0,
1.150 + Control_bpp_2bpp = 1,
1.151 + Control_bpp_4bpp = 2,
1.152 + Control_bpp_8bpp = 3,
1.153 + Control_bpp_15bpp = 4,
1.154 + Control_bpp_16bpp = 4,
1.155 + Control_bpp_18bpp = 5,
1.156 + Control_bpp_24bpp = 5,
1.157 + Control_bpp_24bpp_comp = 6,
1.158 + Control_bpp_30bpp = 7,
1.159 + Control_bpp_32bpp = 7,
1.160 + Control_bpp_mask = 0x7,
1.161 +};
1.162 +
1.163 +// Command descriptions.
1.164 +
1.165 +enum Command_bits : unsigned
1.166 +{
1.167 + Command_frame_start_irq = 31, // SOFINT (start of frame interrupt)
1.168 + Command_frame_end_irq = 30, // EOFINT (end of frame interrupt)
1.169 + Command_lcm_command = 29, // JZ4780: CMD (LCM command/data via DMA0)
1.170 + Command_palette_buffer = 28, // PAL (descriptor references palette, not display data)
1.171 + Command_frame_compressed = 27, // JZ4780: COMPEN (16/24bpp compression enabled)
1.172 + Command_frame_enable = 26, // JZ4780: FRM_EN
1.173 + Command_field_even = 25, // JZ4780: FIELD_SEL (interlace even field)
1.174 + Command_16x16_block = 24, // JZ4780: 16x16BLOCK (fetch data by 16x16 block)
1.175 + Command_buffer_length = 0, // LEN
1.176 +};
1.177 +
1.178 +enum Command_values : unsigned
1.179 +{
1.180 + Command_buffer_length_mask = 0x00ffffff,
1.181 +};
1.182 +
1.183 +// Status descriptions.
1.184 +
1.185 +enum Status_bits : unsigned
1.186 +{
1.187 + Status_frame_end_irq = 5,
1.188 + Status_frame_start_irq = 4,
1.189 + Status_out_underrun_irq = 3,
1.190 + Status_in0_underrun_irq = 2,
1.191 + Status_in1_underrun_irq = 1,
1.192 + Status_disabled = 0,
1.193 +};
1.194 +
1.195 +// OSD configuration bits (JZ4780).
1.196 +
1.197 +enum Osd_config_bits : unsigned
1.198 +{
1.199 + Osd_config_fg1_pixel_alpha_enable = 17,
1.200 + Osd_config_fg1_frame_start_irq_enable = 15,
1.201 + Osd_config_fg1_frame_end_irq_enable = 14,
1.202 + Osd_config_fg0_frame_start_irq_enable = 11,
1.203 + Osd_config_fg0_frame_end_irq_enable = 10,
1.204 + Osd_config_fg1_enable = 4,
1.205 + Osd_config_fg0_enable = 3,
1.206 + Osd_config_alpha_enable = 2,
1.207 + Osd_config_fg0_pixel_alpha_enable = 1,
1.208 + Osd_config_enable = 0,
1.209 +};
1.210 +
1.211 +enum Osd_control_bits : unsigned
1.212 +{
1.213 + Osd_control_ipu_clock_enable = 15,
1.214 +};
1.215 +
1.216 +// RGB control (JZ4780).
1.217 +
1.218 +enum Rgb_control_bits : unsigned
1.219 +{
1.220 + Rgb_data_padded = 15, // RGBDM
1.221 + Rgb_padding_mode = 14, // DMM
1.222 + Rgb_422 = 8, // 422
1.223 + Rgb_format_enable = 7, // RGBFMT
1.224 + Rgb_odd_line = 4, // OddRGB
1.225 + Rgb_even_line = 0, // EvenRGB
1.226 +};
1.227 +
1.228 +enum Rgb_control_values : unsigned
1.229 +{
1.230 + Rgb_padding_end = 0U << Rgb_padding_mode,
1.231 + Rgb_padding_start = 1U << Rgb_padding_mode,
1.232 + Rgb_odd_line_rgb = 0U << Rgb_odd_line,
1.233 + Rgb_odd_line_rbg = 1U << Rgb_odd_line,
1.234 + Rgb_odd_line_grb = 2U << Rgb_odd_line,
1.235 + Rgb_odd_line_gbr = 3U << Rgb_odd_line,
1.236 + Rgb_odd_line_brg = 4U << Rgb_odd_line,
1.237 + Rgb_odd_line_bgr = 5U << Rgb_odd_line,
1.238 + Rgb_even_line_rgb = 0U << Rgb_even_line,
1.239 + Rgb_even_line_rbg = 1U << Rgb_even_line,
1.240 + Rgb_even_line_grb = 2U << Rgb_even_line,
1.241 + Rgb_even_line_gbr = 3U << Rgb_even_line,
1.242 + Rgb_even_line_brg = 4U << Rgb_even_line,
1.243 + Rgb_even_line_bgr = 5U << Rgb_even_line,
1.244 +};
1.245 +
1.246 +// Alpha levels (JZ4780).
1.247 +
1.248 +enum Alpha_levels_bits : unsigned
1.249 +{
1.250 + Alpha_level_fg1 = 8,
1.251 + Alpha_level_fg0 = 0,
1.252 +};
1.253 +
1.254 +enum Alpha_levels_values : unsigned
1.255 +{
1.256 + Alpha_level_fg1_mask = 0x0000ff00,
1.257 + Alpha_level_fg0_mask = 0x000000ff,
1.258 +};
1.259 +
1.260 +// Priority level.
1.261 +
1.262 +enum Priority_level_bits : unsigned
1.263 +{
1.264 + Priority_mode = 31,
1.265 + Priority_highest_burst = 28,
1.266 + Priority_threshold2 = 18,
1.267 + Priority_threshold1 = 9,
1.268 + Priority_threshold0 = 0,
1.269 +};
1.270 +
1.271 +enum Priority_level_values : unsigned
1.272 +{
1.273 + Priority_mode_dynamic = 0U << Priority_mode,
1.274 + Priority_mode_arbiter = 1U << Priority_mode,
1.275 +};
1.276 +
1.277 +enum Priority_burst_values : unsigned
1.278 +{
1.279 + Priority_burst_4 = 0,
1.280 + Priority_burst_8 = 1,
1.281 + Priority_burst_16 = 2,
1.282 + Priority_burst_32 = 3,
1.283 + Priority_burst_64 = 4,
1.284 + Priority_burst_16_cont = 5,
1.285 + Priority_burst_disable = 7,
1.286 +};
1.287 +
1.288 +// Position descriptor member.
1.289 +
1.290 +enum Position_bits : unsigned
1.291 +{
1.292 + Position_bpp = 27,
1.293 + Position_premultiply_lcd = 26,
1.294 + Position_coefficient = 24,
1.295 + Position_y_position = 12,
1.296 + Position_x_position = 0,
1.297 +};
1.298 +
1.299 +enum Position_values : unsigned
1.300 +{
1.301 + Position_bpp_15_16bpp = 4,
1.302 + Position_bpp_18_24bpp = 5,
1.303 + Position_bpp_30bpp = 7,
1.304 +};