1.1 --- a/pkg/devices/lib/lcd/src/jz4740/lcd-jz4740.cc Sat Jun 06 00:04:50 2020 +0200
1.2 +++ b/pkg/devices/lib/lcd/src/jz4740/lcd-jz4740.cc Sat Jun 06 01:22:18 2020 +0200
1.3 @@ -29,284 +29,10 @@
1.4
1.5 #include "lcd-jz4740.h"
1.6 #include "lcd-jz4740-config.h"
1.7 +#include "lcd-jz4740-regs.h"
1.8
1.9 #include <stdint.h>
1.10
1.11 -enum Regs : unsigned
1.12 -{
1.13 - Lcd_config = 0x000, // LCD_CFG
1.14 - Lcd_vsync = 0x004, // LCD_VSYNC
1.15 - Lcd_hsync = 0x008, // LCD_HSYNC
1.16 - Virtual_area = 0x00c, // LCD_VAT
1.17 - Display_hlimits = 0x010, // LCD_DAH
1.18 - Display_vlimits = 0x014, // LCD_DAV
1.19 - Lcd_ps = 0x018, // LCD_PS
1.20 - Lcd_cls = 0x01c, // LCD_CLS
1.21 - Lcd_spl = 0x020, // LCD_SPL
1.22 - Lcd_rev = 0x024, // LCD_REV
1.23 - Lcd_control = 0x030, // LCD_CTRL
1.24 - Lcd_status = 0x034, // LCD_STATE
1.25 - Lcd_irq_id = 0x038, // LCD_IID
1.26 - Desc_address_0 = 0x040, // LCD_DA0
1.27 - Source_address_0 = 0x044, // LCD_SA0
1.28 - Frame_id_0 = 0x048, // LCD_FID0
1.29 - Command_0 = 0x04c, // LCD_CMD0
1.30 - Counter_position_0 = 0x068, // LCD_CPOS0
1.31 - Foreground_size_0 = 0x06c, // LCD_DESSIZE0
1.32 - Desc_address_1 = 0x050, // LCD_DA1
1.33 - Source_address_1 = 0x054, // LCD_SA1
1.34 - Frame_id_1 = 0x058, // LCD_FID1
1.35 - Command_1 = 0x05c, // LCD_CMD1
1.36 - Counter_position_1 = 0x078, // LCD_CPOS1
1.37 - Foreground_size_1 = 0x07c, // LCD_DESSIZE1
1.38 - Rgb_control = 0x090, // LCD_RGBC (JZ4780)
1.39 - Alpha_levels = 0x108, // LCD_ALPHA (JZ4780)
1.40 - Priority_level = 0x2c0, // LCD_PCFG
1.41 -
1.42 - // OSD registers.
1.43 -
1.44 - Osd_config = 0x100, // LCD_OSDC
1.45 - Osd_control = 0x104, // LCD_OSDCTRL
1.46 - Osd_status = 0x108, // LCD_OSDS
1.47 -};
1.48 -
1.49 -// Lcd_config descriptions.
1.50 -
1.51 -enum Config_values : unsigned
1.52 -{
1.53 - Config_stn_pins_mask = 0x3,
1.54 - Config_mode_mask = 0xf,
1.55 -};
1.56 -
1.57 -// Field positions for registers employing two values, with the first typically
1.58 -// being the start value and the second being an end value.
1.59 -
1.60 -enum Value_pair_bits : unsigned
1.61 -{
1.62 - Value_first = 16,
1.63 - Value_second = 0,
1.64 -};
1.65 -
1.66 -// Virtual area bits.
1.67 -
1.68 -enum Virtual_area_values : unsigned
1.69 -{
1.70 - Virtual_area_horizontal_size = Value_first, // sum of display and blank regions (dot/pixel clock periods)
1.71 - Virtual_area_vertical_size = Value_second, // sum of display and blank regions (line periods)
1.72 -};
1.73 -
1.74 -// Lcd_control descriptions.
1.75 -
1.76 -enum Control_bits : unsigned
1.77 -{
1.78 - Control_pin_modify = 31, // PINMD (change pin usage from 15..0 to 17..10, 8..1)
1.79 - Control_burst_length = 28, // BST (burst length selection)
1.80 - Control_rgb_mode = 27, // RGB (RGB mode)
1.81 - Control_out_underrun = 26, // OFUP (output FIFO underrun protection)
1.82 - Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection)
1.83 - Control_palette_delay = 16, // PDD (load palette delay counter)
1.84 - Control_dac_loopback_test = 14, // DACTE (DAC loopback test)
1.85 - Control_frame_end_irq_enable = 13, // EOFM (end of frame interrupt enable)
1.86 - Control_frame_start_irq_enable = 12, // SOFM (start of frame interrupt enable)
1.87 - Control_out_underrun_irq_enable = 11, // OFUM (output FIFO underrun interrupt enable)
1.88 - Control_in0_underrun_irq_enable = 10, // IFUM0 (input FIFO 0 underrun interrupt enable)
1.89 - Control_in1_underrun_irq_enable = 9, // IFUM1 (input FIFO 1 underrun interrupt enable)
1.90 - Control_disabled_irq_enable = 8, // LDDM (LCD disable done interrupt enable)
1.91 - Control_quick_disabled_irq_enable = 7, // QDM (LCD quick disable done interrupt enable)
1.92 - Control_endian_select = 6, // BEDN (endian selection)
1.93 - Control_bit_order = 5, // PEDN (bit order in bytes)
1.94 - Control_disable = 4, // DIS (disable controller)
1.95 - Control_enable = 3, // ENA (enable controller)
1.96 - Control_bpp = 0, // BPP (bits per pixel)
1.97 -};
1.98 -
1.99 -enum Burst_length_values : unsigned
1.100 -{
1.101 - Burst_length_4 = 0, // 4 word
1.102 - Burst_length_8 = 1, // 8 word
1.103 - Burst_length_16 = 2, // 16 word
1.104 -
1.105 - // JZ4780 extensions.
1.106 -
1.107 - Burst_length_32 = 3, // 32 word
1.108 - Burst_length_64 = 4, // 64 word
1.109 - Burst_length_mask = 0x7,
1.110 -};
1.111 -
1.112 -enum Rgb_mode_values : unsigned
1.113 -{
1.114 - Rgb_mode_565 = 0,
1.115 - Rgb_mode_555 = 1,
1.116 - Rgb_mode_mask = 0x1,
1.117 -};
1.118 -
1.119 -enum Frc_algorithm_values : unsigned
1.120 -{
1.121 - Frc_greyscales_16 = 0,
1.122 - Frc_greyscales_4 = 1,
1.123 - Frc_greyscales_2 = 2,
1.124 - Frc_greyscales_mask = 0x3,
1.125 -};
1.126 -
1.127 -enum Control_bpp_values : unsigned
1.128 -{
1.129 - Control_bpp_1bpp = 0,
1.130 - Control_bpp_2bpp = 1,
1.131 - Control_bpp_4bpp = 2,
1.132 - Control_bpp_8bpp = 3,
1.133 - Control_bpp_15bpp = 4,
1.134 - Control_bpp_16bpp = 4,
1.135 - Control_bpp_18bpp = 5,
1.136 - Control_bpp_24bpp = 5,
1.137 - Control_bpp_24bpp_comp = 6,
1.138 - Control_bpp_30bpp = 7,
1.139 - Control_bpp_32bpp = 7,
1.140 - Control_bpp_mask = 0x7,
1.141 -};
1.142 -
1.143 -// Command descriptions.
1.144 -
1.145 -enum Command_bits : unsigned
1.146 -{
1.147 - Command_frame_start_irq = 31, // SOFINT (start of frame interrupt)
1.148 - Command_frame_end_irq = 30, // EOFINT (end of frame interrupt)
1.149 - Command_lcm_command = 29, // JZ4780: CMD (LCM command/data via DMA0)
1.150 - Command_palette_buffer = 28, // PAL (descriptor references palette, not display data)
1.151 - Command_frame_compressed = 27, // JZ4780: COMPEN (16/24bpp compression enabled)
1.152 - Command_frame_enable = 26, // JZ4780: FRM_EN
1.153 - Command_field_even = 25, // JZ4780: FIELD_SEL (interlace even field)
1.154 - Command_16x16_block = 24, // JZ4780: 16x16BLOCK (fetch data by 16x16 block)
1.155 - Command_buffer_length = 0, // LEN
1.156 -};
1.157 -
1.158 -enum Command_values : unsigned
1.159 -{
1.160 - Command_buffer_length_mask = 0x00ffffff,
1.161 -};
1.162 -
1.163 -// Status descriptions.
1.164 -
1.165 -enum Status_bits : unsigned
1.166 -{
1.167 - Status_frame_end_irq = 5,
1.168 - Status_frame_start_irq = 4,
1.169 - Status_out_underrun_irq = 3,
1.170 - Status_in0_underrun_irq = 2,
1.171 - Status_in1_underrun_irq = 1,
1.172 - Status_disabled = 0,
1.173 -};
1.174 -
1.175 -// OSD configuration bits (JZ4780).
1.176 -
1.177 -enum Osd_config_bits : unsigned
1.178 -{
1.179 - Osd_config_fg1_pixel_alpha_enable = 17,
1.180 - Osd_config_fg1_frame_start_irq_enable = 15,
1.181 - Osd_config_fg1_frame_end_irq_enable = 14,
1.182 - Osd_config_fg0_frame_start_irq_enable = 11,
1.183 - Osd_config_fg0_frame_end_irq_enable = 10,
1.184 - Osd_config_fg1_enable = 4,
1.185 - Osd_config_fg0_enable = 3,
1.186 - Osd_config_alpha_enable = 2,
1.187 - Osd_config_fg0_pixel_alpha_enable = 1,
1.188 - Osd_config_enable = 0,
1.189 -};
1.190 -
1.191 -enum Osd_control_bits : unsigned
1.192 -{
1.193 - Osd_control_ipu_clock_enable = 15,
1.194 -};
1.195 -
1.196 -// RGB control (JZ4780).
1.197 -
1.198 -enum Rgb_control_bits : unsigned
1.199 -{
1.200 - Rgb_data_padded = 15, // RGBDM
1.201 - Rgb_padding_mode = 14, // DMM
1.202 - Rgb_422 = 8, // 422
1.203 - Rgb_format_enable = 7, // RGBFMT
1.204 - Rgb_odd_line = 4, // OddRGB
1.205 - Rgb_even_line = 0, // EvenRGB
1.206 -};
1.207 -
1.208 -enum Rgb_control_values : unsigned
1.209 -{
1.210 - Rgb_padding_end = 0U << Rgb_padding_mode,
1.211 - Rgb_padding_start = 1U << Rgb_padding_mode,
1.212 - Rgb_odd_line_rgb = 0U << Rgb_odd_line,
1.213 - Rgb_odd_line_rbg = 1U << Rgb_odd_line,
1.214 - Rgb_odd_line_grb = 2U << Rgb_odd_line,
1.215 - Rgb_odd_line_gbr = 3U << Rgb_odd_line,
1.216 - Rgb_odd_line_brg = 4U << Rgb_odd_line,
1.217 - Rgb_odd_line_bgr = 5U << Rgb_odd_line,
1.218 - Rgb_even_line_rgb = 0U << Rgb_even_line,
1.219 - Rgb_even_line_rbg = 1U << Rgb_even_line,
1.220 - Rgb_even_line_grb = 2U << Rgb_even_line,
1.221 - Rgb_even_line_gbr = 3U << Rgb_even_line,
1.222 - Rgb_even_line_brg = 4U << Rgb_even_line,
1.223 - Rgb_even_line_bgr = 5U << Rgb_even_line,
1.224 -};
1.225 -
1.226 -// Alpha levels (JZ4780).
1.227 -
1.228 -enum Alpha_levels_bits : unsigned
1.229 -{
1.230 - Alpha_level_fg1 = 8,
1.231 - Alpha_level_fg0 = 0,
1.232 -};
1.233 -
1.234 -enum Alpha_levels_values : unsigned
1.235 -{
1.236 - Alpha_level_fg1_mask = 0x0000ff00,
1.237 - Alpha_level_fg0_mask = 0x000000ff,
1.238 -};
1.239 -
1.240 -// Priority level.
1.241 -
1.242 -enum Priority_level_bits : unsigned
1.243 -{
1.244 - Priority_mode = 31,
1.245 - Priority_highest_burst = 28,
1.246 - Priority_threshold2 = 18,
1.247 - Priority_threshold1 = 9,
1.248 - Priority_threshold0 = 0,
1.249 -};
1.250 -
1.251 -enum Priority_level_values : unsigned
1.252 -{
1.253 - Priority_mode_dynamic = 0U << Priority_mode,
1.254 - Priority_mode_arbiter = 1U << Priority_mode,
1.255 -};
1.256 -
1.257 -enum Priority_burst_values : unsigned
1.258 -{
1.259 - Priority_burst_4 = 0,
1.260 - Priority_burst_8 = 1,
1.261 - Priority_burst_16 = 2,
1.262 - Priority_burst_32 = 3,
1.263 - Priority_burst_64 = 4,
1.264 - Priority_burst_16_cont = 5,
1.265 - Priority_burst_disable = 7,
1.266 -};
1.267 -
1.268 -// Position descriptor member.
1.269 -
1.270 -enum Position_bits : unsigned
1.271 -{
1.272 - Position_bpp = 27,
1.273 - Position_premultiply_lcd = 26,
1.274 - Position_coefficient = 24,
1.275 - Position_y_position = 12,
1.276 - Position_x_position = 0,
1.277 -};
1.278 -
1.279 -enum Position_values : unsigned
1.280 -{
1.281 - Position_bpp_15_16bpp = 4,
1.282 - Position_bpp_18_24bpp = 5,
1.283 - Position_bpp_30bpp = 7,
1.284 -};
1.285 -
1.286
1.287
1.288 // Utility functions.
1.289 @@ -348,8 +74,7 @@
1.290 : _panel(panel)
1.291 {
1.292 _regs = new Hw::Mmio_register_block<32>(addr);
1.293 - _burst_size = 64; // 64-word burst size (JZ4780)
1.294 - //_burst_size = 16; // 16-word burst size
1.295 + _burst_size = 16; // 16-word burst size
1.296 }
1.297
1.298 struct Jz4740_lcd_panel *
1.299 @@ -644,25 +369,6 @@
1.300 }
1.301 }
1.302
1.303 -// Return colour depth control value.
1.304 -// JZ4780 position details only.
1.305 -
1.306 -uint32_t
1.307 -Lcd_jz4740_chip::_position_bpp()
1.308 -{
1.309 - uint32_t value;
1.310 -
1.311 - switch (_panel->bpp)
1.312 - {
1.313 - case 15: case 16: value = Position_bpp_15_16bpp; break;
1.314 - case 18: case 24: value = Position_bpp_18_24bpp; break;
1.315 - case 30: value = Position_bpp_30bpp; break;
1.316 - default: value = 0; break;
1.317 - }
1.318 -
1.319 - return value << Position_bpp;
1.320 -}
1.321 -
1.322 // Return a panel-related control value.
1.323
1.324 uint32_t
1.325 @@ -742,28 +448,6 @@
1.326 ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Status_frame_end_irq) : 0);
1.327 }
1.328
1.329 -uint32_t
1.330 -Lcd_jz4740_chip::_priority_transfer()
1.331 -{
1.332 - uint32_t length;
1.333 -
1.334 - switch (_burst_size)
1.335 - {
1.336 - case 4: length = Priority_burst_4; break;
1.337 - case 8: length = Priority_burst_8; break;
1.338 - case 32: length = Priority_burst_32; break;
1.339 - case 64: length = Priority_burst_64; break;
1.340 - case 16:
1.341 - default: length = Priority_burst_16; break;
1.342 - }
1.343 -
1.344 - return Priority_mode_arbiter |
1.345 - (length << Priority_highest_burst) |
1.346 - (511U << Priority_threshold2) |
1.347 - (400U << Priority_threshold1) |
1.348 - (256U << Priority_threshold0);
1.349 -}
1.350 -
1.351 // STN panel-specific initialisation.
1.352
1.353 void
1.354 @@ -861,32 +545,17 @@
1.355 Lcd_jz4740_chip::_set_descriptor(struct Jz4740_lcd_descriptor &desc,
1.356 l4_addr_t source, l4_size_t size,
1.357 struct Jz4740_lcd_descriptor *next,
1.358 - uint32_t flags,
1.359 - bool frame_enable)
1.360 + uint32_t flags)
1.361 {
1.362 // In the command, indicate the number of words from the source for transfer.
1.363
1.364 desc.next = next;
1.365 - desc.source = frame_enable ? source : 0;
1.366 + desc.source = source;
1.367 desc.identifier = source;
1.368 desc.command = ((size / sizeof(uint32_t)) & Command_buffer_length_mask) |
1.369 - (frame_enable ? (1U << Command_frame_enable) : 0) |
1.370 flags;
1.371 -
1.372 - // Initialise "new" descriptor fields.
1.373 -
1.374 - desc.offset = 0;
1.375 - desc.page_width = 0;
1.376 - desc.command_position = (1U << Position_premultiply_lcd) |
1.377 - ((frame_enable ? 1U : 3U) << Position_coefficient) |
1.378 - _position_bpp();
1.379 - desc.fg_size = 0xff000000 |
1.380 - ((_panel->height - 1) << 12) |
1.381 - ((_panel->width - 1) << 0);
1.382 }
1.383
1.384 -
1.385 -
1.386 // Initialise the LCD controller with the memory, panel and framebuffer details.
1.387 // Any palette must be initialised separately using get_palette and init_palette.
1.388
1.389 @@ -895,13 +564,8 @@
1.390 struct Jz4740_lcd_descriptor *desc_paddr,
1.391 l4_addr_t fb_paddr)
1.392 {
1.393 - // NOTE: Remarks in the Ingenic Linux 3.0.8 driver suggest that the JZ4775 and
1.394 - // NOTE: JZ4780 do not support palettes.
1.395 -
1.396 int have_palette = (_panel->bpp <= 8);
1.397
1.398 - bool _have_fg1 = true; // NOTE: To be formalised!
1.399 -
1.400 // Provide the first framebuffer descriptor in single and dual modes.
1.401 // Flip back and forth between any palette and the framebuffer.
1.402
1.403 @@ -913,12 +577,11 @@
1.404 // Provide the second framebuffer descriptor only in dual-panel mode.
1.405 // Only employ this descriptor in the second DMA channel.
1.406
1.407 - if ((get_panels() == 2) || _have_fg1)
1.408 + if (get_panels() == 2)
1.409 _set_descriptor(desc_vaddr[1], get_framebuffer(1, fb_paddr),
1.410 get_aligned_size(),
1.411 desc_paddr + 1,
1.412 - _command_irq(),
1.413 - false);
1.414 + _command_irq());
1.415
1.416 // Initialise palette descriptor details for lower colour depths.
1.417
1.418 @@ -941,7 +604,7 @@
1.419
1.420 // Provide a descriptor for the second DMA channel in dual-panel mode.
1.421
1.422 - if ((get_panels() == 2) || _have_fg1)
1.423 + if (get_panels() == 2)
1.424 _regs[Desc_address_1] = (uint32_t) (desc_paddr + 1);
1.425
1.426 // Initialise panel-related registers.
1.427 @@ -949,19 +612,9 @@
1.428 _init_panel();
1.429
1.430 // Initialise the control and configuration registers.
1.431 - // NOTE: JZ4780 does not support bpp setting here.
1.432
1.433 _regs[Lcd_control] = _control_panel() | _control_bpp() | _control_transfer() | _control_irq();
1.434 _regs[Lcd_config] = _panel->config;
1.435 -
1.436 - // NOTE: JZ4780 only.
1.437 -
1.438 - _regs[Rgb_control] = (1U << Rgb_format_enable) | Rgb_odd_line_rgb | Rgb_even_line_rgb;
1.439 - _regs[Priority_level] = _priority_transfer();
1.440 - _regs[Osd_config] = (1U << Osd_config_enable) |
1.441 - (1U << Osd_config_alpha_enable);
1.442 - _regs[Alpha_levels] = ((255U << Alpha_level_fg1) & Alpha_level_fg1_mask) |
1.443 - ((255U << Alpha_level_fg0) & Alpha_level_fg0_mask);
1.444 }
1.445
1.446 // Set the interrupt for controller-related events.