1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pkg/devices/lib/dma/include/dma-jz4780.h Sun Oct 29 16:14:38 2023 +0100
1.3 @@ -0,0 +1,191 @@
1.4 +/*
1.5 + * DMA support for the JZ4780.
1.6 + *
1.7 + * Copyright (C) 2021, 2023 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software; you can redistribute it and/or
1.10 + * modify it under the terms of the GNU General Public License as
1.11 + * published by the Free Software Foundation; either version 2 of
1.12 + * the License, or (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program; if not, write to the Free Software
1.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.22 + * Boston, MA 02110-1301, USA
1.23 + */
1.24 +
1.25 +#pragma once
1.26 +
1.27 +#include <l4/sys/types.h>
1.28 +#include <stdint.h>
1.29 +
1.30 +
1.31 +
1.32 +/* Enumerated types for various transfer parameters. */
1.33 +
1.34 +enum Dma_jz4780_request_type
1.35 +{
1.36 + Dma_request_i2s1_out = 4,
1.37 + Dma_request_i2s1_in = 5,
1.38 + Dma_request_i2s0_out = 6,
1.39 + Dma_request_i2s0_in = 7,
1.40 + Dma_request_auto = 8,
1.41 + Dma_request_sadc_in = 9,
1.42 + Dma_request_uart4_out = 12,
1.43 + Dma_request_uart4_in = 13,
1.44 + Dma_request_uart3_out = 14,
1.45 + Dma_request_uart3_in = 15,
1.46 + Dma_request_uart2_out = 16,
1.47 + Dma_request_uart2_in = 17,
1.48 + Dma_request_uart1_out = 18,
1.49 + Dma_request_uart1_in = 19,
1.50 + Dma_request_uart0_out = 20,
1.51 + Dma_request_uart0_in = 21,
1.52 + Dma_request_ssi0_out = 22,
1.53 + Dma_request_ssi0_in = 23,
1.54 + Dma_request_ssi1_out = 24,
1.55 + Dma_request_ssi1_in = 25,
1.56 + Dma_request_msc0_out = 26,
1.57 + Dma_request_msc0_in = 27,
1.58 + Dma_request_msc1_out = 28,
1.59 + Dma_request_msc1_in = 29,
1.60 + Dma_request_msc2_out = 30,
1.61 + Dma_request_msc2_in = 31,
1.62 + Dma_request_pcm0_out = 32,
1.63 + Dma_request_pcm0_in = 33,
1.64 + Dma_request_i2c0_out = 36,
1.65 + Dma_request_i2c0_in = 37,
1.66 + Dma_request_i2c1_out = 38,
1.67 + Dma_request_i2c1_in = 39,
1.68 + Dma_request_i2c2_out = 40,
1.69 + Dma_request_i2c2_in = 41,
1.70 + Dma_request_i2c3_out = 42,
1.71 + Dma_request_i2c3_in = 43,
1.72 + Dma_request_i2c4_out = 44,
1.73 + Dma_request_i2c4_in = 45,
1.74 + Dma_request_des_out = 46,
1.75 + Dma_request_des_in = 47,
1.76 +};
1.77 +
1.78 +
1.79 +
1.80 +#ifdef __cplusplus
1.81 +
1.82 +#include <l4/devices/cpm-jz4780.h>
1.83 +#include <l4/devices/hw_mmio_register_block.h>
1.84 +
1.85 +// Forward declaration.
1.86 +
1.87 +class Dma_jz4780_chip;
1.88 +
1.89 +
1.90 +
1.91 +// DMA channel.
1.92 +
1.93 +class Dma_jz4780_channel
1.94 +{
1.95 +private:
1.96 + Hw::Register_block<32> _regs;
1.97 + Dma_jz4780_chip *_chip;
1.98 + uint8_t _channel;
1.99 + l4_cap_idx_t _irq = L4_INVALID_CAP;
1.100 +
1.101 +public:
1.102 + Dma_jz4780_channel(Dma_jz4780_chip *chip, uint8_t channel, l4_addr_t start, l4_cap_idx_t irq);
1.103 +
1.104 + unsigned int transfer(uint32_t source, uint32_t destination,
1.105 + unsigned int count,
1.106 + bool source_increment, bool destination_increment,
1.107 + uint8_t source_width, uint8_t destination_width,
1.108 + uint8_t transfer_unit_size,
1.109 + enum Dma_jz4780_request_type type=Dma_request_auto);
1.110 +
1.111 + unsigned int wait();
1.112 +
1.113 +protected:
1.114 + // Transfer property configuration.
1.115 +
1.116 + uint32_t encode_req_detect_int_length(uint8_t units);
1.117 +
1.118 + uint32_t encode_source_port_width(uint8_t width);
1.119 +
1.120 + uint32_t encode_destination_port_width(uint8_t width);
1.121 +
1.122 + uint32_t encode_transfer_unit_size(uint8_t size);
1.123 +
1.124 + // Transaction control.
1.125 +
1.126 + void ack_irq();
1.127 +
1.128 + bool completed();
1.129 +
1.130 + bool error();
1.131 +
1.132 + bool halted();
1.133 +
1.134 + bool wait_for_irq();
1.135 +
1.136 + bool wait_for_irq(unsigned int timeout);
1.137 +};
1.138 +
1.139 +// DMA device control.
1.140 +
1.141 +class Dma_jz4780_chip
1.142 +{
1.143 +private:
1.144 + Hw::Register_block<32> _regs;
1.145 + l4_addr_t _start, _end;
1.146 + Cpm_jz4780_chip *_cpm;
1.147 +
1.148 +public:
1.149 + Dma_jz4780_chip(l4_addr_t start, l4_addr_t end, Cpm_jz4780_chip *cpm);
1.150 +
1.151 + void disable();
1.152 +
1.153 + void enable();
1.154 +
1.155 + Dma_jz4780_channel *get_channel(uint8_t channel, l4_cap_idx_t irq);
1.156 +
1.157 + // Transaction control.
1.158 +
1.159 + void ack_irq(uint8_t channel);
1.160 +
1.161 + bool error();
1.162 +
1.163 + bool halted();
1.164 +
1.165 + bool have_interrupt(uint8_t channel);
1.166 +};
1.167 +
1.168 +#endif /* __cplusplus */
1.169 +
1.170 +
1.171 +
1.172 +/* C language interface. */
1.173 +
1.174 +EXTERN_C_BEGIN
1.175 +
1.176 +void *jz4780_dma_init(l4_addr_t start, l4_addr_t end, void *cpm);
1.177 +
1.178 +void jz4780_dma_disable(void *dma_chip);
1.179 +
1.180 +void jz4780_dma_enable(void *dma_chip);
1.181 +
1.182 +void *jz4780_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq);
1.183 +
1.184 +unsigned int jz4780_dma_transfer(void *dma_channel,
1.185 + uint32_t source, uint32_t destination,
1.186 + unsigned int count,
1.187 + int source_increment, int destination_increment,
1.188 + uint8_t source_width, uint8_t destination_width,
1.189 + uint8_t transfer_unit_size,
1.190 + enum Dma_jz4780_request_type type);
1.191 +
1.192 +unsigned int jz4780_dma_wait(void *dma_channel);
1.193 +
1.194 +EXTERN_C_END