1.1 --- a/pkg/devices/lib/cpm/src/jz4780.cc Thu Dec 14 22:49:02 2023 +0100
1.2 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Fri Dec 15 18:10:13 2023 +0100
1.3 @@ -220,20 +220,22 @@
1.4 Pll_bypass_M (Pll_control_M, 1, 1), // MPLL_BP
1.5 Pll_bypass_V (Pll_control_V, 1, 1), // VPLL_BP
1.6
1.7 - Pll_multiplier_A (Pll_control_A, 0x1fff, 19), // APLLM
1.8 - Pll_multiplier_E (Pll_control_E, 0x1fff, 19), // EPLLM
1.9 - Pll_multiplier_M (Pll_control_M, 0x1fff, 19), // MPLLM
1.10 - Pll_multiplier_V (Pll_control_V, 0x1fff, 19), // VPLLM
1.11 + // Multipliers and dividers yield 1-based values.
1.12 +
1.13 + Pll_multiplier_A (Pll_control_A, 0x1fff, 19, 1), // APLLM
1.14 + Pll_multiplier_E (Pll_control_E, 0x1fff, 19, 1), // EPLLM
1.15 + Pll_multiplier_M (Pll_control_M, 0x1fff, 19, 1), // MPLLM
1.16 + Pll_multiplier_V (Pll_control_V, 0x1fff, 19, 1), // VPLLM
1.17
1.18 - Pll_input_division_A (Pll_control_A, 0x3f, 13), // APLLN
1.19 - Pll_input_division_E (Pll_control_E, 0x3f, 13), // EPLLN
1.20 - Pll_input_division_M (Pll_control_M, 0x3f, 13), // MPLLN
1.21 - Pll_input_division_V (Pll_control_V, 0x3f, 13), // VPLLN
1.22 + Pll_input_division_A (Pll_control_A, 0x3f, 13, 1), // APLLN
1.23 + Pll_input_division_E (Pll_control_E, 0x3f, 13, 1), // EPLLN
1.24 + Pll_input_division_M (Pll_control_M, 0x3f, 13, 1), // MPLLN
1.25 + Pll_input_division_V (Pll_control_V, 0x3f, 13, 1), // VPLLN
1.26
1.27 - Pll_output_division_A (Pll_control_A, 0x0f, 9), // APLLOD
1.28 - Pll_output_division_E (Pll_control_E, 0x0f, 9), // EPLLOD
1.29 - Pll_output_division_M (Pll_control_M, 0x0f, 9), // MPLLOD
1.30 - Pll_output_division_V (Pll_control_V, 0x0f, 9); // VPLLOD
1.31 + Pll_output_division_A (Pll_control_A, 0x0f, 9, 1), // APLLOD
1.32 + Pll_output_division_E (Pll_control_E, 0x0f, 9, 1), // EPLLOD
1.33 + Pll_output_division_M (Pll_control_M, 0x0f, 9, 1), // MPLLOD
1.34 + Pll_output_division_V (Pll_control_V, 0x0f, 9, 1); // VPLLOD
1.35
1.36
1.37
1.38 @@ -457,29 +459,25 @@
1.39 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
1.40 Divider_pll(Pll_multiplier_A, Pll_input_division_A,
1.41 Pll_output_division_A,
1.42 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
1.43 - true)),
1.44 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
1.45
1.46 clock_pll_E(Source(mux_external),
1.47 Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
1.48 Divider_pll(Pll_multiplier_E, Pll_input_division_E,
1.49 Pll_output_division_E,
1.50 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
1.51 - true)),
1.52 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
1.53
1.54 clock_pll_M(Source(mux_external),
1.55 Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
1.56 Divider_pll(Pll_multiplier_M, Pll_input_division_M,
1.57 Pll_output_division_M,
1.58 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
1.59 - true)),
1.60 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max)),
1.61
1.62 clock_pll_V(Source(mux_external),
1.63 Control_pll(Pll_enable_V, Pll_stable_V, Pll_bypass_V),
1.64 Divider_pll(Pll_multiplier_V, Pll_input_division_V,
1.65 Pll_output_division_V,
1.66 - jz4780_pll_intermediate_min, jz4780_pll_intermediate_max,
1.67 - true));
1.68 + jz4780_pll_intermediate_min, jz4780_pll_intermediate_max));
1.69
1.70
1.71