1.1 --- a/pkg/devices/lib/cpm/src/jz4780.cc Thu Nov 16 17:48:32 2023 +0100
1.2 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Thu Nov 16 22:03:51 2023 +0100
1.3 @@ -252,9 +252,9 @@
1.4
1.5 // Main bus and peripheral clock sources.
1.6
1.7 - mux_ahb2 (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_rtc)),
1.8 + mux_ahb2 (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_rtc_external)),
1.9 mux_core (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_pll_E)),
1.10 - mux_main (4, Clocks(Clock_none, Clock_pll_A, Clock_external, Clock_rtc)),
1.11 + mux_main (4, Clocks(Clock_none, Clock_pll_A, Clock_external, Clock_rtc_external)),
1.12
1.13 // Memory and device clock sources.
1.14
1.15 @@ -276,7 +276,8 @@
1.16
1.17 static Clock_null clock_none;
1.18
1.19 -static Clock_passive clock_external(48000000), clock_rtc(32768);
1.20 +static Clock_passive clock_external(48000000),
1.21 + clock_rtc_external(32768);
1.22
1.23
1.24
1.25 @@ -432,6 +433,9 @@
1.26 Control(Clock_gate_vpu, Clock_change_enable_vpu, Clock_busy_vpu),
1.27 Divider(Clock_divider_vpu));
1.28
1.29 +static Clock_divided_fixed
1.30 + clock_external_div_512((Source(mux_external)), (Divider_fixed(512)));
1.31 +
1.32 const double jz4780_pll_intermediate_min = 300000000,
1.33 jz4780_pll_intermediate_max = 1500000000;
1.34
1.35 @@ -480,6 +484,7 @@
1.36 &clock_dma,
1.37 &clock_none, // Clock_emac
1.38 &clock_external,
1.39 + &clock_external_div_512,
1.40 &clock_hclock0,
1.41 &clock_hclock2,
1.42 &clock_hclock2_pclock,
1.43 @@ -517,7 +522,8 @@
1.44 &clock_pll_V,
1.45 &clock_none, // Clock_pwm0
1.46 &clock_none, // Clock_pwm1
1.47 - &clock_rtc,
1.48 + &clock_external_div_512,// Clock_rtc
1.49 + &clock_rtc_external,
1.50 &clock_scc,
1.51 &clock_none, // Clock_sfc
1.52 &clock_ssi,