1.1 --- a/pkg/devices/lib/cpm/include/cpm-common.h Tue Oct 24 18:52:06 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/include/cpm-common.h Fri Oct 27 18:02:49 2023 +0200
1.3 @@ -23,8 +23,8 @@
1.4
1.5 #ifdef __cplusplus
1.6
1.7 +#include <l4/devices/clocks.h>
1.8 #include <l4/devices/hw_register_block.h>
1.9 -#include <l4/devices/cpm.h>
1.10 #include <l4/sys/types.h>
1.11 #include <stdint.h>
1.12
1.13 @@ -38,16 +38,12 @@
1.14
1.15 class Cpm_regs
1.16 {
1.17 +protected:
1.18 Hw::Register_block<32> _regs;
1.19 -
1.20 -protected:
1.21 Clock_base **_clocks;
1.22
1.23 public:
1.24 - uint32_t exclk_freq;
1.25 -
1.26 - explicit Cpm_regs(l4_addr_t addr, Clock_base *clocks[],
1.27 - uint32_t exclk_freq);
1.28 + explicit Cpm_regs(l4_addr_t addr, Clock_base *clocks[]);
1.29
1.30 // Utility methods.
1.31
1.32 @@ -217,6 +213,10 @@
1.33 int have_clock(Cpm_regs ®s);
1.34 void start_clock(Cpm_regs ®s);
1.35 void stop_clock(Cpm_regs ®s);
1.36 +
1.37 + // Undefined control object.
1.38 +
1.39 + static Control undefined;
1.40 };
1.41
1.42
1.43 @@ -314,6 +314,7 @@
1.44 class Divider_pll : public Divider_base
1.45 {
1.46 Field _multiplier, _input_divider, _output_divider0, _output_divider1;
1.47 + double _intermediate_min, _intermediate_max;
1.48
1.49 // General frequency modifiers.
1.50
1.51 @@ -325,10 +326,26 @@
1.52 void set_output_divider(Cpm_regs ®s, uint32_t divider);
1.53
1.54 public:
1.55 +
1.56 + // Double output divider constructor.
1.57 +
1.58 explicit Divider_pll(Field multiplier, Field input_divider,
1.59 - Field output_divider0, Field output_divider1)
1.60 + Field output_divider0, Field output_divider1,
1.61 + double intermediate_min, double intermediate_max)
1.62 : _multiplier(multiplier), _input_divider(input_divider),
1.63 - _output_divider0(output_divider0), _output_divider1(output_divider1)
1.64 + _output_divider0(output_divider0), _output_divider1(output_divider1),
1.65 + _intermediate_min(intermediate_min), _intermediate_max(intermediate_max)
1.66 + {
1.67 + }
1.68 +
1.69 + // Single output divider constructor.
1.70 +
1.71 + explicit Divider_pll(Field multiplier, Field input_divider,
1.72 + Field output_divider,
1.73 + double intermediate_min, double intermediate_max)
1.74 + : _multiplier(multiplier), _input_divider(input_divider),
1.75 + _output_divider0(output_divider), _output_divider1(Field::undefined),
1.76 + _intermediate_min(intermediate_min), _intermediate_max(intermediate_max)
1.77 {
1.78 }
1.79
1.80 @@ -425,7 +442,15 @@
1.81
1.82 class Clock_passive : public Clock_base
1.83 {
1.84 +protected:
1.85 + uint32_t _frequency;
1.86 +
1.87 public:
1.88 + explicit Clock_passive(uint32_t frequency)
1.89 + : _frequency(frequency)
1.90 + {
1.91 + }
1.92 +
1.93 const char *clock_type() { return "passive"; }
1.94
1.95 // Clock control.
1.96 @@ -584,6 +609,11 @@
1.97 {
1.98 }
1.99
1.100 + explicit Clock_divided(Source source, Divider divider)
1.101 + : Clock_divided_base(source), _control(Control::undefined), _divider(divider)
1.102 + {
1.103 + }
1.104 +
1.105 const char *clock_type() { return "divided"; }
1.106 };
1.107