1.1 --- a/pkg/devices/lib/cpm/include/cpm-jz4780.h Tue Oct 24 18:52:06 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/include/cpm-jz4780.h Fri Oct 27 18:02:49 2023 +0200
1.3 @@ -21,8 +21,7 @@
1.4
1.5 #pragma once
1.6
1.7 -#include <l4/devices/cpm.h>
1.8 -
1.9 +#include <l4/devices/clocks.h>
1.10 #include <l4/sys/types.h>
1.11 #include <stdint.h>
1.12
1.13 @@ -30,125 +29,12 @@
1.14
1.15 #ifdef __cplusplus
1.16
1.17 -#include <l4/devices/hw_register_block.h>
1.18 -
1.19 -/* A simple abstraction for accessing the CPM registers.
1.20 - * A proper device could inherit from Hw::Device and use an
1.21 - * Int_property for _exclk_freq and _rtclk_freq. */
1.22 +#include <l4/devices/cpm.h>
1.23
1.24 class Cpm_jz4780_chip : public Cpm_chip
1.25 {
1.26 -private:
1.27 - Hw::Register_block<32> _regs;
1.28 - uint32_t _exclk_freq, _rtclk_freq;
1.29 -
1.30 - // Utility methods.
1.31 -
1.32 - uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift);
1.33 - void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value);
1.34 - uint8_t _get_divider(uint32_t reg, uint32_t mask, uint8_t shift);
1.35 -
1.36 - // PLL status.
1.37 -
1.38 - int have_pll(uint32_t pll_reg);
1.39 - int pll_enabled(uint32_t pll_reg);
1.40 - int pll_bypassed(uint32_t pll_reg);
1.41 -
1.42 - // PLL control.
1.43 -
1.44 - void pll_disable(uint32_t pll_reg);
1.45 - void pll_enable(uint32_t pll_reg);
1.46 -
1.47 - // General frequency modifiers.
1.48 -
1.49 - uint16_t get_multiplier(uint32_t pll_reg);
1.50 - void set_multiplier(uint32_t pll_reg, uint16_t multiplier);
1.51 - uint8_t get_input_division(uint32_t pll_reg);
1.52 - void set_input_division(uint32_t pll_reg, uint8_t divider);
1.53 - uint8_t get_output_division(uint32_t pll_reg);
1.54 - void set_output_division(uint32_t pll_reg, uint8_t divider);
1.55 -
1.56 - // Clock dividers.
1.57 -
1.58 - void set_hdmi_divider(uint16_t division);
1.59 - void set_lcd_pixel_divider(uint8_t controller, uint16_t division);
1.60 -
1.61 - // Input frequencies.
1.62 -
1.63 - uint32_t get_pll_frequency(uint32_t pll_reg);
1.64 -
1.65 - // Clock sources.
1.66 -
1.67 - void set_hclock2_source(uint8_t source);
1.68 - void set_hdmi_source(uint8_t source);
1.69 - void set_lcd_source(uint8_t controller, uint8_t source);
1.70 -
1.71 - // Clock control.
1.72 -
1.73 - uint32_t get_clock_gate_register(enum Clock_identifiers clock);
1.74 - uint32_t get_clock_gate_value(enum Clock_identifiers clock);
1.75 -
1.76 public:
1.77 - void set_pclock_source(uint8_t source);
1.78 - Cpm_jz4780_chip(l4_addr_t addr, uint32_t exclk_freq, uint32_t rtclk_freq);
1.79 -
1.80 - // Clock divider values.
1.81 -
1.82 - uint8_t get_cpu_divider();
1.83 - uint8_t get_hclock0_divider();
1.84 - uint8_t get_hclock2_divider();
1.85 - uint8_t get_pclock_divider();
1.86 - uint8_t get_hdmi_divider();
1.87 - uint8_t get_lcd_pixel_divider(uint8_t controller = 0);
1.88 - uint8_t get_memory_divider();
1.89 -
1.90 - // Clock sources.
1.91 -
1.92 - uint8_t get_main_source();
1.93 - uint8_t get_cpu_source();
1.94 - uint8_t get_hclock0_source();
1.95 - uint8_t get_hclock2_source();
1.96 - uint8_t get_hdmi_source();
1.97 - uint8_t get_lcd_source(uint8_t controller);
1.98 - uint8_t get_lcd_source() { return get_lcd_source(0); }
1.99 - uint8_t get_memory_source();
1.100 - uint8_t get_pclock_source();
1.101 -
1.102 - // PLL frequency status.
1.103 -
1.104 - uint32_t get_apll_frequency();
1.105 - uint32_t get_epll_frequency();
1.106 - uint32_t get_mpll_frequency();
1.107 - uint32_t get_vpll_frequency();
1.108 -
1.109 - uint32_t get_main_frequency();
1.110 - uint32_t get_cpu_source_frequency();
1.111 - uint32_t get_hclock0_source_frequency();
1.112 - uint32_t get_hclock2_source_frequency();
1.113 - uint32_t get_hdmi_source_frequency();
1.114 - uint32_t get_lcd_source_frequency(uint8_t controller);
1.115 - uint32_t get_lcd_source_frequency() { return get_lcd_source_frequency(0); }
1.116 - uint32_t get_memory_source_frequency();
1.117 - uint32_t get_pclock_source_frequency();
1.118 -
1.119 - // Clock frequency status.
1.120 -
1.121 - uint32_t get_cpu_frequency();
1.122 - uint32_t get_hclock0_frequency();
1.123 - uint32_t get_hclock2_frequency();
1.124 - uint32_t get_memory_frequency();
1.125 - uint32_t get_pclock_frequency();
1.126 -
1.127 - void set_pll_parameters(uint32_t pll_reg, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider);
1.128 -
1.129 - // Clock frequency configuration.
1.130 -
1.131 - uint32_t get_frequency(enum Clock_identifiers clock);
1.132 - void set_frequency(enum Clock_identifiers clock, uint32_t frequency);
1.133 -
1.134 - int have_clock(enum Clock_identifiers clock);
1.135 - void start_clock(enum Clock_identifiers clock);
1.136 - void stop_clock(enum Clock_identifiers clock);
1.137 + explicit Cpm_jz4780_chip(l4_addr_t addr);
1.138 };
1.139
1.140 #endif /* __cplusplus */
1.141 @@ -161,51 +47,25 @@
1.142
1.143 void *jz4780_cpm_init(l4_addr_t cpm_base);
1.144
1.145 +const char *jz4780_cpm_clock_type(void *cpm, enum Clock_identifiers clock);
1.146 +
1.147 int jz4780_cpm_have_clock(void *cpm, enum Clock_identifiers clock);
1.148 void jz4780_cpm_start_clock(void *cpm, enum Clock_identifiers clock);
1.149 void jz4780_cpm_stop_clock(void *cpm, enum Clock_identifiers clock);
1.150
1.151 -uint8_t jz4780_cpm_get_cpu_divider(void *cpm);
1.152 -uint8_t jz4780_cpm_get_hclock0_divider(void *cpm);
1.153 -uint8_t jz4780_cpm_get_hclock2_divider(void *cpm);
1.154 -uint8_t jz4780_cpm_get_hdmi_divider(void *cpm);
1.155 -uint8_t jz4780_cpm_get_lcd_pixel_divider(void *cpm);
1.156 -uint8_t jz4780_cpm_get_memory_divider(void *cpm);
1.157 -uint8_t jz4780_cpm_get_pclock_divider(void *cpm);
1.158 -
1.159 -uint8_t jz4780_cpm_get_hclock0_source(void *cpm);
1.160 -uint8_t jz4780_cpm_get_hclock2_source(void *cpm);
1.161 -uint8_t jz4780_cpm_get_hdmi_source(void *cpm);
1.162 -uint8_t jz4780_cpm_get_lcd_source(void *cpm);
1.163 -uint8_t jz4780_cpm_get_memory_source(void *cpm);
1.164 -uint8_t jz4780_cpm_get_pclock_source(void *cpm);
1.165 +int jz4780_cpm_get_parameters(void *cpm, enum Clock_identifiers clock,
1.166 + uint32_t parameters[]);
1.167 +int jz4780_cpm_set_parameters(void *cpm, enum Clock_identifiers clock,
1.168 + int num_parameters, uint32_t parameters[]);
1.169
1.170 -uint32_t jz4780_cpm_get_hclock0_source_frequency(void *cpm);
1.171 -uint32_t jz4780_cpm_get_hclock2_source_frequency(void *cpm);
1.172 -uint32_t jz4780_cpm_get_hdmi_source_frequency(void *cpm);
1.173 -uint32_t jz4780_cpm_get_lcd_source_frequency(void *cpm);
1.174 -uint32_t jz4780_cpm_get_memory_source_frequency(void *cpm);
1.175 -uint32_t jz4780_cpm_get_pclock_source_frequency(void *cpm);
1.176 -
1.177 -void jz4780_cpm_set_pclock_source(void *cpm, uint8_t source);
1.178 +uint8_t jz4780_cpm_get_source(void *cpm, enum Clock_identifiers clock);
1.179 +void jz4780_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source);
1.180 +enum Clock_identifiers jz4780_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock);
1.181 +void jz4780_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source);
1.182
1.183 -uint8_t jz4780_cpm_get_main_source(void *cpm);
1.184 -uint32_t jz4780_cpm_get_main_frequency(void *cpm);
1.185 -
1.186 -uint32_t jz4780_cpm_get_cpu_frequency(void *cpm);
1.187 -uint32_t jz4780_cpm_get_hclock0_frequency(void *cpm);
1.188 -uint32_t jz4780_cpm_get_hclock2_frequency(void *cpm);
1.189 -uint32_t jz4780_cpm_get_memory_frequency(void *cpm);
1.190 -uint32_t jz4780_cpm_get_pclock_frequency(void *cpm);
1.191 -
1.192 -uint32_t jz4780_cpm_get_apll_frequency(void *cpm);
1.193 -uint32_t jz4780_cpm_get_epll_frequency(void *cpm);
1.194 -uint32_t jz4780_cpm_get_mpll_frequency(void *cpm);
1.195 -uint32_t jz4780_cpm_get_vpll_frequency(void *cpm);
1.196 +uint32_t jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock);
1.197
1.198 uint32_t jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock);
1.199 -void jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency);
1.200 -
1.201 -void jz4780_cpm_set_mpll_parameters(void *cpm, uint16_t multiplier, uint8_t in_divider, uint8_t out_divider);
1.202 +int jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency);
1.203
1.204 EXTERN_C_END