1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pkg/devices/lib/spi/src/common.cc Fri Jun 07 16:12:32 2024 +0200
1.3 @@ -0,0 +1,465 @@
1.4 +/*
1.5 + * Perform SPI communication using the JZ4780/X1600 SPI peripheral.
1.6 + *
1.7 + * Copyright (C) 2023, 2024 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software; you can redistribute it and/or
1.10 + * modify it under the terms of the GNU General Public License as
1.11 + * published by the Free Software Foundation; either version 2 of
1.12 + * the License, or (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program; if not, write to the Free Software
1.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.22 + * Boston, MA 02110-1301, USA
1.23 + */
1.24 +
1.25 +#include <l4/devices/byteorder.h>
1.26 +#include <l4/devices/dma.h>
1.27 +#include <l4/devices/spi-common.h>
1.28 +#include <l4/sys/err.h>
1.29 +#include <string.h>
1.30 +#include <stdio.h>
1.31 +
1.32 +
1.33 +
1.34 +/* Register definitions. */
1.35 +
1.36 +enum Regs
1.37 +{
1.38 + Ssi_data = 0x00, // SSIDR
1.39 + Ssi_control0 = 0x04, // SSICR0
1.40 + Ssi_control1 = 0x08, // SSICR1
1.41 + Ssi_status = 0x0c, // SSISR
1.42 + Ssi_interval_time = 0x10, // SSIITR
1.43 + Ssi_char_per_frame = 0x14, // SSIICR
1.44 + Ssi_clock = 0x18, // SSICGR
1.45 + Ssi_recv_counter = 0x1c, // SSIRCNT
1.46 +};
1.47 +
1.48 +enum Ssi_data_bits : unsigned
1.49 +{
1.50 + Ssi_data_gpc_set = 0x10000,
1.51 + Ssi_data_gpc_unset = 0x00000,
1.52 +};
1.53 +
1.54 +enum Ssi_control0_bits : unsigned
1.55 +{
1.56 + Ssi_trans_endian_mask = 0xc0000,
1.57 + Ssi_trans_endian_msbyte_msbit = 0x00000,
1.58 + Ssi_trans_endian_msbyte_lsbit = 0x40000,
1.59 + Ssi_trans_endian_lsbyte_lsbit = 0x80000,
1.60 + Ssi_trans_endian_lsbyte_msbit = 0xc0000,
1.61 +
1.62 + Ssi_recv_endian_mask = 0x30000,
1.63 + Ssi_recv_endian_msbyte_msbit = 0x00000,
1.64 + Ssi_recv_endian_msbyte_lsbit = 0x10000,
1.65 + Ssi_recv_endian_lsbyte_lsbit = 0x20000,
1.66 + Ssi_recv_endian_lsbyte_msbit = 0x30000,
1.67 +
1.68 + Ssi_enable = 0x08000,
1.69 + Ssi_enable_trans_half_empty = 0x04000,
1.70 + Ssi_enable_recv_half_full = 0x02000,
1.71 + Ssi_enable_trans_error = 0x01000,
1.72 + Ssi_enable_recv_error = 0x00800,
1.73 + Ssi_loopback = 0x00400,
1.74 + Ssi_recv_finish_control = 0x00200,
1.75 + Ssi_recv_finished = 0x00100,
1.76 + Ssi_enable_auto_clear_underrun = 0x00080,
1.77 + Ssi_select_pin_is_ce2 = 0x00040,
1.78 + Ssi_use_recv_count = 0x00010,
1.79 + Ssi_old_fifo_empty_mode = 0x00008,
1.80 + Ssi_trans_flush = 0x00004,
1.81 + Ssi_recv_flush = 0x00002,
1.82 + Ssi_disable_recv = 0x00001,
1.83 +};
1.84 +
1.85 +enum Ssi_control1_bits : unsigned
1.86 +{
1.87 + Ssi_active_mask = 0xc0000000,
1.88 + Ssi_active_ce_low = 0x00000000,
1.89 + Ssi_active_ce_high = 0x40000000,
1.90 + Ssi_active_ce2_low = 0x00000000,
1.91 + Ssi_active_ce2_high = 0x80000000,
1.92 +
1.93 + Ssi_clock_start_delay_mask = 0x30000000,
1.94 + Ssi_clock_start_delay_default = 0x00000000,
1.95 + Ssi_clock_start_delay_plus_1 = 0x10000000,
1.96 + Ssi_clock_start_delay_plus_2 = 0x20000000,
1.97 + Ssi_clock_start_delay_plus_3 = 0x30000000,
1.98 +
1.99 + Ssi_clock_stop_delay_mask = 0x0c000000,
1.100 + Ssi_clock_stop_delay_default = 0x00000000,
1.101 + Ssi_clock_stop_delay_plus_1 = 0x04000000,
1.102 + Ssi_clock_stop_delay_plus_2 = 0x08000000,
1.103 + Ssi_clock_stop_delay_plus_3 = 0x0c000000,
1.104 +
1.105 + /* X1600... */
1.106 +
1.107 + Ssi_gpc_level_from_gpc_bit = 0x00000000,
1.108 + Ssi_gpc_level_from_gpc_level = 0x02000000,
1.109 +
1.110 + /* Common... */
1.111 +
1.112 + Ssi_interval_assert_ce_or_ce2 = 0x01000000,
1.113 + Ssi_trans_empty_unfinished = 0x00800000,
1.114 +
1.115 + Ssi_format_mask = 0x00300000,
1.116 + Ssi_format_spi = 0x00000000,
1.117 + Ssi_format_ssp = 0x00100000,
1.118 + Ssi_format_microwire1 = 0x00200000,
1.119 + Ssi_format_microwire2 = 0x00300000,
1.120 +
1.121 + Ssi_trans_threshold_mask = 0x000f0000,
1.122 + Ssi_command_length_mask = 0x0000f000,
1.123 + Ssi_recv_threshold_mask = 0x00000f00,
1.124 + Ssi_char_length_mask = 0x000000f8,
1.125 +
1.126 + /* X1600... */
1.127 +
1.128 + Ssi_gpc_level = 0x00000004, // see Ssi_gpc_level_from_gpc_level
1.129 +
1.130 + /* Common... */
1.131 +
1.132 + Spi_clock_assert_sample = 0x00000000, // phase #0
1.133 + Spi_clock_assert_drive = 0x00000002, // phase #1
1.134 + Spi_clock_idle_low_level = 0x00000000, // polarity #0
1.135 + Spi_clock_idle_high_level = 0x00000001, // polarity #1
1.136 +};
1.137 +
1.138 +enum Ssi_control1_shifts : unsigned
1.139 +{
1.140 + Ssi_trans_threshold_shift = 16,
1.141 + Ssi_command_length_shift = 12,
1.142 + Ssi_recv_threshold_shift = 8,
1.143 + Ssi_char_length_shift = 3,
1.144 +};
1.145 +
1.146 +enum Ssi_control1_limits : unsigned
1.147 +{
1.148 + Ssi_trans_threshold_limit = 15,
1.149 + Ssi_command_length_limit = 15,
1.150 + Ssi_recv_threshold_limit = 15,
1.151 + Ssi_char_length_limit = 30,
1.152 +};
1.153 +
1.154 +enum Ssi_status_bits : unsigned
1.155 +{
1.156 + Ssi_trans_char_count_mask = 0x00ff0000,
1.157 + Ssi_recv_char_count_mask = 0x0000ff00,
1.158 + Ssi_trans_ended = 0x00000080,
1.159 + Ssi_trans_busy = 0x00000040,
1.160 + Ssi_trans_fifo_full = 0x00000020,
1.161 + Ssi_recv_fifo_empty = 0x00000010,
1.162 + Ssi_trans_fifo_half_empty = 0x00000008,
1.163 + Ssi_recv_fifo_half_full = 0x00000004,
1.164 + Ssi_trans_underrun = 0x00000002,
1.165 + Ssi_recv_overrun = 0x00000001,
1.166 +};
1.167 +
1.168 +enum Ssi_status_shifts : unsigned
1.169 +{
1.170 + Ssi_trans_char_count_shift = 16,
1.171 + Ssi_recv_char_count_shift = 8,
1.172 +};
1.173 +
1.174 +enum Ssi_status_limits : unsigned
1.175 +{
1.176 + Ssi_trans_char_count_limit = 0xff,
1.177 + Ssi_recv_char_count_limit = 0xff,
1.178 +};
1.179 +
1.180 +enum Ssi_interval_time_bits : unsigned
1.181 +{
1.182 + Ssi_interval_clock_mask = 0x8000,
1.183 + Ssi_interval_clock_bit_clock = 0x0000,
1.184 + Ssi_interval_clock_32k_clock = 0x8000,
1.185 + Ssi_interval_time_mask = 0x3fff,
1.186 +};
1.187 +
1.188 +enum Ssi_char_per_frame_bits : unsigned
1.189 +{
1.190 + Ssi_char_per_frame_mask = 0x7,
1.191 +};
1.192 +
1.193 +enum Ssi_clock_bits : unsigned
1.194 +{
1.195 + Ssi_clock_frequency_mask = 0xff,
1.196 +};
1.197 +
1.198 +enum Ssi_recv_counter_bits : unsigned
1.199 +{
1.200 + Ssi_recv_counter_mask = 0xffff,
1.201 +};
1.202 +
1.203 +
1.204 +
1.205 +/* Initialise a channel. */
1.206 +
1.207 +Spi_channel::Spi_channel(l4_addr_t spi_start, l4_addr_t start,
1.208 + enum Clock_identifiers clock,
1.209 + Cpm_chip *cpm,
1.210 + Dma_channel *dma,
1.211 + int request_type,
1.212 + uint64_t frequency)
1.213 +: _spi_start(spi_start), _clock(clock), _cpm(cpm), _dma(dma),
1.214 + _request_type(request_type), _frequency(frequency)
1.215 +{
1.216 + _regs = new Hw::Mmio_register_block<32>(start);
1.217 + _cpm->start_clock(clock);
1.218 +
1.219 + /* Disable the channel while configuring: send MSB first, big endian wire
1.220 + representation. Disable reception. */
1.221 +
1.222 + _regs[Ssi_control0] = Ssi_trans_endian_msbyte_msbit |
1.223 + Ssi_select_pin_is_ce2 |
1.224 + Ssi_disable_recv;
1.225 +
1.226 + /* Set default transfer properties. */
1.227 +
1.228 + configure_transfer(8);
1.229 +
1.230 + /* Select "normal" mode. */
1.231 +
1.232 + _regs[Ssi_interval_time] = 0;
1.233 +
1.234 + /* Limit the frequency to half that of the device clock. */
1.235 +
1.236 + if (_frequency >= _cpm->get_frequency(_clock))
1.237 + _frequency = _cpm->get_frequency(_clock) / 2;
1.238 +
1.239 + /* SSI_CLK = DEV_CLK / (2 * (divider + 1)) */
1.240 +
1.241 + uint32_t divider = _cpm->get_frequency(_clock) / (_frequency * 2) - 1;
1.242 +
1.243 + _regs[Ssi_clock] = divider < Ssi_clock_frequency_mask ? divider : Ssi_clock_frequency_mask;
1.244 +
1.245 + /* Enable the channel. */
1.246 +
1.247 + _regs[Ssi_control0] = _regs[Ssi_control0] | Ssi_enable;
1.248 +}
1.249 +
1.250 +/* NOTE: More transfer characteristics should be configurable. */
1.251 +
1.252 +void Spi_channel::configure_transfer(uint8_t char_size)
1.253 +{
1.254 + uint32_t char_length;
1.255 +
1.256 + if (char_size < 2)
1.257 + char_length = 0;
1.258 + else
1.259 + {
1.260 + char_length = char_size - 2;
1.261 +
1.262 + if (char_size > Ssi_char_length_limit)
1.263 + char_length = Ssi_char_length_limit;
1.264 + }
1.265 +
1.266 + /* Clear the status. */
1.267 +
1.268 + _regs[Ssi_control0] = _regs[Ssi_control0] | Ssi_trans_flush | Ssi_recv_flush;
1.269 + _regs[Ssi_status] = 0;
1.270 +
1.271 + /* Indicate the desired character size.
1.272 +
1.273 + Use active low device selection, SPI format with active low clock, with
1.274 + data driven on the falling (asserted) clock and sampled on the rising
1.275 + clock. */
1.276 +
1.277 + _regs[Ssi_control1] = (char_length << Ssi_char_length_shift) |
1.278 + ((Ssi_trans_threshold_limit / 2) << Ssi_trans_threshold_shift) |
1.279 + Ssi_format_spi | Ssi_active_ce2_low |
1.280 + Spi_clock_assert_sample | Spi_clock_idle_low_level;
1.281 +}
1.282 +
1.283 +/* Transfer the given number of bytes from a buffer. */
1.284 +
1.285 +uint32_t
1.286 +Spi_channel::send(uint32_t bytes, const uint8_t data[])
1.287 +{
1.288 + return send_units(bytes, data, 1, 8, false);
1.289 +}
1.290 +
1.291 +/* Transfer the given number of bytes from a buffer together with control
1.292 + values. Return the number of bytes transferred. */
1.293 +
1.294 +uint32_t
1.295 +Spi_channel::send_dc(uint32_t bytes, const uint8_t data[],
1.296 + const int dc[], uint8_t char_size, bool big_endian)
1.297 +{
1.298 + configure_transfer(char_size);
1.299 +
1.300 + uint32_t transferred, char_unit;
1.301 + uint8_t char_unit_size = ((char_size ? char_size - 1 : 0) / 8) + 1;
1.302 + uint32_t char_mask = (1 << char_size) - 1;
1.303 + bool last_control;
1.304 +
1.305 + for (transferred = 0, char_unit = 0; transferred < bytes;
1.306 + transferred += char_unit_size, char_unit++)
1.307 + {
1.308 + uint32_t value = get_stored_value(&data[transferred], char_unit_size, big_endian);
1.309 +
1.310 + /* Relocate the data/command level to bit 16. */
1.311 +
1.312 + uint32_t command = dc[char_unit] ? Ssi_data_gpc_set : Ssi_data_gpc_unset;
1.313 +
1.314 + /* Wait if the FIFO is full before sending. */
1.315 +
1.316 + while (_regs[Ssi_status] & Ssi_trans_fifo_full);
1.317 +
1.318 + /* Combine the character with the data/command bit. */
1.319 +
1.320 + if (_control == NULL)
1.321 + _regs[Ssi_data] = (value & char_mask) | command;
1.322 + else
1.323 + {
1.324 + /* Set the control level after waiting for sending to complete to ensure
1.325 + synchronisation. */
1.326 +
1.327 + bool this_control = dc[char_unit];
1.328 +
1.329 + if (transferred && (this_control != last_control))
1.330 + wait_busy();
1.331 +
1.332 + _control->acquire_control(this_control ? 1 : 0);
1.333 + _regs[Ssi_data] = (value & char_mask);
1.334 + last_control = this_control;
1.335 + }
1.336 + }
1.337 +
1.338 + wait_busy();
1.339 +
1.340 + return transferred;
1.341 +}
1.342 +
1.343 +/* Transfer the given number of bytes from a buffer using the given unit size in
1.344 + bytes and character size in bits. The bytes are stored in a big endian
1.345 + arrangement. Return the number of bytes transferred. */
1.346 +
1.347 +uint32_t
1.348 +Spi_channel::send_units(uint32_t bytes, const uint8_t data[],
1.349 + uint8_t unit_size, uint8_t char_size,
1.350 + bool big_endian)
1.351 +{
1.352 + configure_transfer(char_size);
1.353 +
1.354 + uint32_t transferred;
1.355 + uint32_t char_mask = (1 << char_size) - 1;
1.356 + bool last_control;
1.357 +
1.358 + for (transferred = 0; transferred < bytes; transferred += unit_size)
1.359 + {
1.360 + uint32_t value = get_stored_value(&data[transferred], unit_size, big_endian);
1.361 +
1.362 + /* Relocate any command bit to bit 16 for byte characters. */
1.363 +
1.364 + bool data_only = unit_size * 8 == char_size;
1.365 + bool gpc_set = (char_size < 16) && (value & (1 << char_size));
1.366 + uint32_t command = gpc_set ? Ssi_data_gpc_set : Ssi_data_gpc_unset;
1.367 +
1.368 + /* Wait if the FIFO is full before sending. */
1.369 +
1.370 + while (_regs[Ssi_status] & Ssi_trans_fifo_full);
1.371 +
1.372 + /* Combine the character portion of the unit with the command. */
1.373 +
1.374 + if (_control == NULL)
1.375 + _regs[Ssi_data] = (value & char_mask) | command;
1.376 + else
1.377 + {
1.378 + /* Set the control level after waiting for sending to complete to ensure
1.379 + synchronisation. */
1.380 +
1.381 + bool this_control = gpc_set || data_only;
1.382 +
1.383 + if (transferred && (this_control != last_control))
1.384 + wait_busy();
1.385 +
1.386 + _control->acquire_control(this_control ? 1 : 0);
1.387 + _regs[Ssi_data] = (value & char_mask);
1.388 + last_control = this_control;
1.389 + }
1.390 + }
1.391 +
1.392 + wait_busy();
1.393 +
1.394 + return transferred;
1.395 +}
1.396 +
1.397 +/* Transfer the given number of bytes from a DMA region using the given
1.398 + unit size in bytes and character size in bits. Return the number of bytes
1.399 + transferred. */
1.400 +
1.401 +uint32_t
1.402 +Spi_channel::transfer(l4_addr_t vaddr,
1.403 + l4re_dma_space_dma_addr_t paddr,
1.404 + uint32_t count, uint8_t unit_size,
1.405 + uint8_t char_size,
1.406 + l4_addr_t desc_vaddr,
1.407 + l4re_dma_space_dma_addr_t desc_paddr)
1.408 +{
1.409 + /* Employ a non-DMA transfer if no usable physical address is provided.
1.410 + Assume little endian byte ordering in line with the native value
1.411 + representation. */
1.412 +
1.413 + if (!paddr)
1.414 + return send_units(count, (const uint8_t *) vaddr, unit_size, char_size,
1.415 + false);
1.416 +
1.417 + /* Configure and initiate a DMA transfer with optional descriptor. */
1.418 +
1.419 + configure_transfer(char_size);
1.420 +
1.421 + uint32_t transferred = 0;
1.422 + uint32_t unit_count = count / unit_size;
1.423 + uint32_t to_transfer = _dma->transfer(paddr, _spi_start + Ssi_data,
1.424 + unit_count, true, false,
1.425 + unit_size, unit_size, unit_size,
1.426 + _request_type, desc_vaddr, desc_paddr);
1.427 +
1.428 + /* Wait if not using a descriptor, which could be configured in a cycle to
1.429 + cause an endless, repeating transfer, perhaps updating a display, for
1.430 + example. */
1.431 +
1.432 + if (to_transfer && !desc_vaddr)
1.433 + {
1.434 + transferred = to_transfer ? (unit_count - _dma->wait()) * unit_size : 0;
1.435 + wait_busy();
1.436 + }
1.437 + else
1.438 + transferred = to_transfer * unit_size;
1.439 +
1.440 + return transferred;
1.441 +}
1.442 +
1.443 +/* Wait for the busy condition to clear or for a limited period. */
1.444 +
1.445 +void
1.446 +Spi_channel::wait_busy()
1.447 +{
1.448 + for (unsigned int i = 0; i < (1 << 20) && (_regs[Ssi_status] & Ssi_trans_busy); i++);
1.449 +}
1.450 +
1.451 +
1.452 +
1.453 +/* Initialise the peripheral abstraction. */
1.454 +
1.455 +Spi_chip::Spi_chip(l4_addr_t spi_start, l4_addr_t start, l4_addr_t end,
1.456 + Cpm_chip *cpm)
1.457 +: _spi_start(spi_start), _start(start), _end(end), _cpm(cpm)
1.458 +{
1.459 +}
1.460 +
1.461 +Spi_channel *
1.462 +Spi_chip::get_channel(uint8_t channel, Dma_channel *dma, uint64_t frequency)
1.463 +{
1.464 + if (channel < num_channels())
1.465 + return _get_channel(channel, dma, frequency);
1.466 + else
1.467 + throw -L4_EINVAL;
1.468 +}