1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Sat Sep 16 17:56:49 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Sun Sep 17 18:41:41 2023 +0200
1.3 @@ -40,8 +40,10 @@
1.4 Clock_status = 0x0d4, // CPCSR
1.5 Divider_ddr = 0x02c, // DDRCDR
1.6 Divider_mac = 0x054, // MACCDR
1.7 - Divider0_i2s0 = 0x060, // I2SCDR
1.8 - Divider1_i2s0 = 0x070, // I2S1CDR
1.9 + Divider0_i2s0 = 0x060, // I2S0CDR
1.10 + Divider1_i2s0 = 0x070, // I2S0CDR1
1.11 + Divider0_i2s1 = 0x07c, // I2S1CDR (from X2000 manual)
1.12 + Divider1_i2s1 = 0x080, // I2S1CDR1 (from X2000 manual)
1.13 Divider_lcd = 0x064, // LPCDR
1.14 Divider_msc0 = 0x068, // MSC0CDR
1.15 Divider_msc1 = 0x0a4, // MSC1CDR
1.16 @@ -87,140 +89,146 @@
1.17
1.18 // Register field definitions.
1.19
1.20 -Field Clock_source_main (Clock_control, 3, 30); // SEL_SRC (output to SCLK_A)
1.21 -Field Clock_source_cpu (Clock_control, 3, 28); // SEL_CPLL (output to CCLK)
1.22 -Field Clock_source_hclock0 (Clock_control, 3, 26); // SEL_H0PLL (output to AHB0)
1.23 -Field Clock_source_hclock2 (Clock_control, 3, 24); // SEL_H2PLL (output to AHB2)
1.24 -Field Clock_source_can0 (Divider_can0, 3, 30); // CA0CS
1.25 -Field Clock_source_can1 (Divider_can1, 3, 30); // CA1CS
1.26 -Field Clock_source_cdbus (Divider_cdbus, 3, 30); // CDCS
1.27 -Field Clock_source_cim (Divider_cim, 3, 30); // CIMPCS
1.28 -Field Clock_source_ddr (Divider_ddr, 3, 30); // DCS
1.29 -Field Clock_source_i2s (Divider0_i2s0, 1, 31); // I2PCS
1.30 -Field Clock_source_lcd (Divider_lcd, 3, 30); // LPCS
1.31 -Field Clock_source_mac (Divider_mac, 3, 30); // MACPCS
1.32 -Field Clock_source_msc0 (Divider_msc0, 3, 30); // MPCS
1.33 -Field Clock_source_msc1 (Divider_msc1, 3, 30); // MPCS
1.34 -Field Clock_source_pwm (Divider_pwm, 3, 30); // PWMPCS
1.35 -Field Clock_source_sfc (Divider_sfc, 3, 30); // SFCS
1.36 -Field Clock_source_ssi (Divider_ssi, 3, 30); // SPCS
1.37 -
1.38 -Field Clock_busy_cpu (Clock_status, 1, 0);
1.39 -Field Clock_busy_ddr (Divider_ddr, 1, 28);
1.40 -Field Clock_busy_mac (Divider_mac, 1, 28);
1.41 -Field Clock_busy_lcd (Divider_lcd, 1, 28);
1.42 -Field Clock_busy_msc0 (Divider_msc0, 1, 28);
1.43 -Field Clock_busy_msc1 (Divider_msc1, 1, 28);
1.44 -Field Clock_busy_sfc (Divider_sfc, 1, 28);
1.45 -Field Clock_busy_ssi (Divider_ssi, 1, 28);
1.46 -Field Clock_busy_cim (Divider_cim, 1, 28);
1.47 -Field Clock_busy_pwm (Divider_pwm, 1, 28);
1.48 -Field Clock_busy_can0 (Divider_can0, 1, 28);
1.49 -Field Clock_busy_can1 (Divider_can1, 1, 28);
1.50 -Field Clock_busy_cdbus (Divider_cdbus, 1, 28);
1.51 +static Field Clock_source_main (Clock_control, 3, 30), // SEL_SRC (output to SCLK_A)
1.52 + Clock_source_cpu (Clock_control, 3, 28), // SEL_CPLL (output to CCLK)
1.53 + Clock_source_hclock0 (Clock_control, 3, 26), // SEL_H0PLL (output to AHB0)
1.54 + Clock_source_hclock2 (Clock_control, 3, 24), // SEL_H2PLL (output to AHB2)
1.55 + Clock_source_can0 (Divider_can0, 3, 30), // CA0CS
1.56 + Clock_source_can1 (Divider_can1, 3, 30), // CA1CS
1.57 + Clock_source_cdbus (Divider_cdbus, 3, 30), // CDCS
1.58 + Clock_source_cim (Divider_cim, 3, 30), // CIMPCS
1.59 + Clock_source_ddr (Divider_ddr, 3, 30), // DCS
1.60 + Clock_source_i2s (Divider0_i2s0, 1, 31), // I2PCS
1.61 + Clock_source_lcd (Divider_lcd, 3, 30), // LPCS
1.62 + Clock_source_mac (Divider_mac, 3, 30), // MACPCS
1.63 + Clock_source_msc0 (Divider_msc0, 3, 30), // MPCS
1.64 + Clock_source_msc1 (Divider_msc1, 3, 30), // MPCS
1.65 + Clock_source_pwm (Divider_pwm, 3, 30), // PWMPCS
1.66 + Clock_source_sfc (Divider_sfc, 3, 30), // SFCS
1.67 + Clock_source_ssi (Divider_ssi, 3, 30), // SPCS
1.68
1.69 -Field Clock_change_enable_cpu (Clock_control, 1, 22);
1.70 -Field Clock_change_enable_ahb0 (Clock_control, 1, 21);
1.71 -Field Clock_change_enable_ahb2 (Clock_control, 1, 20);
1.72 -Field Clock_change_enable_ddr (Divider_ddr, 1, 29);
1.73 -Field Clock_change_enable_mac (Divider_mac, 1, 29);
1.74 -Field Clock_change_enable_i2s (Divider0_i2s0, 1, 29);
1.75 -Field Clock_change_enable_lcd (Divider_lcd, 1, 29);
1.76 -Field Clock_change_enable_msc0 (Divider_msc0, 1, 29);
1.77 -Field Clock_change_enable_msc1 (Divider_msc1, 1, 29);
1.78 -Field Clock_change_enable_sfc (Divider_sfc, 1, 29);
1.79 -Field Clock_change_enable_ssi (Divider_ssi, 1, 29);
1.80 -Field Clock_change_enable_cim (Divider_cim, 1, 29);
1.81 -Field Clock_change_enable_pwm (Divider_pwm, 1, 29);
1.82 -Field Clock_change_enable_can0 (Divider_can0, 1, 29);
1.83 -Field Clock_change_enable_can1 (Divider_can1, 1, 29);
1.84 -Field Clock_change_enable_cdbus (Divider_cdbus, 1, 29);
1.85 + Clock_busy_cpu (Clock_status, 1, 0),
1.86 + Clock_busy_ddr (Divider_ddr, 1, 28),
1.87 + Clock_busy_mac (Divider_mac, 1, 28),
1.88 + Clock_busy_lcd (Divider_lcd, 1, 28),
1.89 + Clock_busy_msc0 (Divider_msc0, 1, 28),
1.90 + Clock_busy_msc1 (Divider_msc1, 1, 28),
1.91 + Clock_busy_sfc (Divider_sfc, 1, 28),
1.92 + Clock_busy_ssi (Divider_ssi, 1, 28),
1.93 + Clock_busy_cim (Divider_cim, 1, 28),
1.94 + Clock_busy_pwm (Divider_pwm, 1, 28),
1.95 + Clock_busy_can0 (Divider_can0, 1, 28),
1.96 + Clock_busy_can1 (Divider_can1, 1, 28),
1.97 + Clock_busy_cdbus (Divider_cdbus, 1, 28),
1.98
1.99 -Field Clock_divider_can0 (Divider_can0, 0xff, 0); // CAN0CDR
1.100 -Field Clock_divider_can1 (Divider_can1, 0xff, 0); // CAN1CDR
1.101 -Field Clock_divider_cdbus (Divider_cdbus, 0xff, 0); // CDBUSCDR
1.102 -Field Clock_divider_cim (Divider_cim, 0xff, 0); // CIMCDR
1.103 -Field Clock_divider_cpu (Clock_control, 0x0f, 0); // CDIV
1.104 -Field Clock_divider_ddr (Divider_ddr, 0x0f, 0); // DDRCDR
1.105 -Field Clock_divider_hclock0 (Clock_control, 0x0f, 8); // H0DIV (fast AHB peripherals)
1.106 -Field Clock_divider_hclock2 (Clock_control, 0x0f, 12); // H2DIV (fast AHB peripherals)
1.107 -Field Clock_divider_l2cache (Clock_control, 0x0f, 4); // L2CDIV
1.108 -Field Clock_divider_lcd (Divider_lcd, 0xff, 0); // LPCDR
1.109 -Field Clock_divider_mac (Divider_mac, 0xff, 0); // MACCDR
1.110 -Field Clock_divider_msc0 (Divider_msc0, 0xff, 0); // MSC0CDR
1.111 -Field Clock_divider_msc1 (Divider_msc1, 0xff, 0); // MSC1CDR
1.112 -Field Clock_divider_pclock (Clock_control, 0x0f, 16); // PDIV (slow APB peripherals)
1.113 -Field Clock_divider_pwm (Divider_pwm, 0x0f, 0); // PWMCDR
1.114 -Field Clock_divider_sfc (Divider_sfc, 0xff, 0); // SFCCDR
1.115 -Field Clock_divider_ssi (Divider_ssi, 0xff, 0); // SSICDR
1.116 + Clock_change_enable_cpu (Clock_control, 1, 22),
1.117 + Clock_change_enable_ahb0 (Clock_control, 1, 21),
1.118 + Clock_change_enable_ahb2 (Clock_control, 1, 20),
1.119 + Clock_change_enable_ddr (Divider_ddr, 1, 29),
1.120 + Clock_change_enable_mac (Divider_mac, 1, 29),
1.121 + Clock_change_enable_i2s (Divider0_i2s0, 1, 29),
1.122 + Clock_change_enable_lcd (Divider_lcd, 1, 29),
1.123 + Clock_change_enable_msc0 (Divider_msc0, 1, 29),
1.124 + Clock_change_enable_msc1 (Divider_msc1, 1, 29),
1.125 + Clock_change_enable_sfc (Divider_sfc, 1, 29),
1.126 + Clock_change_enable_ssi (Divider_ssi, 1, 29),
1.127 + Clock_change_enable_cim (Divider_cim, 1, 29),
1.128 + Clock_change_enable_pwm (Divider_pwm, 1, 29),
1.129 + Clock_change_enable_can0 (Divider_can0, 1, 29),
1.130 + Clock_change_enable_can1 (Divider_can1, 1, 29),
1.131 + Clock_change_enable_cdbus (Divider_cdbus, 1, 29),
1.132
1.133 -Field Clock_gate_main (Clock_control, 1, 23); // GATE_SCLKA
1.134 -Field Clock_gate_ddr (Clock_gate0, 1, 31); // DDR
1.135 -Field Clock_gate_ahb0 (Clock_gate0, 1, 29); // AHB0
1.136 -Field Clock_gate_apb0 (Clock_gate0, 1, 28); // APB0
1.137 -Field Clock_gate_rtc (Clock_gate0, 1, 27); // RTC
1.138 -Field Clock_gate_aes (Clock_gate0, 1, 24); // AES
1.139 -Field Clock_gate_lcd_pixel (Clock_gate0, 1, 23); // LCD
1.140 -Field Clock_gate_cim (Clock_gate0, 1, 22); // CIM
1.141 -Field Clock_gate_dma (Clock_gate0, 1, 21); // PDMA
1.142 -Field Clock_gate_ost (Clock_gate0, 1, 20); // OST
1.143 -Field Clock_gate_ssi0 (Clock_gate0, 1, 19); // SSI0
1.144 -Field Clock_gate_timer (Clock_gate0, 1, 18); // TCU
1.145 -Field Clock_gate_dtrng (Clock_gate0, 1, 17); // DTRNG
1.146 -Field Clock_gate_uart2 (Clock_gate0, 1, 16); // UART2
1.147 -Field Clock_gate_uart1 (Clock_gate0, 1, 15); // UART1
1.148 -Field Clock_gate_uart0 (Clock_gate0, 1, 14); // UART0
1.149 -Field Clock_gate_sadc (Clock_gate0, 1, 13); // SADC
1.150 -Field Clock_gate_audio (Clock_gate0, 1, 11); // AUDIO
1.151 -Field Clock_gate_ssi_slv (Clock_gate0, 1, 10); // SSI_SLV
1.152 -Field Clock_gate_i2c1 (Clock_gate0, 1, 8); // I2C1
1.153 -Field Clock_gate_i2c0 (Clock_gate0, 1, 7); // I2C0
1.154 -Field Clock_gate_msc1 (Clock_gate0, 1, 5); // MSC1
1.155 -Field Clock_gate_msc0 (Clock_gate0, 1, 4); // MSC0
1.156 -Field Clock_gate_otg (Clock_gate0, 1, 3); // OTG
1.157 -Field Clock_gate_sfc (Clock_gate0, 1, 2); // SFC
1.158 -Field Clock_gate_efuse (Clock_gate0, 1, 1); // EFUSE
1.159 -Field Clock_gate_nemc (Clock_gate0, 1, 0); // NEMC
1.160 -Field Clock_gate_arb (Clock_gate1, 1, 30); // ARB
1.161 -Field Clock_gate_mipi_csi (Clock_gate1, 1, 28); // MIPI_CSI
1.162 -Field Clock_gate_intc (Clock_gate1, 1, 26); // INTC
1.163 -Field Clock_gate_gmac0 (Clock_gate1, 1, 23); // GMAC0
1.164 -Field Clock_gate_uart3 (Clock_gate1, 1, 16); // UART3
1.165 -Field Clock_gate_i2s0_tx (Clock_gate1, 1, 9); // I2S0_dev_tclk
1.166 -Field Clock_gate_i2s0_rx (Clock_gate1, 1, 8); // I2S0_dev_rclk
1.167 -Field Clock_gate_hash (Clock_gate1, 1, 6); // HASH
1.168 -Field Clock_gate_pwm (Clock_gate1, 1, 5); // PWM
1.169 -Field Clock_gate_cdbus (Clock_gate1, 1, 2); // CDBUS
1.170 -Field Clock_gate_can1 (Clock_gate1, 1, 1); // CAN1
1.171 -Field Clock_gate_can0 (Clock_gate1, 1, 0); // CAN0
1.172 + Clock_divider_can0 (Divider_can0, 0xff, 0), // CAN0CDR
1.173 + Clock_divider_can1 (Divider_can1, 0xff, 0), // CAN1CDR
1.174 + Clock_divider_cdbus (Divider_cdbus, 0xff, 0), // CDBUSCDR
1.175 + Clock_divider_cim (Divider_cim, 0xff, 0), // CIMCDR
1.176 + Clock_divider_cpu (Clock_control, 0x0f, 0), // CDIV
1.177 + Clock_divider_ddr (Divider_ddr, 0x0f, 0), // DDRCDR
1.178 + Clock_divider_hclock0 (Clock_control, 0x0f, 8), // H0DIV (fast AHB peripherals)
1.179 + Clock_divider_hclock2 (Clock_control, 0x0f, 12), // H2DIV (fast AHB peripherals)
1.180 + Clock_divider_i2s0_m (Divider0_i2s0, 0x1ff, 20), // I2SDIV_M
1.181 + Clock_divider_i2s0_n (Divider0_i2s0, 0xfffff, 0), // I2SDIV_N
1.182 + Clock_divider_i2s0_d (Divider1_i2s0, 0xfffff, 0), // I2SDIV_D
1.183 + Clock_divider_i2s1_m (Divider0_i2s1, 0x1ff, 20), // I2SDIV_M
1.184 + Clock_divider_i2s1_n (Divider0_i2s1, 0xfffff, 0), // I2SDIV_N
1.185 + Clock_divider_i2s1_d (Divider1_i2s1, 0xfffff, 0), // I2SDIV_D
1.186 + Clock_divider_l2cache (Clock_control, 0x0f, 4), // L2CDIV
1.187 + Clock_divider_lcd (Divider_lcd, 0xff, 0), // LPCDR
1.188 + Clock_divider_mac (Divider_mac, 0xff, 0), // MACCDR
1.189 + Clock_divider_msc0 (Divider_msc0, 0xff, 0), // MSC0CDR
1.190 + Clock_divider_msc1 (Divider_msc1, 0xff, 0), // MSC1CDR
1.191 + Clock_divider_pclock (Clock_control, 0x0f, 16), // PDIV (slow APB peripherals)
1.192 + Clock_divider_pwm (Divider_pwm, 0x0f, 0), // PWMCDR
1.193 + Clock_divider_sfc (Divider_sfc, 0xff, 0), // SFCCDR
1.194 + Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR
1.195
1.196 -Field Pll_enable_A (Pll_control_A, 1, 0); // APLLEN
1.197 -Field Pll_enable_E (Pll_control_E, 1, 0); // EPLLEN
1.198 -Field Pll_enable_M (Pll_control_M, 1, 0); // MPLLEN
1.199 -
1.200 -Field Pll_stable_A (Pll_control_A, 1, 3); // APLL_ON
1.201 -Field Pll_stable_E (Pll_control_E, 1, 3); // EPLL_ON
1.202 -Field Pll_stable_M (Pll_control_M, 1, 3); // MPLL_ON
1.203 -
1.204 -Field Pll_bypass_A (Pll_control_A, 1, 30); // APLL_BP
1.205 -Field Pll_bypass_E (Pll_control_E, 1, 26); // EPLL_BP
1.206 -Field Pll_bypass_M (Pll_control_M, 1, 28); // MPLL_BP
1.207 + Clock_gate_main (Clock_control, 1, 23), // GATE_SCLKA
1.208 + Clock_gate_ddr (Clock_gate0, 1, 31), // DDR
1.209 + Clock_gate_ahb0 (Clock_gate0, 1, 29), // AHB0
1.210 + Clock_gate_apb0 (Clock_gate0, 1, 28), // APB0
1.211 + Clock_gate_rtc (Clock_gate0, 1, 27), // RTC
1.212 + Clock_gate_aes (Clock_gate0, 1, 24), // AES
1.213 + Clock_gate_lcd_pixel (Clock_gate0, 1, 23), // LCD
1.214 + Clock_gate_cim (Clock_gate0, 1, 22), // CIM
1.215 + Clock_gate_dma (Clock_gate0, 1, 21), // PDMA
1.216 + Clock_gate_ost (Clock_gate0, 1, 20), // OST
1.217 + Clock_gate_ssi0 (Clock_gate0, 1, 19), // SSI0
1.218 + Clock_gate_timer (Clock_gate0, 1, 18), // TCU
1.219 + Clock_gate_dtrng (Clock_gate0, 1, 17), // DTRNG
1.220 + Clock_gate_uart2 (Clock_gate0, 1, 16), // UART2
1.221 + Clock_gate_uart1 (Clock_gate0, 1, 15), // UART1
1.222 + Clock_gate_uart0 (Clock_gate0, 1, 14), // UART0
1.223 + Clock_gate_sadc (Clock_gate0, 1, 13), // SADC
1.224 + Clock_gate_audio (Clock_gate0, 1, 11), // AUDIO
1.225 + Clock_gate_ssi_slv (Clock_gate0, 1, 10), // SSI_SLV
1.226 + Clock_gate_i2c1 (Clock_gate0, 1, 8), // I2C1
1.227 + Clock_gate_i2c0 (Clock_gate0, 1, 7), // I2C0
1.228 + Clock_gate_msc1 (Clock_gate0, 1, 5), // MSC1
1.229 + Clock_gate_msc0 (Clock_gate0, 1, 4), // MSC0
1.230 + Clock_gate_otg (Clock_gate0, 1, 3), // OTG
1.231 + Clock_gate_sfc (Clock_gate0, 1, 2), // SFC
1.232 + Clock_gate_efuse (Clock_gate0, 1, 1), // EFUSE
1.233 + Clock_gate_nemc (Clock_gate0, 1, 0), // NEMC
1.234 + Clock_gate_arb (Clock_gate1, 1, 30), // ARB
1.235 + Clock_gate_mipi_csi (Clock_gate1, 1, 28), // MIPI_CSI
1.236 + Clock_gate_intc (Clock_gate1, 1, 26), // INTC
1.237 + Clock_gate_gmac0 (Clock_gate1, 1, 23), // GMAC0
1.238 + Clock_gate_uart3 (Clock_gate1, 1, 16), // UART3
1.239 + Clock_gate_i2s0_tx (Clock_gate1, 1, 9), // I2S0_dev_tclk
1.240 + Clock_gate_i2s0_rx (Clock_gate1, 1, 8), // I2S0_dev_rclk
1.241 + Clock_gate_hash (Clock_gate1, 1, 6), // HASH
1.242 + Clock_gate_pwm (Clock_gate1, 1, 5), // PWM
1.243 + Clock_gate_cdbus (Clock_gate1, 1, 2), // CDBUS
1.244 + Clock_gate_can1 (Clock_gate1, 1, 1), // CAN1
1.245 + Clock_gate_can0 (Clock_gate1, 1, 0), // CAN0
1.246
1.247 -Field Pll_multiplier_A (Pll_control_A, 0x1fff, 20); // APLLM
1.248 -Field Pll_multiplier_E (Pll_control_E, 0x1fff, 20); // EPLLM
1.249 -Field Pll_multiplier_M (Pll_control_M, 0x1fff, 20); // MPLLM
1.250 + Pll_enable_A (Pll_control_A, 1, 0), // APLLEN
1.251 + Pll_enable_E (Pll_control_E, 1, 0), // EPLLEN
1.252 + Pll_enable_M (Pll_control_M, 1, 0), // MPLLEN
1.253
1.254 -Field Pll_input_division_A (Pll_control_A, 0x3f, 14); // APLLN
1.255 -Field Pll_input_division_E (Pll_control_E, 0x3f, 14); // EPLLN
1.256 -Field Pll_input_division_M (Pll_control_M, 0x3f, 14); // MPLLN
1.257 + Pll_stable_A (Pll_control_A, 1, 3), // APLL_ON
1.258 + Pll_stable_E (Pll_control_E, 1, 3), // EPLL_ON
1.259 + Pll_stable_M (Pll_control_M, 1, 3), // MPLL_ON
1.260 +
1.261 + Pll_bypass_A (Pll_control_A, 1, 30), // APLL_BP
1.262 + Pll_bypass_E (Pll_control_E, 1, 26), // EPLL_BP
1.263 + Pll_bypass_M (Pll_control_M, 1, 28), // MPLL_BP
1.264
1.265 -Field Pll_output_division1_A (Pll_control_A, 0x07, 11); // APLLOD1
1.266 -Field Pll_output_division1_E (Pll_control_E, 0x07, 11); // EPLLOD1
1.267 -Field Pll_output_division1_M (Pll_control_M, 0x07, 11); // MPLLOD1
1.268 + Pll_multiplier_A (Pll_control_A, 0x1fff, 20), // APLLM
1.269 + Pll_multiplier_E (Pll_control_E, 0x1fff, 20), // EPLLM
1.270 + Pll_multiplier_M (Pll_control_M, 0x1fff, 20), // MPLLM
1.271 +
1.272 + Pll_input_division_A (Pll_control_A, 0x3f, 14), // APLLN
1.273 + Pll_input_division_E (Pll_control_E, 0x3f, 14), // EPLLN
1.274 + Pll_input_division_M (Pll_control_M, 0x3f, 14), // MPLLN
1.275
1.276 -Field Pll_output_division0_A (Pll_control_A, 0x07, 8); // APLLOD0
1.277 -Field Pll_output_division0_E (Pll_control_E, 0x07, 8); // EPLLOD0
1.278 -Field Pll_output_division0_M (Pll_control_M, 0x07, 8); // MPLLOD0
1.279 + Pll_output_division1_A (Pll_control_A, 0x07, 11), // APLLOD1
1.280 + Pll_output_division1_E (Pll_control_E, 0x07, 11), // EPLLOD1
1.281 + Pll_output_division1_M (Pll_control_M, 0x07, 11), // MPLLOD1
1.282 +
1.283 + Pll_output_division0_A (Pll_control_A, 0x07, 8), // APLLOD0
1.284 + Pll_output_division0_E (Pll_control_E, 0x07, 8), // EPLLOD0
1.285 + Pll_output_division0_M (Pll_control_M, 0x07, 8); // MPLLOD0
1.286
1.287
1.288
1.289 @@ -248,195 +256,127 @@
1.290
1.291 Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2));
1.292
1.293 -Clock clock_aic_bitclk;
1.294 -
1.295 -Clock clock_aic_pclk;
1.296 -
1.297 Clock clock_can0(Source(mux_bus, Clock_source_can0),
1.298 - Clock_gate_can0,
1.299 - Clock_change_enable_can0,
1.300 - Clock_busy_can0,
1.301 + Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
1.302 Divider(Clock_divider_can0));
1.303
1.304 Clock clock_can1(Source(mux_bus, Clock_source_can1),
1.305 - Clock_gate_can1,
1.306 - Clock_change_enable_can1,
1.307 - Clock_busy_can1,
1.308 + Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
1.309 Divider(Clock_divider_can1));
1.310
1.311 Clock clock_cdbus(Source(mux_dev, Clock_source_cdbus),
1.312 - Clock_gate_cdbus,
1.313 - Clock_change_enable_cdbus,
1.314 - Clock_busy_cdbus,
1.315 + Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
1.316 Divider(Clock_divider_cdbus));
1.317
1.318 Clock clock_cim(Source(mux_dev, Clock_source_cim),
1.319 - Clock_gate_cim,
1.320 - Clock_change_enable_cim,
1.321 - Clock_busy_cim,
1.322 + Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
1.323 Divider(Clock_divider_cim));
1.324
1.325 Clock clock_cpu(Source(mux_core, Clock_source_cpu),
1.326 - Field::undefined,
1.327 - Clock_change_enable_cpu,
1.328 - Clock_busy_cpu,
1.329 + Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
1.330 Divider(Clock_divider_cpu));
1.331
1.332 Clock clock_ddr(Source(mux_core, Clock_source_ddr),
1.333 - Clock_gate_ddr,
1.334 - Clock_change_enable_ddr,
1.335 - Clock_busy_ddr,
1.336 + Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
1.337 Divider(Clock_divider_ddr));
1.338
1.339 -Clock clock_dma(Source(mux_pclock), Clock_gate_dma);
1.340 +Clock clock_dma(Source(mux_pclock), Control(Clock_gate_dma), Divider::undefined);
1.341
1.342 -Clock clock_emac;
1.343 -
1.344 -Clock clock_external;
1.345 +Clock_passive clock_external;
1.346
1.347 Clock clock_hclock0(Source(mux_core, Clock_source_hclock0),
1.348 - Clock_gate_ahb0,
1.349 - Clock_change_enable_ahb0,
1.350 - Field::undefined,
1.351 + Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
1.352 Divider(Clock_divider_hclock0));
1.353
1.354 Clock clock_hclock2(Source(mux_ahb2_apb),
1.355 - Clock_gate_apb0,
1.356 - Clock_change_enable_ahb2,
1.357 - Field::undefined,
1.358 + Control(Clock_gate_apb0, Clock_change_enable_ahb2),
1.359 Divider(Clock_divider_hclock2));
1.360
1.361 -Clock clock_hdmi;
1.362 -
1.363 -Clock clock_i2c(Source(mux_pclock), Clock_gate_i2c0);
1.364 +Clock clock_i2c(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined);
1.365
1.366 -Clock clock_i2c0(Source(mux_pclock), Clock_gate_i2c0);
1.367 +Clock clock_i2c0(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined);
1.368
1.369 -Clock clock_i2c1(Source(mux_pclock), Clock_gate_i2c1);
1.370 -
1.371 -Clock clock_i2s;
1.372 +Clock clock_i2c1(Source(mux_pclock), Control(Clock_gate_i2c1), Divider::undefined);
1.373
1.374 -Clock clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
1.375 - Clock_gate_i2s0_rx,
1.376 - Clock_change_enable_i2s);
1.377 +Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
1.378 + Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s),
1.379 + Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
1.380 + Clock_divider_i2s0_d));
1.381
1.382 -Clock clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s),
1.383 - Clock_gate_i2s0_tx,
1.384 - Clock_change_enable_i2s);
1.385 -
1.386 -Clock clock_kbc;
1.387 -
1.388 -Clock clock_lcd;
1.389 +Clock_divided_i2s clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s),
1.390 + Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s),
1.391 + Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
1.392 + Clock_divider_i2s1_d));
1.393
1.394 Clock clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
1.395 - Clock_gate_lcd_pixel,
1.396 - Clock_change_enable_lcd,
1.397 - Clock_busy_lcd,
1.398 + Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
1.399 Divider(Clock_divider_lcd));
1.400
1.401 Clock clock_mac(Source(mux_dev, Clock_source_mac),
1.402 - Clock_gate_gmac0,
1.403 - Clock_change_enable_mac,
1.404 - Clock_busy_mac,
1.405 + Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
1.406 Divider(Clock_divider_mac));
1.407
1.408 Clock clock_main(Source(mux_core, Clock_source_main),
1.409 - Clock_gate_main);
1.410 + Control(Clock_gate_main));
1.411
1.412 Clock clock_msc(Source(mux_dev, Clock_source_msc0),
1.413 - Clock_gate_msc0,
1.414 - Clock_change_enable_msc0,
1.415 - Clock_busy_msc0,
1.416 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.417 Divider(Clock_divider_msc0));
1.418
1.419 Clock clock_msc0(Source(mux_dev, Clock_source_msc0),
1.420 - Clock_gate_msc0,
1.421 - Clock_change_enable_msc0,
1.422 - Clock_busy_msc0,
1.423 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.424 Divider(Clock_divider_msc0));
1.425
1.426 Clock clock_msc1(Source(mux_dev, Clock_source_msc1),
1.427 - Clock_gate_msc1,
1.428 - Clock_change_enable_msc1,
1.429 - Clock_busy_msc1,
1.430 + Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
1.431 Divider(Clock_divider_msc1));
1.432
1.433 -Clock clock_none;
1.434 +Clock_null clock_none;
1.435
1.436 Clock clock_pclock(Source(mux_ahb2_apb),
1.437 - Clock_gate_apb0,
1.438 - Field::undefined,
1.439 - Field::undefined,
1.440 + Control(Clock_gate_apb0, Field::undefined, Field::undefined),
1.441 Divider(Clock_divider_pclock));
1.442
1.443 Pll clock_pll_A(Source(mux_external),
1.444 - Pll_enable_A, Pll_stable_A, Pll_bypass_A,
1.445 + Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
1.446 Divider_pll(Pll_multiplier_A, Pll_input_division_A,
1.447 Pll_output_division0_A, Pll_output_division1_A));
1.448
1.449 Pll clock_pll_E(Source(mux_external),
1.450 - Pll_enable_E, Pll_stable_E, Pll_bypass_E,
1.451 + Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
1.452 Divider_pll(Pll_multiplier_E, Pll_input_division_E,
1.453 Pll_output_division0_E, Pll_output_division1_E));
1.454
1.455 Pll clock_pll_M(Source(mux_external),
1.456 - Pll_enable_M, Pll_stable_M, Pll_bypass_M,
1.457 + Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
1.458 Divider_pll(Pll_multiplier_M, Pll_input_division_M,
1.459 Pll_output_division0_M, Pll_output_division1_M));
1.460
1.461 Clock clock_pwm(Source(mux_dev, Clock_source_pwm),
1.462 - Clock_gate_pwm,
1.463 - Clock_change_enable_pwm,
1.464 - Clock_busy_pwm,
1.465 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.466 Divider(Clock_divider_pwm));
1.467
1.468 Clock clock_pwm0(Source(mux_dev, Clock_source_pwm),
1.469 - Clock_gate_pwm,
1.470 - Clock_change_enable_pwm,
1.471 - Clock_busy_pwm,
1.472 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.473 Divider(Clock_divider_pwm));
1.474
1.475 -Clock clock_pwm1;
1.476 -
1.477 -Clock clock_scc;
1.478 -
1.479 Clock clock_sfc(Source(mux_dev, Clock_source_sfc),
1.480 - Clock_gate_sfc,
1.481 - Clock_change_enable_sfc,
1.482 - Clock_busy_sfc,
1.483 + Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
1.484 Divider(Clock_divider_sfc));
1.485
1.486 -Clock clock_smb0;
1.487 -
1.488 -Clock clock_smb1;
1.489 -
1.490 -Clock clock_smb2;
1.491 -
1.492 -Clock clock_smb3;
1.493 -
1.494 -Clock clock_smb4;
1.495 -
1.496 Clock clock_ssi(Source(mux_dev, Clock_source_ssi),
1.497 - Clock_gate_ssi0,
1.498 - Clock_change_enable_ssi,
1.499 - Clock_busy_ssi,
1.500 + Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
1.501 Divider(Clock_divider_ssi));
1.502
1.503 -Clock clock_timer(Source(mux_pclock), Clock_gate_timer);
1.504 -
1.505 -Clock clock_uart0(Source(mux_external), Clock_gate_uart0);
1.506 +Clock clock_timer(Source(mux_pclock), Control(Clock_gate_timer), Divider::undefined);
1.507
1.508 -Clock clock_uart1(Source(mux_external), Clock_gate_uart1);
1.509 -
1.510 -Clock clock_uart2(Source(mux_external), Clock_gate_uart2);
1.511 +Clock clock_uart0(Source(mux_external), Control(Clock_gate_uart0), Divider::undefined);
1.512
1.513 -Clock clock_uart3(Source(mux_external), Clock_gate_uart3);
1.514 -
1.515 -Clock clock_udc;
1.516 +Clock clock_uart1(Source(mux_external), Control(Clock_gate_uart1), Divider::undefined);
1.517
1.518 -Clock clock_uhc;
1.519 +Clock clock_uart2(Source(mux_external), Control(Clock_gate_uart2), Divider::undefined);
1.520
1.521 -Clock clock_uprt;
1.522 +Clock clock_uart3(Source(mux_external), Control(Clock_gate_uart3), Divider::undefined);
1.523
1.524
1.525
1.526 @@ -444,8 +384,8 @@
1.527
1.528 static Clock_base *clocks[Clock_identifier_count] = {
1.529 &clock_ahb2_apb,
1.530 - &clock_aic_bitclk,
1.531 - &clock_aic_pclk,
1.532 + &clock_none, // Clock_aic_bitclk
1.533 + &clock_none, // Clock_aic_pclk
1.534 &clock_can0,
1.535 &clock_can1,
1.536 &clock_cdbus,
1.537 @@ -453,19 +393,19 @@
1.538 &clock_cpu,
1.539 &clock_ddr,
1.540 &clock_dma,
1.541 - &clock_emac,
1.542 + &clock_none, // Clock_emac
1.543 &clock_external,
1.544 &clock_hclock0,
1.545 &clock_hclock2,
1.546 - &clock_hdmi,
1.547 + &clock_none, // Clock_hdmi
1.548 &clock_i2c,
1.549 &clock_i2c0,
1.550 &clock_i2c1,
1.551 - &clock_i2s,
1.552 + &clock_none, // Clock_i2s
1.553 &clock_i2s0_rx,
1.554 &clock_i2s0_tx,
1.555 - &clock_kbc,
1.556 - &clock_lcd,
1.557 + &clock_none, // Clock_kbc
1.558 + &clock_none, // Clock_lcd
1.559 &clock_lcd_pixel,
1.560 &clock_mac,
1.561 &clock_main,
1.562 @@ -479,23 +419,23 @@
1.563 &clock_pll_M,
1.564 &clock_pwm,
1.565 &clock_pwm0,
1.566 - &clock_pwm1,
1.567 - &clock_scc,
1.568 + &clock_none, // Clock_pwm1
1.569 + &clock_none, // Clock_scc
1.570 &clock_sfc,
1.571 - &clock_smb0,
1.572 - &clock_smb1,
1.573 - &clock_smb2,
1.574 - &clock_smb3,
1.575 - &clock_smb4,
1.576 + &clock_none, // Clock_smb0
1.577 + &clock_none, // Clock_smb1
1.578 + &clock_none, // Clock_smb2
1.579 + &clock_none, // Clock_smb3
1.580 + &clock_none, // Clock_smb4
1.581 &clock_ssi,
1.582 &clock_timer,
1.583 &clock_uart0,
1.584 &clock_uart1,
1.585 &clock_uart2,
1.586 &clock_uart3,
1.587 - &clock_udc,
1.588 - &clock_uhc,
1.589 - &clock_uprt,
1.590 + &clock_none, // Clock_udc
1.591 + &clock_none, // Clock_uhc
1.592 + &clock_none, // Clock_uprt
1.593 };
1.594
1.595
1.596 @@ -533,31 +473,52 @@
1.597 uint32_t
1.598 Cpm_x1600_chip::get_divider(enum Clock_identifiers clock)
1.599 {
1.600 - return clocks[clock]->get_divider(_cpm_regs);
1.601 + Clock *clk = dynamic_cast<Clock *>(clocks[clock]);
1.602 +
1.603 + if (clk != NULL)
1.604 + return clk->get_divider(_cpm_regs);
1.605 + else
1.606 + return 1;
1.607 }
1.608
1.609 void
1.610 Cpm_x1600_chip::set_divider(enum Clock_identifiers clock, uint32_t division)
1.611 {
1.612 - clocks[clock]->set_divider(_cpm_regs, division);
1.613 + Clock *clk = dynamic_cast<Clock *>(clocks[clock]);
1.614 +
1.615 + if (clk != NULL)
1.616 + clk->set_divider(_cpm_regs, division);
1.617 }
1.618
1.619 uint8_t
1.620 Cpm_x1600_chip::get_source(enum Clock_identifiers clock)
1.621 {
1.622 - return clocks[clock]->get_source(_cpm_regs);
1.623 + Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]);
1.624 +
1.625 + if (clk != NULL)
1.626 + return clk->get_source(_cpm_regs);
1.627 + else
1.628 + return 0;
1.629 }
1.630
1.631 void
1.632 Cpm_x1600_chip::set_source(enum Clock_identifiers clock, uint8_t source)
1.633 {
1.634 - clocks[clock]->set_source(_cpm_regs, source);
1.635 + Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]);
1.636 +
1.637 + if (clk != NULL)
1.638 + clk->set_source(_cpm_regs, source);
1.639 }
1.640
1.641 uint32_t
1.642 Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock)
1.643 {
1.644 - return clocks[clock]->get_source_frequency(_cpm_regs);
1.645 + Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]);
1.646 +
1.647 + if (clk != NULL)
1.648 + return clk->get_source_frequency(_cpm_regs);
1.649 + else
1.650 + return 0;
1.651 }
1.652
1.653 uint32_t
1.654 @@ -579,12 +540,15 @@
1.655
1.656 // Switch to the MPLL and attempt to set the divider.
1.657
1.658 - Clock_base *lcd = clocks[Clock_lcd_pixel];
1.659 + Clock *lcd = dynamic_cast<Clock *>(clocks[Clock_lcd_pixel]);
1.660 Clock_base *pll = clocks[Clock_pll_M];
1.661
1.662 - lcd->set_source(_cpm_regs, Source_mME_pll_M);
1.663 - pll->start_clock(_cpm_regs);
1.664 - lcd->set_divider(_cpm_regs, lcd->get_source_frequency(_cpm_regs) / frequency);
1.665 + if (lcd != NULL)
1.666 + {
1.667 + lcd->set_source(_cpm_regs, Source_mME_pll_M);
1.668 + pll->start_clock(_cpm_regs);
1.669 + lcd->set_divider(_cpm_regs, lcd->get_source_frequency(_cpm_regs) / frequency);
1.670 + }
1.671 break;
1.672 }
1.673
1.674 @@ -599,7 +563,8 @@
1.675 {
1.676 Pll *pll = dynamic_cast<Pll *>(clocks[clock]);
1.677
1.678 - pll->set_pll_parameters(_cpm_regs, multiplier, in_divider, out_divider);
1.679 + if (pll != NULL)
1.680 + pll->set_parameters(_cpm_regs, multiplier, in_divider, out_divider);
1.681 }
1.682
1.683